GB9917129D0 - Setting condition values in a computer - Google Patents

Setting condition values in a computer

Info

Publication number
GB9917129D0
GB9917129D0 GBGB9917129.0A GB9917129A GB9917129D0 GB 9917129 D0 GB9917129 D0 GB 9917129D0 GB 9917129 A GB9917129 A GB 9917129A GB 9917129 D0 GB9917129 D0 GB 9917129D0
Authority
GB
United Kingdom
Prior art keywords
computer
setting condition
condition values
condition setting
setting indicator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9917129.0A
Other versions
GB2355084A (en
GB2355084B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Element 14 Ltd
Original Assignee
Element 14 Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Element 14 Ltd filed Critical Element 14 Ltd
Priority to GB9917129A priority Critical patent/GB2355084B/en
Priority to US09/395,298 priority patent/US6530012B1/en
Publication of GB9917129D0 publication Critical patent/GB9917129D0/en
Priority to PCT/GB2000/002765 priority patent/WO2001006354A1/en
Priority to EP00946143A priority patent/EP1206737B1/en
Priority to AU60023/00A priority patent/AU6002300A/en
Priority to DE60018078T priority patent/DE60018078T2/en
Priority to AT00946143T priority patent/ATE289092T1/en
Publication of GB2355084A publication Critical patent/GB2355084A/en
Priority to US10/303,600 priority patent/US6918031B2/en
Application granted granted Critical
Publication of GB2355084B publication Critical patent/GB2355084B/en
Priority to US11/123,119 priority patent/US7441098B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards

Abstract

A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether or not multibit condition codes are set. When they are to be set, they are set depending on the results for carrying out the operation for each lane.
GB9917129A 1999-07-21 1999-07-21 Setting condition values in a computer Expired - Fee Related GB2355084B (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
GB9917129A GB2355084B (en) 1999-07-21 1999-07-21 Setting condition values in a computer
US09/395,298 US6530012B1 (en) 1999-07-21 1999-09-13 Setting condition values in a computer
AT00946143T ATE289092T1 (en) 1999-07-21 2000-07-18 SETTING CONDITIONAL VALUES IN A CALCULATOR
EP00946143A EP1206737B1 (en) 1999-07-21 2000-07-18 Setting condition values in a computer
AU60023/00A AU6002300A (en) 1999-07-21 2000-07-18 Setting condition values in a computer
DE60018078T DE60018078T2 (en) 1999-07-21 2000-07-18 SETTING CONDITIONAL VALUES IN A COMPUTER
PCT/GB2000/002765 WO2001006354A1 (en) 1999-07-21 2000-07-18 Setting condition values in a computer
US10/303,600 US6918031B2 (en) 1999-07-21 2002-11-25 Setting condition values in a computer
US11/123,119 US7441098B2 (en) 1999-07-21 2005-05-06 Conditional execution of instructions in a computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9917129A GB2355084B (en) 1999-07-21 1999-07-21 Setting condition values in a computer

Publications (3)

Publication Number Publication Date
GB9917129D0 true GB9917129D0 (en) 1999-09-22
GB2355084A GB2355084A (en) 2001-04-11
GB2355084B GB2355084B (en) 2004-04-28

Family

ID=10857676

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9917129A Expired - Fee Related GB2355084B (en) 1999-07-21 1999-07-21 Setting condition values in a computer

Country Status (7)

Country Link
US (3) US6530012B1 (en)
EP (1) EP1206737B1 (en)
AT (1) ATE289092T1 (en)
AU (1) AU6002300A (en)
DE (1) DE60018078T2 (en)
GB (1) GB2355084B (en)
WO (1) WO2001006354A1 (en)

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AU2003256870A1 (en) * 2002-08-09 2004-02-25 Intel Corporation Multimedia coprocessor control mechanism including alignment or broadcast instructions
US7002595B2 (en) * 2002-10-04 2006-02-21 Broadcom Corporation Processing of color graphics data
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US7346763B2 (en) * 2004-06-02 2008-03-18 Broadcom Corporation Processor instruction with repeated execution code
US7216218B2 (en) * 2004-06-02 2007-05-08 Broadcom Corporation Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
US7747843B2 (en) * 2004-06-02 2010-06-29 Broadcom Corporation Microprocessor with integrated high speed memory
US7565514B2 (en) * 2006-04-28 2009-07-21 Freescale Semiconductor, Inc. Parallel condition code generation for SIMD operations
JP2008071130A (en) * 2006-09-14 2008-03-27 Ricoh Co Ltd Simd type microprocessor
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
JP5304239B2 (en) * 2008-12-26 2013-10-02 富士通株式会社 Processor test apparatus, processor test method, processor test program
US8819399B1 (en) 2009-07-31 2014-08-26 Google Inc. Predicated control flow and store instructions for native code module security
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US8880857B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
EP2624126B1 (en) * 2011-04-07 2016-11-02 VIA Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US8924695B2 (en) 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9344366B2 (en) 2011-08-02 2016-05-17 Cavium, Inc. System and method for rule matching in a processor
US20140280271A1 (en) * 2013-03-15 2014-09-18 Intel Corporation Instruction and logic for processing text strings
US9544402B2 (en) 2013-12-31 2017-01-10 Cavium, Inc. Multi-rule approach to encoding a group of rules
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US9684514B2 (en) 2014-09-10 2017-06-20 International Business Machines Corporation Inference based condition code generation
US10402199B2 (en) * 2015-10-22 2019-09-03 Texas Instruments Incorporated Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
US11593105B2 (en) * 2018-12-29 2023-02-28 Intel Corporation Vector logical operation and test instructions with result negation

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Also Published As

Publication number Publication date
DE60018078T2 (en) 2006-05-04
US6918031B2 (en) 2005-07-12
GB2355084A (en) 2001-04-11
US20030079108A1 (en) 2003-04-24
US6530012B1 (en) 2003-03-04
US7441098B2 (en) 2008-10-21
US20050198478A1 (en) 2005-09-08
ATE289092T1 (en) 2005-02-15
EP1206737A1 (en) 2002-05-22
WO2001006354A1 (en) 2001-01-25
GB2355084B (en) 2004-04-28
EP1206737B1 (en) 2005-02-09
AU6002300A (en) 2001-02-05
DE60018078D1 (en) 2005-03-17

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Legal Events

Date Code Title Description
COOA Change in applicant's name or ownership of the application
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20140721