GB763735A - Improvements in or relating to electronic circuits embodying transistors - Google Patents

Abstract

763,735. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Dec. 16, 1954 [Dec. 17,1953], No. 35209/53. Class 106 (1). [Also in Group XL (c)] A number of two-state transistor circuits are combined to indicate the presence of none, one, some or all of a number of input signals. The input signals may be of pulse form occurring simultaneously or sequentially in an electronic digital computer. Each transistor operates in a circuit of the type described in Specification 747,606 in which two of the electrodes are supplied from constant current sources in the on condition and are limited to certain potential levels in the off condition. In the on condition, the electrodes of transistor T1, Fig. 1, are all near the collector potential while in the off state the emitter is held near earth due to diode D5 conducting, diode D1 holding the base near +2. In the on condition of transistors T2, T3, T4 the electrodes are all near the collector potentials which are biased increasingly negative. Clock pulses a and signal pulses band c are applied to the cathodes of diodes D1, D2, D3, the pulses band c also being fed through an and gate to diode D4. An a pulse triggers transistor T1 on to indicate that no signals has been received but if either b or c is applied the current through resistor R1 is diverted to transistor T2 or T3, transistor T1 remaining in the off state. When both a band c are received transistor T4 operates, biasing off the emitters of the other transistors. The circuit is reset by a negative pulse applied to the cathode of diode D5, and output pulses may be derived from the bases of the transistors. In a modification, Fig. 3 (not shown), loads are arranged in the collector leads to give larger output currents. In a further modification, Fig. 4, for serial operation a diode gate D14, D15 and D16 is arranged between transistors T11 and T12. Transistor T9 operates in each case and is reset by operation of T 10 or T11. When pulse b is followed by c, the latter passes through diodes D14, D15 since diode D16 is biased off due to the fall in emitter potential of transistor T10. Transistor T12 passes to the on state, resetting the other transistors. Positive input pulses. A positive a pulse, Fig. 7, allows the anode of diode D17 to rise carrying the emitter temporarily positive to switch transistor T13 on, the base and collector becoming slightly negative with respect to earth. In a similar manner, inputs band c are effective to switch on transistors T14 and T15, the rise in collector potential of either raising the anode potential of the corresponding diode D18 to feed a positive resetting pulse to the base of transistor T13. The collectors of transistors T14, T15 are also connected over diodes forming an and gate to the input of transistor T16. When both band c pulses occur the transistors T14, T15 trigger transistor T16. The circuit is reset by pulses applied over diodes to all the bases and outputs are taken from the collectors.