GB2558973A

GB2558973A - Offset calibration for amplifier and preceding circuit

Info

Publication number: GB2558973A
Application number: GB1712743.2A
Authority: GB
Inventors: Zhu Lei; He Ku; Zhao Xin; Song Miao; Singh Saurabh; Jayakumar Vinod
Original assignee: Cirrus Logic International Semiconductor Ltd
Current assignee: Cirrus Logic International Semiconductor Ltd
Priority date: 2017-01-20
Filing date: 2017-08-09
Publication date: 2018-07-25
Anticipated expiration: 2037-08-09
Also published as: US20180212569A1; GB201712743D0; CN110326215A; WO2018136682A1; GB2558973B; CN110326215B; US10236827B2

Abstract

An apparatus, and method of operation, comprises a closed loop amplifier 16, a signal processing block 14 generating an amplifier input signal VIN from a received input signal, and a calibration subsystem 28. The amplifier, e.g. audio amplifier, includes a first stage 22 generating an intermediate signal VINT from the received input signal, a second stage 42 generating an output signal VOUT from the intermediate signal, and an input network 24 and feedback network 26 configured to set a gain of the amplifier. In a calibration mode, the calibration subsystem decouples the first stage output from the second stage input, and determines an offset signal (CAL) that, when applied to the input of the signal processing block, generates approximately zero as the intermediate signal. The offset signal may be determined at two different amplifier gains. Based on the offset signal, one or more parameters of the apparatus are controlled by the calibration subsystem to compensate for an offset of at least one of the first stage and signal processing block. The amplifier second stage may be class-D or class-AB. After determining the first offset signal, the calibration subsystem may determine a second offset signal that generates zero as the intermediate signal by electrically shorting the second stage output and overdriving a common mode voltage.

Description

(54) Title of the Invention: Offset calibration for amplifier and preceding circuit

Abstract Title: Apparatus and method for offset calibration in an amplifier and associated input signal processing block (57) An apparatus, and method of operation, comprises a closed loop amplifier 16, a signal processing block 14 generating an amplifier input signal V,_N from a received input signal, and a calibration subsystem 28. The amplifier, e.g. audio amplifier, includes a first stage 22 generating an intermediate signal V|_NT from the received input signal, a second stage 42 generating an output signal V_Out from the intermediate signal, and an input network 24 and feedback network 26 configured to set a gain of the amplifier. In a calibration mode, the calibration subsystem decouples the first stage output from the second stage input, and determines an offset signal (CAL) that, when applied to the input of the signal processing block, generates approximately zero as the intermediate signal. The offset signal may be determined at two different amplifier gains. Based on the offset signal, one or more parameters of the apparatus are controlled by the calibration subsystem to compensate for an offset of at least one of the first stage and signal processing block. The amplifier second stage may be class-D or class-AB. After determining the first offset signal, the calibration subsystem may determine a second offset signal that generates zero as the intermediate signal by electrically shorting the second stage output and overdriving a common mode voltage.

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FIG. 3

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FIG. 2

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FIG. 3

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OFFSET CALIBRATION FOR AMPLIFIER AND PRECEDING CIRCUIT

RELATED APPLICATION

The present disclosure claims priority to United States Provisional Patent 5 Application Serial No. 62/448,490, filed January 20, 2017, which is incorporated by reference herein in its entirety.

FIELD OF DISCLOSURE

The present disclosure relates in general to circuits for audio devices, including 10 without limitation personal audio devices, such as wireless telephones and media players, and more specifically, to systems and methods relating to calibrating offset for an amplifier and a circuit preceding the amplifier in a signal path.

BACKGROUND

Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a power amplifier for driving an audio output signal to headphones or speakers. Generally speaking, a power amplifier amplifies an audio signal by taking energy from a power supply and controlling an audio output signal to match an input signal shape but with a larger amplitude.

One example of an audio amplifier is a class-D amplifier. A class-D amplifier (also known as a “switching amplifier”) may comprise an electronic amplifier in which the amplifying devices (e.g., transistors, typically metal-oxide-semiconductor field effect transistors) operate as electronic switches. In a class-D amplifier, an analog signal to be amplified may be converted to a series of pulses by pulse-width modulation, pulsedensity modulation, or another method of modulation, such that the analog signal is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of the analog signal. After amplification with a class-D amplifier, the output pulse train may be converted back to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in the class-D amplifier or a load driven by the class-D amplifier. Class-D amplifiers are often used due to the fact that they may be more power efficient than linear analog amplifiers, in that class-D amplifiers may dissipate less power as heat in active devices as compared to linear analog amplifiers.

In a class-D amplifier, signal offset may be present due to a circuit (e.g., a digitalto-analog converter) preceding the amplifier, an input stage of the amplifier, and input impedances and feedback resistances that add offset due to varying common mode voltages. Other types of amplifiers may experience offset due to one or more of the same reasons. For high performance of a circuit comprising an amplifier, it may be desirable to calibrate and correct for such sources of offset.

SUMMARY

In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to offset calibration associated with an amplifier may be reduced or eliminated.

In accordance with embodiments of the present disclosure, an apparatus may include a closed loop amplifier, a signal processing block, and a calibration subsystem. The closed loop amplifier may include a first stage configured to receive an amplifier input signal at an amplifier input and generate at a first stage output an intermediate signal which is a function of the amplifier input signal, a second stage configured to receive the intermediate signal at a second stage input and configured to generate at a second stage output an output signal from the intermediate signal which is a function of the amplifier input signal, and an input network and a feedback network configured to set a gain of the closed loop amplifier. The signal processing block may be configured to generate the amplifier input signal as a function of an upstream signal received at an input of the signal processing block. The calibration subsystem may be configured to, in a calibration mode, decouple the second stage input from the first stage output, determine an offset signal that when applied to the input of the signal processing block as the upstream signal generates approximately zero as the intermediate signal, and control one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

In accordance with these and other embodiments of the present disclosure, a method may include, in an apparatus comprising a closed loop amplifier having a first stage configured to receive an amplifier input signal at an amplifier input and generate at a first stage output an intermediate signal which is a function of the amplifier input signal, a second stage configured to receive the intermediate signal at a second stage input and configured to generate at a second stage output an output signal from the intermediate signal which is a function of the amplifier input signal, and an input network and a feedback network configured to set a gain of the closed loop amplifier, and the apparatus also having a signal processing block configured to generate the amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling the second stage input from the first stage output; determining an offset signal that when applied to the input of the signal processing block as the upstream signal generates approximately zero as the intermediate signal; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

FIGURE 1 is an illustration of an example personal audio device, in accordance with embodiments of the present disclosure;

FIGURE 2 is a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure;

FIGURE 3 is a block diagram of selected components of the example audio integrated circuit shown in FIGURE 2 with a calibration circuit and additional detail regarding an amplifier of the audio integrated circuit, in accordance with embodiments of the present disclosure; and

FIGURE 4 is a flow chart of an example method for offset calibration in a circuit comprising an amplifier, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

FIGURE 1 is an illustration of an example personal audio device 1, in accordance with embodiments of the present disclosure. FIGETRE 1 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8 A and 8B. Headset 3 depicted in FIGETRE 1 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1. Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1. As also shown in FIGURE 1, personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer.

FIGURE 2 is a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure. In some embodiments, example audio IC 9 may be used to implement audio IC 9 of FIGURE 1. As shown in FIGURE 2, a microcontroller core 18 may supply a digital audio input signal DIG IN to a digital-to-analog converter (DAC) 14, which may convert the digital audio input signal to an analog input signal Vin. DAC 14 may supply analog signal Vin to an amplifier 16 which may amplify or attenuate analog input signal Vin to provide an audio output signal Vout, which may operate a speaker, headphone transducer, a line level signal output, and/or other suitable output.

FIGURE 3 is a block diagram of selected components of example audio IC 9 shown in FIGURE 2 with a calibration subsystem 28 and additional detail regarding amplifier 16, in accordance with embodiments of the present disclosure. As shown in FIGURE 3, amplifier 16 may include a first stage 22 (e.g., an analog front end) configured to receive analog input signal Vin at an amplifier input of amplifier 16 and generate an intermediate signal Vint which is a function of analog input signal Vin, a final output stage comprising a class-D audio output stage 42 configured to generate audio output signal Vout at an amplifier output of amplifier 16 as a function of intermediate signal Vint, an input network 24 at the amplifier input, and a signal feedback network 26 coupled between the amplifier output and the amplifier input. Also as depicted in FIGURE 3, audio IC 9 may include calibration subsystem 28 for calibration of offset in the audio signal path of audio IC 9, as described in greater detail below.

First stage 22 may include any suitable analog front end circuit for conditioning analog input signal Vin for use by class-D audio output stage 42. For example, first stage 22 may include one or more analog integrators 32 cascaded in series, as shown in FIGURE 3.

Class-D audio output stage 42 may include any suitable driving circuit for driving audio output signal Vout as a function of intermediate signal Vint (thus, also making audio output signal Vout a function of analog input signal Vin). For example, class-D audio output stage 42 may comprise any suitable system, device, or apparatus configured to amplify intermediate signal Vint and convert intermediate signal Vint into a series of pulses by pulse-width modulation, pulse-density modulation, or another method of modulation, such that intermediate signal Vint is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of intermediate signal Vint. After amplification by class-D audio output stage 42, its output pulse train may be converted back to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in output circuitry of class-D audio output stage 42 or a load driven class-D audio output stage 42. As shown in FIGURE 3, class-D audio output stage 42 may include a control input for receiving a control input from calibration subsystem 28 in order to selectively enable class-D audio output stage 42 during an operational mode of audio IC 9 and disable class-D audio output stage 42 during a calibration mode of audio IC 9 (e.g., powering down or otherwise preventing class-D audio output stage 42 from driving the amplifier output of amplifier 16 by disabling or decoupling a supply voltage from class-D audio output stage 42 or by disabling or decoupling driving devices of the amplifier output of amplifier 16). As shown in FIGURE 3, class-D audio output stage 42 may include a modulator 52 having a modulator input for receiving intermediate signal Vint and configured to generate at a modulator output a modulated signal from intermediate signal Vint and also having an output switch block 54 comprising a plurality of output switches configured to generate audio output signal Vout from the modulated signal when the first mode is enabled.

Input network 24 may include any suitable input network for receiving an input signal (e.g., Vin) at the amplifier input of amplifier 16. For example, as shown in FIGURE 3, input network 24 may include variable input resistors 46. In addition, signal feedback network 26 may include any suitable feedback network for feeding back a signal indicative of audio output signal Vout to the amplifier input of amplifier 16. For example, as shown in FIGURE 3, signal feedback network 26 may include variable feedback resistors 48. In operation, resistances of input resistors 46 and variable feedback resistors 48 may be controlled by control signals received from a suitable gain control circuit in order to set a signal gain for amplifier 16.

Thus, in accordance with the above, amplifier 16 may comprise a closed loop amplifier having a first stage (e.g., first stage 26) configured to receive an amplifier input signal (e.g., Vin) at an amplifier input and generate at a first stage output an intermediate signal (e.g., Vint) which is a function of the amplifier input signal, a second stage (e.g., class-D audio output stage 42) configured to receive the intermediate signal at a second stage input and configured to generate at a second stage output an output signal (e.g., Vout) from the intermediate signal which is a function of the amplifier input signal, and an input network (e.g., input network 24) and a feedback network (e.g., feedback network 26) configured to set a gain of the closed loop amplifier.

Calibration subsystem 28 may include any suitable system, device, or apparatus configured to, in a calibration mode of audio IC 9, decouple an input of a second stage of an amplifier (e.g., input of class-D audio output stage 42), an output of a first stage of the amplifier (e.g., output of first stage 22), determine an offset signal (e.g., calibration signal CAL shown in FIGURE 3) that when applied to the input of a signal processing block (e.g., DAC 14) generates approximately zero as an intermediate signal (e.g., Vint) at the output of the first stage, and controls one or more parameters of an apparatus (e.g., audio IC 9) based on the offset signal to compensate for an offset of at least one of the first stage (e.g., first stage 22) and the signal processing block (e.g., DAC 14).

In addition, calibration subsystem 28 may, in the calibration mode, further determine the offset signal (e.g., calibration signal CAL shown in FIGURE 3) at two different signal gains of the amplifier (e.g., as set by resistances of input resistors 46 and variable feedback resistors 48) to extrapolate an offset of the first stage (e.g., first stage 22) and an offset of the signal processing block (e.g., DAC 14) and control one or more parameters of the apparatus (e.g., audio IC 9) based on the offset of the first stage to compensate for the offset of the first stage and based on the offset of the signal processing block to compensate for the offset of the signal processing block.

Furthermore, calibration subsystem 28 may be further configured to, in the calibration mode, electrically short the second stage output (e.g., input of class-D audio output stage 42) prior to determining the offset signal (e.g., calibration signal CAL shown in FIGURE 3).

Moreover, calibration subsystem 28 may be further configured to, in the calibration mode, electrically short the second stage output (e.g., input of class-D audio output stage 42), overdrive a common mode voltage of the second stage output, determine a second offset signal (e.g., another determination of calibration signal CAL shown in FIGURE 3) that when applied to the input of the signal processing block (e.g., DAC 14) generates approximately zero as the intermediate signal (e.g., Vint), and control one or more parameters of the apparatus (e.g., audio IC 9) based on the second offset signal to compensate for an offset of an input network (e.g., input network 24) and a feedback network (e.g., feedback network 26).

As shown in FIGURE 3, calibration subsystem 28 may include a comparator 56 and a digital calibration engine 58. Comparator 56 may comprise an auto-zero comparator that receives intermediate voltage Vint and outputs a signal indicative of a comparison of the terminals of intermediate voltage Vint to digital calibration engine 58. Digital calibration engine 58 may, based on the output of comparator 56, generate a digital calibration signal CAL that may be combined with digital input signal DIG IN to generate a calibrated digital input signal DIGINCAL received by DAC 14. More detailed operation of calibration subsystem 28 is set forth below with respect to FIGURE

4.

FIGURE 4 is a flow chart of an example method 60 for offset calibration in a circuit (e.g., audio IC 9) comprising an amplifier (e.g., amplifier 16), in accordance with embodiments of the present disclosure. According to some embodiments, method 60 may begin at step 62. As noted above, teachings of the present disclosure are implemented in a variety of configurations of personal audio device 1. As such, the preferred initialization point for method 60 and the order of the steps comprising method 60 may depend on the implementation chosen.

At step 62, calibration subsystem 28 may disable (e.g., power down) modulator 52 and output switch 54 of class-D audio output stage 42 and electrically short the output terminals of class-D audio output stage together (e.g., such that output voltage Vout = 0). At step 64, microcontroller core 18 may generate digital input signal DIG IN equal to zero. At step 66, calibration subsystem 28 may, at a first gain of amplifier 16, adjust digital calibration signal CAL to find the point at which the adjustment of digital calibration signal CAL causes the output of comparator 56 to change (e.g., thus indicating a change in polarity of intermediate signal Vint). At step 68, calibration subsystem 28 may, at a second gain of amplifier 16, adjust digital calibration signal CAL to find the point at which the adjustment of digital calibration signal CAL causes the output of comparator 56 to change (e.g., thus indicating a change in polarity of intermediate signal Vint). At step 70, calibration subsystem 28 may extrapolate an offset of first stage 22 and an offset of DAC 14 based on the calibration signals CAL determined at steps 66 and 68.

At step 72, calibration system 28 may apply the digital calibration signal CAL determined at step 68. At step 74, calibration subsystem 28 may cause a load at the output of amplifier 16 to be overdriven with a common-mode voltage. At step 76, calibration subsystem 28 may, at a particular gain of amplifier 16, adjust digital calibration signal CAL to find the point at which the adjustment of digital calibration signal CAL causes the output of comparator 56 to change (e.g., thus indicating a change in polarity of intermediate signal Vint). At step 78, calibration subsystem 28 may determine if step 76 has been applied for each gain setting of amplifier 16. If step 76 has not been applied for each gain setting of amplifier 16, method 60 may proceed again to step 76. Otherwise, if step 76 has been applied for each gain setting of amplifier 16, method 60 may proceed to step 80. At step 80, calibration subsystem 28 may extrapolate an offset of input network 24 and feedback network 26 based on the calibration signals CAL determined at multiple iterations of step 76. After completion of step 80, method 60 may end.

Although FIGURE 4 discloses a particular number of steps to be taken with respect to method 60, method 60 may be executed with greater or fewer steps than those depicted in FIGURE 4. In addition, although FIGURE 4 discloses a certain order of steps to be taken with respect to method 60, the steps comprising method 60 may be completed in any suitable order.

Method 60 may be implemented using personal audio device 1 or any other system operable to implement method 60. In certain embodiments, method 60 may be implemented partially or fully in software and/or firmware embodied in computerreadable media and executable by a controller.

Although the foregoing discussion contemplates embodiments in which amplifier 16 is a class-D amplifier having class-D audio output stage 42, the foregoing systems and methods may be applied to amplifiers other than class-D amplifiers having second stages other than a class-D audio output stage. For example, in some embodiments, amplifier 16 may include a class-AB audio output stage in lieu of class-D audio output stage 42. In such class-AB embodiments, first stage 22 may be used as a comparator along with calibration subsystem 28 in order to extract an offset for amplifier 16 and an offset for DAC 14.

In addition, although the foregoing discussion contemplates embodiments in which first stage 22 comprises one or more integrators 32, in some embodiments, first stage 22 may comprise an open-loop amplifier in lieu of integrators 32.

Moreover, although the foregoing discussion contemplates embodiments in which DAC 14 is interfaced between microcontroller core 18 and amplifier 16, in some embodiments, another signal processing system in addition to or in lieu of DAC 14 may be interfaced between microcontroller core 18 and amplifier 16.

As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.

All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

Claims

WHAT IS CLAIMED IS:

1. An apparatus comprising:

a closed loop amplifier comprising:

a first stage configured to receive an amplifier input signal at an amplifier input and generate at a first stage output an intermediate signal which is a function of the amplifier input signal;

a second stage configured to receive the intermediate signal at a second stage input and configured to generate at a second stage output an output signal from the intermediate signal which is a function of the amplifier input signal; and an input network and a feedback network configured to set a gain of the closed loop amplifier;

a signal processing block configured to generate the amplifier input signal as a function of an upstream signal received at an input of the signal processing block; and a calibration subsystem configured to, in a calibration mode:

decouple the second stage input from the first stage output;

determine an offset signal that when applied to the input of the signal processing block as the upstream signal generates approximately zero as the intermediate signal; and control one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

2. The apparatus of Claim 1, wherein the first stage comprises an integrator.

3. The apparatus of Claim 1, wherein the second stage comprises a Class D output stage.

4. The apparatus of Claim 1, wherein the second stage comprises a Class AB output stage.

5. The apparatus of Claim 1, wherein the calibration subsystem is further configured to, in the calibration mode:

determine the offset signal at two different signal gains of the closed loop amplifier to extrapolate an offset of the first stage and an offset of the signal processing block; and control one or more parameters of the apparatus based on the offset of the first stage to compensate for the offset of the first stage and based on the offset of the signal processing block to compensate for the offset of the signal processing block.

6. The apparatus of Claim 1, wherein the calibration subsystem is further configured to, in the calibration mode, electrically short the second stage output prior to determining the offset signal.

7. The apparatus of Claim 1, wherein the calibration subsystem is further configured to, in the calibration mode, after determining the offset signal of the first stage and the signal processing block:

electrically short the second stage output;

overdrive a common mode voltage of the second stage output;

determine a second offset signal that when applied to the input of the signal processing block as the upstream signal generates approximately zero as the intermediate signal; and control one or more parameters of the apparatus based on the second offset signal to compensate for an offset of the input network and the feedback network.

8. The apparatus of Claim 1, wherein the signal processing block comprises a digital-to-analog converter.

9. A method comprising, in an apparatus comprising a closed loop amplifier having a first stage configured to receive an amplifier input signal at an amplifier input and generate at a first stage output an intermediate signal which is a function of the amplifier input signal, a second stage configured to receive the intermediate signal at a second stage input and configured to generate at a second stage output an output signal from the intermediate signal which is a function of the amplifier input signal, and an input network and a feedback network configured to set a gain of the closed loop amplifier, and the closed loop amplifier also having a signal processing block configured to generate the amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus:

decoupling the second stage input from the first stage output;

determining an offset signal that when applied to the input of the signal processing block as the upstream signal generates approximately zero as the intermediate signal; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

10. The method of Claim 9, wherein the first stage comprises an integrator.

11. The method of Claim 9, wherein the second stage comprises a Class D output stage.

12. The method of Claim 9, wherein the second stage comprises a Class AB output stage.

13. The method of Claim 9, further comprising, in the calibration mode: determining the offset signal at two different signal gains of the closed loop amplifier to extrapolate an offset of the first stage and an offset of the signal processing block; and controlling one or more parameters of the apparatus based on the offset of the first stage to compensate for the offset of the first stage and based on the offset of the signal processing block to compensate for the offset of the signal processing block.

14. The method of Claim 9, further comprising, in the calibration mode, electrically shorting the second stage output prior to determining the offset signal.

5

15. The method of Claim 9, further comprising, in the calibration mode, after determining the offset signal of the first stage and the signal processing block:

electrically shorting the second stage output;

overdriving a common mode voltage of the second stage output;

determining a second offset signal that when applied to the input of the signal

10 processing block as the upstream signal generates approximately zero as the intermediate signal; and controlling one or more parameters of the apparatus based on the second offset signal to compensate for an offset of the input network and the feedback network.

15

16. The method of Claim 9, wherein the signal processing block comprises a digital-to-analog converter.

Intellectual

Property

Office

Application No: GB1712743.2 Examiner: Ms Gillian Buggey