GB2529090A - Memory access control - Google Patents
Memory access control Download PDFInfo
- Publication number
- GB2529090A GB2529090A GB1517914.6A GB201517914A GB2529090A GB 2529090 A GB2529090 A GB 2529090A GB 201517914 A GB201517914 A GB 201517914A GB 2529090 A GB2529090 A GB 2529090A
- Authority
- GB
- United Kingdom
- Prior art keywords
- access
- memory
- requests
- units
- circuitry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Dram (AREA)
- Memory System (AREA)
- Multi Processors (AREA)
Abstract
Memory access circuitry for controlling access to a memory comprising multiple memory units arranged in parallel with each other. The memory access circuitry comprising: two access units each configured to select one of the multiple memory units in response to a received memory access request and to control and track subsequent accesses to the selected memory unit, the multiple memory units comprising at least three memory units; arbitration circuitry configured to receive the memory access requests from a system and to select and forward the memory access requests to one of the two access units, the arbitration circuitry being configured to forward a plurality of memory access requests for accessing one memory unit to a first of the two access units, and to direct a plurality of memory access requests for accessing a further memory unit to a second of the two access units and to subsequently direct a plurality of memory access requests for accessing a yet further memory unit to one of the first or second access units. The two access units comprise storing circuitry to store requests in a queue prior to transmitting the requests to the respective memory unit; and tracking circuitry to track requests sent to the respective memory units and to determine when to transmit subsequent requests from the queue. The control circuitry is configured to set a state of each of the two access units, the state being one of active, prepare and dormant, the access unit in the active state being operable to transmit both access and activate requests to the respective memory unit, the activate request preparing the access in the respective memory unit and the access request accessing the data, the access unit in the prepare state being operable to transmit the activate requests and not the access requests, the access unit in the dormant state being operable not to transmit any access or activate requests, the control circuitry being configured to switch states of the two access units periodically and to set not more than one of the access units to the active state at a same time.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/868,180 US9411774B2 (en) | 2013-04-23 | 2013-04-23 | Memory access control |
| PCT/GB2014/051085 WO2014174246A1 (en) | 2013-04-23 | 2014-04-08 | Memory access control |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB201517914D0 GB201517914D0 (en) | 2015-11-25 |
| GB2529090A true GB2529090A (en) | 2016-02-10 |
| GB2529090B GB2529090B (en) | 2021-01-06 |
Family
ID=50478524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1517914.6A Active GB2529090B (en) | 2013-04-23 | 2014-04-08 | Memory access control |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9411774B2 (en) |
| CN (1) | CN105144128B (en) |
| GB (1) | GB2529090B (en) |
| WO (1) | WO2014174246A1 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11243898B2 (en) * | 2014-08-01 | 2022-02-08 | Arm Limited | Memory controller and method for controlling a memory device to process access requests issued by at least one master device |
| KR102373544B1 (en) | 2015-11-06 | 2022-03-11 | 삼성전자주식회사 | Memory Device and Memory System Performing Request-based Refresh and Operating Method of Memory Device |
| KR102491651B1 (en) * | 2015-12-14 | 2023-01-26 | 삼성전자주식회사 | Nonvolatile memory module, computing system having the same, and operating method thereof |
| DE102017119426B4 (en) | 2017-08-24 | 2020-02-13 | Infineon Technologies Ag | TEST AND MANAGEMENT OF STORAGE CELLS |
| US10437758B1 (en) | 2018-06-29 | 2019-10-08 | Apple Inc. | Memory request management system |
| US10621115B2 (en) | 2018-06-29 | 2020-04-14 | Apple Inc | System and method for communication link management in a credit-based system |
| US11347644B2 (en) * | 2018-10-15 | 2022-05-31 | Texas Instruments Incorporated | Distributed error detection and correction with hamming code handoff |
| US11321135B2 (en) * | 2019-10-31 | 2022-05-03 | Oracle International Corporation | Rate limiting compliance assessments with multi-layer fair share scheduling |
| US11379388B1 (en) * | 2021-03-31 | 2022-07-05 | Advanced Micro Devices, Inc. | Credit scheme for multi-queue memory controllers |
| CN116594570B (en) * | 2023-07-03 | 2024-03-01 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
| CN116578245B (en) * | 2023-07-03 | 2023-11-17 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
| CN116521096B (en) * | 2023-07-03 | 2023-09-22 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6571325B1 (en) * | 1999-09-23 | 2003-05-27 | Rambus Inc. | Pipelined memory controller and method of controlling access to memory devices in a memory system |
| US20070294470A1 (en) * | 2006-06-14 | 2007-12-20 | Nvidia Corporation | Memory interface with independent arbitration of precharge, activate, and read/write |
| US7343457B1 (en) * | 2003-08-01 | 2008-03-11 | Unisys Corporation | Dual active bank memory controller |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6330646B1 (en) * | 1999-01-08 | 2001-12-11 | Intel Corporation | Arbitration mechanism for a computer system having a unified memory architecture |
| US6572325B2 (en) * | 1999-03-23 | 2003-06-03 | The Burlington Northern And Santa Fe Railway Co. | Freight container and lift casting therefore and method for lifting and transporting same |
| US6552596B2 (en) * | 2001-08-10 | 2003-04-22 | Micron Technology, Inc. | Current saving mode for input buffers |
| US20040103249A1 (en) * | 2002-11-25 | 2004-05-27 | Chang-Ming Lin | Memory access over a shared bus |
| US7577039B2 (en) * | 2005-11-16 | 2009-08-18 | Montage Technology Group, Ltd. | Memory interface to bridge memory buses |
| US7555659B2 (en) * | 2006-02-28 | 2009-06-30 | Mosaid Technologies Incorporated | Low power memory architecture |
| JP5252171B2 (en) * | 2007-09-19 | 2013-07-31 | アイシン・エィ・ダブリュ株式会社 | Vehicle control device |
| WO2011094436A2 (en) * | 2010-01-28 | 2011-08-04 | Hewlett-Packard Development Company, L.P. | Interface methods and apparatus for memory devices |
-
2013
- 2013-04-23 US US13/868,180 patent/US9411774B2/en active Active
-
2014
- 2014-04-08 GB GB1517914.6A patent/GB2529090B/en active Active
- 2014-04-08 CN CN201480021912.5A patent/CN105144128B/en active Active
- 2014-04-08 WO PCT/GB2014/051085 patent/WO2014174246A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6571325B1 (en) * | 1999-09-23 | 2003-05-27 | Rambus Inc. | Pipelined memory controller and method of controlling access to memory devices in a memory system |
| US7343457B1 (en) * | 2003-08-01 | 2008-03-11 | Unisys Corporation | Dual active bank memory controller |
| US20070294470A1 (en) * | 2006-06-14 | 2007-12-20 | Nvidia Corporation | Memory interface with independent arbitration of precharge, activate, and read/write |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105144128A (en) | 2015-12-09 |
| WO2014174246A1 (en) | 2014-10-30 |
| US9411774B2 (en) | 2016-08-09 |
| US20140317360A1 (en) | 2014-10-23 |
| GB201517914D0 (en) | 2015-11-25 |
| GB2529090B (en) | 2021-01-06 |
| CN105144128B (en) | 2018-08-07 |
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