GB2524622A

GB2524622A - Prioritising events to which a processor is to respond

Info

Publication number: GB2524622A
Application number: GB1501024.2A
Authority: GB
Inventors: David William Knox; Adrian John Anderson
Original assignee: Imagination Technologies Ltd
Current assignee: Imagination Technologies Ltd
Priority date: 2014-03-25
Filing date: 2015-01-21
Publication date: 2015-09-30
Anticipated expiration: 2035-01-21
Also published as: US9292365B2; GB201405323D0; DE102015104460A1; GB2524622B; CN104951365A; CN104951365B; US20150277998A1; GB201501024D0; DE102015104460B4

Abstract

A computer system comprises a processor (106) configured to respond to events from a plurality of sources, and a prioritisation module (104) implemented in hardware and configured to prioritise the events for the processor. Events from devices are placed in queues 1021-3 and a flag1-3 is output to a number of inputs 1101-3 on a prioritisation module, the module comprising one or more decision modules (108). The prioritisation module stores a source identifier 1121-3 which is used by identification logic (116) to identify which of the input has the highest priority to receive an asserted flag to an output (114) alongside a boolean OR output form an OR module (111) of the source corresponding to the highest priority asserted event flag. The processor can read the stored source identifier to identify the source of an event to which the processor is to respond. In this way, the decision as to which event a processor should respond to next is offloaded from the processor and implemented in hardware in the prioritisation module. This can reduce the workload of the processor and thereby result in a more efficient computer system.

Description

PRIORITSING EVENTS TO WHICH A PROCESSOR IS TO RESPOND

Background

Many computer systems include one or more processors which are configured to execute computer instructions. Computer systems also often include other devices such as a memory and/or peripheral devices such as a camera or keyboard, etc. Events can occur at the devices in a computer system which require a processor to respond, e.g. which require the processor to execute some instructions relating to the events. There are many different types of event to which a processor may respond, which may be generated by many different sources (e.g. devices) of the computer system. For example, in a communications processing system, an event may be generated by hardware in response to the filling of a buffer of received sampled data. In another example, an event may be generated by software when a memory buffer can be released for re-use.

When an event occurs which requires a response from the processor an indication that the event is pending (e.g. an event flag) may be sent to the processor to indicate that the processor should respond to the event. There may be times at which events are occurring at a faster rate than the rate at which the processor can handle the events. Therefore the processor can use a queuing system to queue the events to be processed. The queues are implemented in software at the processor, and as an example there may be a queue for each source of events, or alternatively one queue may be used to queue events generated by more than one source. When the processor is ready to respond to a new event, a decision can be made as to which of the queued events the processor should respond to next. This decision is implemented in software at the processor, and may for example be based upon a set of rules. For example, events from some sources may be prioritised over events from other sources. The decision may also be based on the length of time that an event has been waiting for a response from the processor.

The processor takes time and processing resources for queuing the events in the software queues and to implement the software instructions of the decision process in order to determine which event the processor is to respond to next.

Reducing the time and/or processing resources that the processor spends for queuing events and to implement the decision process may provide a more efficient computer system in terms of how the processor responds to events that occur in the computer system. Any improvements to the efficiency of a computer system are often beneficial.

Summary

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

The inventors have realised that the queuing of events and the decision logic for deciding which event a processor should respond to, can be offloaded from the processor. In particular, the event queues and the decision logic may be implemented in hardware and the result of the decision made by the decision logic (i.e. which event the processor should respond to next) may be provided to the processor from the hardware. In this way, the processor does not need to spend time or processing resources to determine which event to respond to, as the decision process is offloaded from software and implemented in hardware. In examples described herein, the decision logic is implemented in a prioritisation module which is implemented in hardware and coupled to the processor.

There is provided a computer system comprising: a processor configured to respond to events from a plurality of sources; and a prioritisation module implemented in hardware and configured to prioritise the events for the processor, the prioritisation module comprising one or more decision modules, wherein at least one of the one or more decision modules comprises: a plurality of inputs configured to receive respective event flags relating to events from respective sources, wherein each of the inputs is associated with a respective priority; OR logic configured to output a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; identification logic configured to identify which of the inputs to receive an asserted flag has the highest priority; and an output register configured to store a source identifier of the source for which an asserted event flag is received at the identified input; wherein the processor is configured to: (i) respond to receiving an asserted flag outputted by one of said one or more decision modules, by reading the source identifier stored in the output register of said one of the decision modules, and (ii) use said source identifier to identify a source of an event to which the processor is to respond.

There is provided a method of responding to events in a computer system comprising a processor configured to respond to events from a plurality of sources, and a prioritisation module implemented in hardware and configured to prioritise the events for the processor, wherein the prioritisation module comprises one or more decision modules which each have a plurality of inputs associated with respective priorities, the method comprising: receiving respective event flags relating to events from respective sources at the inputs of at least one of the one or more decision modules; outputting, from OR logic of the at least one decision module, a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; for each of the at least one decision module, identifying which of the inputs of the decision module to receive an asserted flag has the highest priority; storing, in a respective output register of each of the at least one decision module, a source identifier of the source for which an asserted event flag is received at the identified input of the decision module; responsive to the processor receiving an asserted flag outputted by one of said one or more decision modules! the processor reading the source identifier stored in the output register of said one of the decision modules; and the processor using the source identifier to identify a source of an event to which the processor is to respond.

There is provided a prioritisation module implemented in hardware and configured to be coupled to a processor configured to respond to events from a plurality of sources, wherein the prioritisation module is configured to prioritise the events for the processor, the prioritisation module comprising: one or more decision modules, wherein at least one of the one or more decision modules comprises: a plurality of inputs configured to receive respective event flags relating to events from respective sources, wherein each of the inputs is associated with a respective priority; OR logic configured to output a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; identification logic configured to identify which of the inputs to receive an asserted flag has the highest priority; and an output register configured to store a source identifier of the source for which an asserted event flag is received at the identified input; wherein the prioritisation module is configured to allow the processor to read the source identifier from the output register of one of said one or more decision modules for use in identifying a source of an event to which the processor is to respond.

There is provided a method of using a prioritisation module implemented in hardware to prioritise events for a processor which is configured to respond to events from a plurality of sources, wherein the prioritisation module comprises one or more decision modules which each have a plurality of inputs associated with respective priorities, the method comprising: receiving respective event flags relating to events from respective sources at the inputs of at least one of the one or more decision modules; outputting from OR logic of the at least one decision module, a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; for each of the at least one decision module, identifying which of the inputs of the decision module to receive an asserted flag has the highest priority; storing, in a respective output register of each of the at least one decision module, a source identifier of the source for which an asserted event flag is received at the identified input of the decision module; and the prioritisation module allowing the processor to read the source identifier from the output register of one of said one or more decision modules for use in identifying a source of an event to which the processor is to respond.

There may be provided computer readable code for generating a computer system or a prioritisation module as described in any of the examples described herein.

The computer readable code may be encoded on a computer readable storage medium.

The above features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the examples described herein.

Brief Description of the Drawings

Examples will now be described in detail with reference to the accompanying drawings in which: Figure 1 shows a computer system in which events are prioritised for a processor; Figure 2 shows a flow chart for a method of responding to events in a computer system; Figure 3 shows a schematic diagram of a prioritisation module in one example; Figure 4 shows a schematic diagram of a prioritisation module in another example; and Figure 5 shows a schematic diagram of identification logic in an example.

The accompanying drawings illustrate various examples. The skilled person will appreciate that the illustrated element boundaries (e.g., boxes, groups of boxes, or other shapes) in the drawings represent one example of the boundaries. It may be that in some examples, one element may be designed as multiple elements or that multiple elements may be designed as one element. Common reference numerals are used throughout the figures, where appropriate, to indicate similar features.

Detailed Description

Embodiments will now be described by way of example only.

Figure 1 shows a computer system 100 which comprises a plurality of event queues lO2, 1022 and 102, a prioritisation module 104 and a processor 106.

The queues 102 and the prioritisation module 104 are implemented in hardware, such that their functionality is offloaded from the processor 106. The event queues 102 are configured to store data relating to events which are waiting for a response from the processor 106. For example, in the computer system 100 shown in Figure 1, each of the queues 1 02 to 1023 is arranged to receive data relating to events generated by a respective device to which the processor 106 is to respond. That is, the event queue lOZ receives data relating to events generated by a first device ("Device 1"), the event queue 1022 receives data relating to events generated by a second device ("Device 2"), and the event queue 1023 receives data relating to events generated by a third device ("Device 3"). The devices might be peripheral devices or any other type of devices which generate events to which the processor 106 is to respond.

Each of the queues 102 is configured to provide an event flag to the prioritisation module 104 to indicate whether there is at least one event in the queue which is waiting for the processor 106 to respond. For example, the events may be removed from the queues 102 when the processor responds to the events, so the event flags provided from the event queues 102 to the prioritisation module 104 may be not empty' flags of the queues 102. The not empty' flag of a queue 102 is asserted when the queue 102 is not empty, i.e. when the queue includes at least some data relating to at least one event.

The prioritisation module 104 is arranged to receive the event flags from the queues 102. The prioritisation module 104 provides a Boolean OR output to the processor 106 to indicate whether there are any events waiting for a response from the processor 106. If there is at least one event to which the processor 106 is to respond, the processor can read a source identifier from the prioritisation module 104, as described in more detail below, in order to determine the source of the event. The prioritisation module 104 comprises a single decision module 108.

In other examples described below with reference to Figures 3 and 4, the prioritisation module comprises a plurality of decision modules. It is noted that a "decision module" may also be referred to as a "logical OR module". The decision module 108 comprises a plurality of inputs 1101, 1102 and 1103 which are coupled to outputs of the respective event queues lO2i, 1022 and 102g. The decision module 108 also comprises OR logic 111 configured to determine and output a flag corresponding to the result of a logical OR operation on the event flags received at the inputs llO, 1102 and 1103. The decision module 108 also comprises a plurality of input registers 112i, 1122 and 112 which are arranged to store source identifiers of the respective sources of the event flags. The source identifiers may, for example, comprise 8 bits. As an example, the source identifiers stored in the input registers 112 may be queue identifiers which identify one of the queues 102. For example, the input register 1 l2i may store a queue identifier identifying the queue 102i, the input register 1122 may store a queue identifier identifying the queue 1022, and the input register 1123 may store a queue identifier identifying the queue 1023. The source identifiers may be written into the input registers 112 when the decision module is configured in accordance with the sources that provide event flags to the corresponding inputs 110. The decision module 108 also comprises an output register 114 which is configured to store one of the source identifiers from the input registers 112 based on the event flags received at the inputs 110. The source identifier stored in the output register 114 can be read by the processor 106 to thereby provide the source identifier to the processor 106 to identify a source of an event to which the processor 106 is to respond. The decision module 108 also comprises identification logic 116 which is configured to identify which of the inputs 110 to receive an asserted flag has the highest priority, and to cause the source identifier from the input register 112 corresponding to the identified input to be written into the output register 114.

A method of using the computer system 100 to respond to events is described with reference to the flow chart shown in Figure 2. Each of the inputs 1101, 1102 and 1103 is associated with a respective priority. For example, the input 11 0 may have a high priority, the input 1102 may have a medium priority and the input 1103 may have a low priority. As described in more detail below, the inputs 110 may receive asserted or non-asserted signals and the decision module 108 (in particular the identification logic 116) determines which of the inputs 110 to receive an asserted signal has the highest priority. In this way, the decision module 108 (in particular the identification logic 116) determines which is the highest priority asserted input.

Before the method begins, in a configuration stage, source identifiers (e.g. queue identifiers of the queues 1 02i, 1022 and 1023) are stored in the respective input registers ll2, 1122 and 1123, e.g. by a configuration tool, in conjunction with the configuration of which event flags are provided to which of the inputs 110. The source identifier stored in input register 11 Z identifies the source of the signal provided to input 1101, so in this example input register ll2i stores the queue identifier for the queue 1 02i. The source identifier stored in input register 1122 identifies the source of the signal provided to input 1102] so in this example input register 1122 stores the queue identifier for the queue 1022. The source identifier stored in input register 1123 identifies the source of the signal provided to input 1103, so in this example input register 1123 stores the queue identifier for the queue 1023. The arrangement of which sources provide signals to which of the inputs 110 of the decision module 108 is configurable, and may be determined by configuration registers whose values are calculated by a configuration tool. In this way, the relative priorities of the sources are set (in a configurable manner). For example, in the embodiment shown in Figure 1, events occurring at device 1 are high priority so the data relating to those events is stored in queue 102i and the event flags are provided from the queue 1 02i to the high priority input 1101 and the queue identifier for queue 1 O2i is stored in the input register 11 2i. Furthermore, in the embodiment shown in Figure 1, events occurring at device 2 are medium priority so the data relating to those events is stored in queue 1022 and the event flags are provided from the queue 1022 to the medium priority input 1102 and the queue identifier for queue 1022 is stored in the input register 1122. Similarly, in the embodiment shown in Figure 1, events occurring at device 3 are low priority so the data relating to those events is stored in queue 1023 and the event flags are provided from the queue 1023 to the low priority input 1103 and the queue identifier for queue 1023 is stored in the input register 1123. If the priorities of the events occurring at the devices change for some reason then the system 100 is configurable to change the arrangement of which sources provide signals to which of the inputs 110 of the decision module 108, and the source identifiers stored in the input registers 112 will be changed accordingly.

In step S202 event flags are received at the inputs of the decision module 108. In the example shown in Figure 1, the event flags are the not empty' flags of the queues 102. In other examples, the event flags may be any other suitable indication that an event has occurred to which the processor 106 is to respond.

The event flags received at the inputs 110 are asserted if the respective queues 102 are not empty, i.e. if there is an event for the processor 106 to respond to. In step S204 the identification logic 116 determines which of the inputs 110 which receive an asserted event flag has the highest priority. That is, the identification logic 116 determines the highest priority asserted input. The source identifier for the source received at the highest priority asserted input is stored in the output register 114. That is, forwhichever input (110) is determined to be the highest priority asserted input, the source identifier stored in the corresponding input register (11 2) is copied into the output register 114. Figure 5 shows an example of how the identification logic 116 may be implemented, but it will be clear to a person skilled in the art that the identification logic 116 may be implemented in other ways to achieve the functions of identifying the highest priority asserted input and writing the appropriate source identifier into the output register 114.

In the example shown in Figure 5, the identification logic 116 is coupled to the inputs 1101, 1102 and 1103. The identification logic 116 is also coupled to the input registers 112, 1122 and 1123. The identification logic 116 comprises two NOT gates 502 and 504, three AND gates 506, 508 and 510 and three switches 512, 514 and 516. A signal received at input 1101 is used to control the switch 512 and is also provided, via the NOT gate 502 to a first inputs of the AND gates 506 and 508. A signal received at input 1102 is provided to a second input of the AND gate 506 and is also provided, via the NOT gate 504 to a second input of the AND gate 508. An output of the AND gate 508 is provided to a first input of the AND gate 510. A signal received at input 1103 is provided to a second input of the AND gate 510. An output of the AND gate 506 is used to control the switch 514.

An output of the AND gate 510 is used to control the switch 516. When the switch 512 is closed the source identifier stored in the input register ll2i can be written into the output register 114. When the switch 514 is closed the source identifier stored in the input register 1122 can be written into the output register 114. When the switch 516 is closed the source identifier stored in the input register 1123 can be written into the output register 114. In this way, if the input 1101 receives an asserted event flag then switch 512 is closed and switches 514 and 516 are open, such that the source identifier stored in the input register 11 Z is written into the output register 114. If the input 1101 does not receive an asserted event flag and input 1102 does receive an asserted event flag then switch 514 is closed and switches 512 and 516 are open, such that the source identifier stored in the input register 1122 is written into the output register 114. If the inputs 1101 and 1102 do not receive an asserted event flags and input 11 O does receive an asserted event flag then switch 516 is closed and switches 512 and 514 are open, such that the source identifier stored in the input register 112 is written into the output register 114. A new identifier may be written into the output register 114 each time the state of at least one of the switches (512, 514 or 516) changes.

In step S205 the OR logic 111 determines and outputs a flag corresponding to the result of a logical OR operation on the event flags received at the inputs 110. The Boolean OR output from the OR logic 111 is sent to the processor 106, to indicate to the processor 106 whether there is an event to which it is required to respond.

The OR logic 111 may be implemented as a simple logical OR gate. The processor 106 may poll the Boolean OR output provided by the OR logic 111 to determine when it is asserted, e.g. the processor 106 may poll the output from the OR logic 111 when the processor 106 is ready to respond to the next event.

Alternatively (or additionally) the Boolean OR output may be configured to interrupt the processor 106 when it is asserted. The Boolean OR output may be a single bit, e.g. a 1'to indicate that there is a pending event or a 0' to indicate that there is not a pending event for the processor 106.

In step S206, responsive to receiving an asserted flag from the OR logic 111, the processor 106 reads the source identifier stored in the output register 114.

Therefore, in steps S202 to S206 the prioritisation module 104 acts to determine which of the currently pending events the processor 106 should respond to next and allows the processor 106 to read, from the output register 111, the source identifier for the source of the next event to which the processor 106 is to respond.

The source identifier stored in the output register 114 relates to the highest priority asserted input. The prioritisation module 104 is implemented in hardware, so the process of making the decision as to what to process next is offloaded from the processor 106 into hardware, which may result in a more efficient computer system 100.

In step S208 the processor 106 uses the source identifier which has been read from the output register 114 to identify the source of an event to which the processor 106 is to respond. Therefore, the processor 106 does not need to perform further processing steps to decide which event should be responded to next and to identify the source of the event: these processes are offloaded from the processor 106 to the prioritisation module 104.

In step S210 the processor 106 retrieves instructions relating to an event from the identified source. Then in step S212 the processor 106 processes the retrieved instructions to thereby respond to the event from the identified source. For example, if the source identifier is a queue identifier identifying one of the queues 102, then the processor 106 will retrieve data from the queue relating to the event and process the retrieved data.

As described above, the event could be a variety of different things which require a response from the processor 106 and the processor 106 may correspondingly respond to an event in one of a variety of different ways which is suitable to the particular event in question. For example, in a communications processing system, an event may be generated by hardware in response to the filling of a buffer of received sampled data. In another example, an event may be generated by software when a memory buffer can be released for re-use. The type of the event which is waiting for a response from the processor may be implicit, e.g. all events from a particular source may be of the same type. This would allow the processor to know the type of the event that is to be handled for the source before it begins the processing of the event. In other cases, the processor might not know what type of event is to be handled, but on contacting the source (as identified by the source identifier) the processor can determine the type of the event so that the event can be processed correctly.

In the examples described above, the source identifiers are queue identifiers. In other examples, the source identifiers could be offsets into a lookup table, wherein the lookup table comprises memory addresses which are to be accessed by the processor 106 to thereby respond to the events. That is, instructions for the processor 106 to execute in response to the events may be stored in a memory (e.g. in a memory of the computer system 100) and the memory address of the instructions for responding to a particular event is stored in the lookup table. An offset into the lookup table therefore identifies the memory address of the instructions for responding to the event, so the offset into the lookup table can be used as the source identifier for an event, which can be stored in the input registers 112 and the output register 114 and read by the processor 106 to allow the processor 106 to determine which event is to be responded to next.

In the example shown in Figure 1, the prioritisation module 104 comprises a single decision module 108. In other examples, the prioritisation module may comprise a plurality of decision modules, wherein the output of the OR logic (i.e. the Boolean OR output) of at least one of the decision modules is coupled to an input of another one of the decision modules. For example, Figure 3 shows an example of a prioritisation module 304 which can be used in a corresponding way as the prioritisation module 104 described above. The prioritisation module 304 comprises four decision modules 3O8i, 3082, 3083 and 3084 which are arranged in a hierarchy comprising two levels. A first of the levels comprises the first decision module 3O8i. A second of the levels comprises the second, third and fourth decision modules 3082, 308 and 3084. Each of the decision modules 308 substantially corresponds to the decision module 108 described above, and includes corresponding components such as three inputs, three input registers, identification logic, an output register and OR logic. As shown in Figure 3, the outputs of the OR logic of the second, third and fourth decision modules 3082, 3083 and 3084 are coupled to respective inputs of the first decision module 3OSi, and the output of the OR logic of the first decision module 3O8i is configured to output a flag to the processor 106, wherein in response to receiving the flag, the processor can read a source identifier from the output register of the first decision module 3O8i to thereby identify a source of an event to which the processor 106 is to respond, as described in more detail below.

The second decision module 3082 is arranged to receive three event flags (Flagi, Flag2 and Flag3) which relate to events from respective sources. The input registers of the decision module 3082 store source identifiers (e.g. queue identifiers) identifying the sources of the events which relate to the event flags received at the respective inputs of the decision module 3082. As described above in relation to the decision module 108, the decision module 3082 stores in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted event flag. The output of the OR logic of the decision module 3082 (which is asserted if any of the inputs to the decision module 3082 are asserted) is received at a first input of the decision module 3O8i. The third decision module 3083 is arranged to receive three event flags (Flag4, Flag5 and Flag6) which relate to events from respective sources. The input registers of the decision module 3083 store source identifiers (e.g. queue identifiers) identifying the sources of the events which relate to the event flags received at the respective inputs of the decision module 3083. The decision module 3083 stores in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted event flag. The output of the OR logic of the decision module 3083 (which is asserted if any of the inputs to the decision module 3083 are asserted) is received at a second input of the decision module 3OSi. The fourth decision module 3084 is arranged to receive three event flags (Flag7, Flag3 and Flagg) which relate to events from respective sources. The input registers of the decision module 3084 store source identifiers (e.g. queue identifiers) identifying the sources of the events which relate to the event flags received at the respective inputs of the decision module 3084. The decision module 3084 stores in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted event flag. The output of the OR logic of the decision module 3084 (which is asserted if any of the inputs to the decision module 3084 are asserted) is received at a third input of the decision module 3OSi.

The input registers of the decision module 3O8i store identifiers of the respective decision modules (3082, 3083 and 3083) to which the corresponding inputs of the decision module 3OBi are connected. The decision module 3O8i (in particular the identification logic of the decision module 3O8i) is configured to: (i) determine which of the 2 tier decision modules (3082 to 3084) provides the highest priority asserted input to the decision module 3O8i, (ii) fetch the source identifier from the output register of that 2 tier decision module, and (iii) store the fetched source identifier in the output register of the decision module 3O8i. In this way the decision module 3O8i stores in its output register the source identifier corresponding to the highest priority of the asserted event flags (Flagi to Flagg).

The processor can read the source identifier from the output register of the decision module 3OBi. It is noted that the identification logic of the decision module 3O8i is slightly different to the identification logic 116 described above because rather than simply writing one of the source identifiers from the input registers into the output register it performs the steps (i) to (iii) mentioned above.

In this way the identification logic of the decision module 3O8i fetches the source identifier from the output register of the 2' tier decision module (3082, 3083 or 3084) which provides the highest priority input to the decision module 3OBi, and writes the fetched source identifier into the output register of the decision module 3O8i. The exact implementation of the identification logic of the decision module 3OSi may be different in different examples and a person skilled in the art would know how to implement the identification logic of the decision module 3OBi such that it has the desired functionality as described above.

In this way, the decision modules 308 of the prioritisation module 304 are arranged such that the source identifier corresponding to the highest priority asserted event flag (of the nine flags Flag1 to Flagg) is stored in the output register of the decision module 308i and can be read by the processor 106 to indicate to the processor 106 which event to respond to next. That is, a source identifier corresponding to the highest priority asserted input to the prioritisation module 304 appears in the output register of the decision module 3OBi, thereby avoiding multi-stage reading of the different decision modules 308. That is, the processor 106 can just read the source identifier from the output register of the top decision module 308i without needing to read any source identifiers from the other decision modules 3082 to 3084. The two tier hierarchy of the decision modules 308 shown in Figure 3 allows up to nine event flags to be provided to the prioritisation module 304 (when each decision module 308 comprises three inputs) and the highest priority asserted event flag is determined. If there are fewer than nine sources with events occurring then some of the flags (Fi to Fg) are not asserted. As described above, a configuration tool can arrange the order in which the event flags are coupled to the different inputs (with the corresponding source identifiers being stored in the corresponding input registers of the lower level decision modules 3082 to 3084), to thereby set the priorities with which the processor 106 responds to the events. In this way, the priorities assigned to different events are configurable.

As another example, Figure 4 shows an example of a prioritisation module 404 which can be used in a corresponding way as the prioritisation modules 104 and 304 described above. The prioritisation module 404 comprises thirteen decision modules 4O8i to 40813 which are arranged in a hierarchy comprising three levels.

A first of the levels comprises the first decision module 4OS. A second of the levels comprises the second, third and fourth decision modules 4082, 4O8 and 4084. A third of the levels comprises the fifth to thirteenth decision modules 4085 to 40813. Each of the decision modules 408 substantially corresponds to the decision module 108 described above, and includes corresponding components such as three inputs, three input registers, identification logic, an output register and OR logic. As shown in Figure 4, the outputs of the OR logic of the fifth, sixth and seventh decision modules 4O8, 4O8 and 4087 are coupled to respective inputs of the second decision module 4082; the outputs of the OR logic of the eighth, ninth and tenth decision modules 4O5, 4OSg and 4OS are coupled to respective inputs of the third decision module 4O8; the outputs of the OR logic of the eleventh, twelfth and thirteenth decision modules 408ii, 40812 and 408ia are coupled to respective inputs of the fourth decision module 4084; the outputs of the OR logic of the second, third and fourth decision modules 4082, 4083 and 4084 are coupled to respective inputs of the first decision module 4OBi; and the output of the OR logic of the first decision module 4OBi is configured to output a flag to the processor 106, wherein in response to receiving the flag, the processor can read a source identifier from the output register of the first decision module 408 to thereby identify a source of an event to which the processor 106 is to respond.

The cascading of the decision modules 408 works in a similar manner to the cascading of the decision modules 308 described above in relation to Figure 3.

That is, the fifth decision module 4085 is arranged to receive three event flags (Fi, F2 and F3) which relate to events from respective sources. The input registers of the decision module 4085 store source identifiers (e.g. queue identifiers) identifying the sources of the events which relate to the event flags received at the respective inputs of the decision module 4085. As described above in relation to the decision module 108, the decision module 408 stores in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted event flag. The output of the OR logic of the decision module 4085 (which is asserted if any of the inputs to the decision module 4085 are asserted) is received at a first input of the decision module 4082. Similarly, the sixth decision module 4086 is arranged to receive three event flags (F4, F5 and F6) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the sixth decision module 4085 is provided to a second input of the decision module 4082.

Similarly, the seventh decision module 4087 is arranged to receive three event flags (F7, F8 and F9) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag.

The output of the OR logic of the seventh decision module 4087 is provided to a third input of the decision module 4082. Similarly, the eighth decision module 408 is arranged to receive three event flags (Fio, F11 and F12) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the eighth decision module 408g is provided to a first input of the decision module 4083. Similarly, the ninth decision module 408 is arranged to receive three event flags (F13, F14 and F15) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the ninth decision module 408g is provided to a second input of the decision module 4083. Similarly, the tenth decision module 408i is arranged to receive three event flags (F15, F17 and F15) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the tenth decision module 4081o is provided to a third input of the decision module 408g. Similarly, the eleventh decision module 408ii is arranged to receive three event flags (F19, F20 and F21) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the eleventh decision module 408ii is provided to a first input of the decision module 4084. Similarly, the twelfth decision module 40812 is arranged to receive three event flags (F22, F23 and F24) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the twelfth decision module 40812 is provided to a second input of the decision module 4084. Similarly, the thirteenth decision module 40813 is arranged to receive three event flags (F25, F26 and F27) and to store in its output register the source identifier corresponding to the highest priority of its inputs which receive an asserted flag. The output of the OR logic of the thirteenth decision module 40513 is provided to a third input of the decision module 4084.

The input registers of the decision module 4082 store identifiers of the respective decision modules (4085, 408 and 4087) to which the corresponding inputs of the decision module 4082 are connected. The decision module 4082 (in particular the identification logic of the decision module 4082) is configured to: (i) determine which of the 3 tier decision modules (408 to 4087) provides the highest priority asserted input to the decision module 4082, (ii) fetch the source identifier from the output register of that 3 tier decision module, and (iii) store the fetched source identifier in the output register of the decision module 4082. In this way, the decision module 4082 stores in its output register the source identifier corresponding to the highest priority of the asserted event flags F1 to F9. The identification logic of the decision module 4082 is similar to the identification logic of the decision module 308 described above with reference to Figure 3, and as such is slightly different to the identification logic 116 described above in relation to Figure 1. This is because rather than simply writing one of the source identifiers from the input registers into the output register the identification logic of the decision module 4082 performs the steps (i) to (iii) mentioned above, to thereby fetch the source identifier from the output register of the 3R tier decision module (4O8, 4086 or 4087) which provides the highest priority input to the decision module 4082, and writes the fetched source identifier into the output register of the decision module 4082. Similarly, the input registers of the decision module 4083 store identifiers of the respective decision modules (4088, 408 and 408io) to which the corresponding inputs of the decision module 4083 are connected. The decision module 4083 (in particular the identification logic of the decision module 4083) is configured to: (i) determine which of the 3 tier decision modules (408 to 4O6rn) provides the highest priority asserted input to the decision module 4083, (ii) fetch the source identifier from the output register of that 3 tier decision module, and (Hi) store the fetched source identifier in the output register of the decision module 4083. In this way, the decision module 4083 stores in its output register the source identifier corresponding to the highest priority of the asserted event flags F19 to F18. The identification logic of the decision module 4083 is similar to the identification logic of the decision module 308i described above with reference to Figure 3, and as such is slightly different to the identification logic 116 described above in relation to Figure 1. This is because rather than simply writing one of the source identifiers from the input registers into the output register the identification logic of the decision module 4083 performs the steps (i) to (Hi) mentioned above, to thereby fetch the source identifier from the output register of the 3rd tier decision module (408, 408 or 408io) which provides the highest priority input to the decision module 4083, and writes the fetched source identifier into the output register of the decision module 4083. Similarly, the input registers of the decision module 4084 store identifiers of the respective decision modules (4O8ii, 40812 and 40813) to which the corresponding inputs of the decision module 4084 are connected. The decision module 4084 (in particular the identification logic of the decision module 4084) is configured to: (i) determine which of the 3 tier decision modules (4OBii to 40813) provides the highest priority asserted input to the decision module 4084, (ii) fetch the source identifier from the output register of that 3R tier decision module, and (iH) store the fetched source identifier in the output register of the decision module 4084. In this way, the decision module 4084 stores in its output register the source identifier corresponding to the highest priority of the asserted event flags F19 to F27. The identification logic of the decision module 4084 is similar to the identification logic of the decision module 308i described above with reference to Figure 3, and as such is slightly different to the identification logic 116 described above in relation to Figure 1. This is because rather than simply writing one of the source identifiers from the input registers into the output register the identification logic of the decision module 4084 performs the steps (i) to (iii) mentioned above, to thereby fetch the source identifier from the output register of the 3 tier decision module (4OBii, 40812 or 40813) which provides the highest priority input to the decision module 4084, and writes the fetched source identifier into the output register of the decision module 4084.

The input registers of the decision module 408i store identifiers of the respective decision modules (4082, 4083 and 4084) to which the corresponding inputs of the decision module 408i are connected. The decision module 408i (in particular the identification logic of the decision module 4O8i) is configured to: (i) determine which of the 2 tier decision modules (4082 to 4084) provides the highest priority asserted input to the decision module 408i, (U) fetch the source identifier from the output register of that 2x tier decision module, and (Ui) store the fetched source identifier in the output register of the decision module 408i. In this way, the decision module 408i stores in its output register the source identifier corresponding to the highest priority of the asserted event flags F1 to F27. The processor can read the source identifier from the output register of the decision module 408i. The identification logic of the decision module 408i is similar to the identification logic of the decision module 308i described above with reference to Figure 3, and as such is slightly different to the identification logic 116 described above in relation to Figure 1. This is because rather than simply writing one of the source identifiers from the input registers into the output register the identification logic of the decision module 408i performs the steps (i) to (iU) mentioned above, to thereby fetch the source identifier from the output register of the 2" tier decision module (4082, 4083 or 4084) which provides the highest priority input to the decision module 408i, and writes the fetched source identifier into the output register of the decision module 408i.

The decision modules 408 of the prioritisation module 404 are arranged such that the source identifier corresponding to the highest priority asserted event flag (of the twenty-seven flags F1 to F27) is stored in the output register of the decision module 408i and can be read by the processor 106 to indicate to the processor 106 which event to respond to next. That is, a source identifier corresponding to the highest priority asserted input to the prioritisation module 404 appears in the output register of the decision module 4OBi, thereby avoiding multi-stage reading of the different decision modules 408. That is, the processor 106 can just read the source identifier from the output register of the top decision module 408i without needing to read any source identifiers from the other decision modules 4082 to 40813. The three tier hierarchy of the decision modules 408 shown in Figure 4 allows up to twenty seven event flags to be provided to the prioritisation module 404 (when each decision module 408 comprises three inputs) and the highest priority asserted event flag is determined. If there are fewer than twenty seven sources with events occurring then some of the flags (Fi to F27) are not asserted.

As described above, a configuration tool can arrange the order in which the event flags are coupled to the different inputs (with the corresponding source identifiers being stored in the corresponding input registers of the 3 level decision modules 4085 to 4O8ia), to thereby set the priorities with which the processor 106 responds to the events. In this way the priorities assigned to different events are configurable.

In the examples described above, each of the decision modules comprises three inputs. In other examples, the decision modules may comprise different numbers of inputs, e.g. two inputs or more than three inputs. In examples in which the prioritisation module comprises a plurality of decision modules then each of the decision modules may comprise the same number of inputs, or different ones of the decision modules may comprise different numbers of inputs. The different inputs of a decision module are associated with different relative priorities.

In the example computer system 100 shown in Figure 1, there is just one processor 106. In other examples, there may be more than one processor in the computer system, and there may be a prioritisation module for each of the processors such that respective prioritisation modules can prioritise the events for the respective processors in the computer system.

There has been described herein various examples of computer systems in which the decision as to which event a processor should respond to next is offloaded from the processor and implemented in hardware in a prioritisation module. This can reduce the workload of the processor and thereby result in a more efficient computer system.

Those skilled in the art will realize that all, or a portion of the functionality, techniques or methods described herein may be carried out by a dedicated circuit, an application-specific integrated circuit, a programmable logic array, a field-programmable gate array, or the like. For example, the "module", "functionality", "component" or "logic" described herein may comprise hardware in the form of circuitry. Such circuitry may include transistors and/or other hardware elements available in a manufacturing process. Such transistors and/or other elements may be used to form circuitry or structures that implement and/or contain memory, such as registers, flip flops, or latches, logical operators, such as Boolean operations, mathematical operators, such as adders, multipliers, or shifters, and interconnects, by way of example. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other levels of abstraction. Such elements may be interconnected in a specific arrangement. The module, functionality, component or logic may include circuitry that is fixed function and circuitry that can be programmed to perform a function or functions; such programming may be provided from a firmware or software update or control mechanism. In an example, hardware logic has circuitry that implements a fixed function operation, state machine or process.

It is also intended to encompass software which "describes" or defines the configuration of hardware that implements a module, functionality, component or logic described above, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code for generating a computer system and/or a prioritisation module configured to perform any of the methods described herein, or for generating a computer system and/or a prioritisation module comprising any apparatus described herein. One such configuration of a computer-readable medium is signal bearing medium and thus is configured to transmit the instructions (e.g. as a carrier wave) to the computing device, such as via a network. The computer-readable medium may also be configured as a non-transitory computer-readable storage medium and thus is not a signal bearing medium. Examples of a computer-readable storage medium include a random-access memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine.

The term processor' and computer' are used herein to refer to any device, or portion thereof, with processing capability such that it can execute instructions, or a dedicated circuit capable of carrying out all or a portion of the functionality or methods, or any combination thereof.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims. It will be understood that the benefits and advantages described above may relate to one example or may relate to several examples.

Any range or value given herein may be extended or altered without losing the effect sought, as will be apparent to the skilled person. The steps of the methods described herein may be carried out in any suitable order, or simultaneously where appropriate. Aspects of any of the examples described above may be combined with aspects of any of the other examples described to form further examples without losing the effect sought.

Claims

Claims 1. A computer system comprising: a processor configured to respond to events from a plurality of sources; and a prioritisation module implemented in hardware and configured to prioritise the events for the processor, the prioritisation module comprising one or more decision modules, wherein at least one of the one or more decision modules comprises: a plurality of inputs configured to receive respective event flags relating to events from respective sources, wherein each of the inputs is associated with a respective priority; OR logic configured to output a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; identification logic configured to identify which of the inputs to receive an asserted flag has the highest priority; and an output register configured to store a source identifier of the source for which an asserted event flag is received at the identified input; wherein the processor is configured to: (i) respond to receiving an asserted flag outputted by one of said one or more decision modules, by reading the source identifier stored in the output register of said one of the decision modules, and (ii) use said source identifier to identify a source of an event to which the processor is to respond.
2. The computer system of claim 1 wherein each of the at least one decision module further comprises input registers configured to store source identifiers of the sources of the event flags received at the inputs.
3. The computer system of claim 2 wherein the identification logic is configured to cause the source identifier from the input register corresponding to the identified input to be written into the output register.
4. The computer system of any preceding claim wherein, responsive to reading the source identifier from the output register of said one of said one or more decision modules, the processor is configured to: retrieve instructions relating to an event from the identified source; and process the retrieved instructions to thereby respond to the event from the identified source.
5. The computer system of any preceding claim further comprising event queues which are configured to: store data relating to events; and provide the event flags to the prioritisation module.
6. The computer system of claim 5 wherein each of the event queues is configured to store data relating to events generated by a respective device to which the processor is to respond.
7. The computer system of claim 5 or 6 wherein the event flags are not empty' flags of the event queues.
8. The computer system of any of claims 5 to 7 wherein the source identifiers are queue identifiers.
9. The computer system of any of claims 1 to 7 wherein the source identifiers are offsets into a lookup table, wherein the lookup table comprises memory addresses which are to be accessed by the processor to thereby respond to the events.
10. The computer system of any preceding claim wherein each of the at least one decision module comprises three inputs.
11. The computer system of any preceding claim wherein the prioritisation module comprises a single decision module.
12. The computer system of any of claims ito 10 wherein the prioritisation module comprises a plurality of decision modules, wherein the output of the OR logic of at least one of the decision modules is coupled to an input of another one of the decision modules.
13. The computer system of claim 12 wherein the prioritisation module comprises four decision modules arranged in a hierarchy comprising two levels; wherein a first level comprises a first of the decision modules and a second level comprises a second, a third and a fourth of the decision modules; wherein the outputs of the OR logic of the second, third and fourth decision modules are coupled to respective inputs of the first decision module, and wherein the OR logic of the first decision module is configured to output a flag to the processor, and wherein the output register of the first decision module is configured to store a source identifier which identifies a source of an event to which the processor is to respond.
14. The computer system of claim 12 wherein the prioritisation module comprises thirteen decision modules arranged in a hierarchy comprising three levels; wherein a first level comprises a first of the decision modules; a second level comprises a second, a third and a fourth of the decision modules; and a third level comprises a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh, a twelfth and a thirteenth of the decision modules; wherein the outputs of the OR logic of the fifth, sixth and seventh decision modules are coupled to respective inputs of the second decision module, wherein the outputs of the OR logic of the eighth, ninth and tenth decision modules are coupled to respective inputs of the third decision module, wherein the outputs of the OR logic of the eleventh, twelfth and thirteenth decision modules are coupled to respective inputs of the fourth decision module, wherein the outputs of the OR logic of the second, third and fourth decision modules are coupled to respective inputs of the first decision module, and wherein the OR logic of the first decision module is configured to output a flag to the processor, wherein the output register of the first decision module is configured to store a source identifier which identifies a source of an event to which the processor is to respond.
15. The computer system of any preceding claim wherein the arrangement of which sources relate to event flags provided to which of the inputs of the at least one decision module of the prioritisation module is configurable.
16. The computer system of any preceding claim wherein the source identifiers are 8-bit identifiers.
17. A method of responding to events in a computer system comprising a processor configured to respond to events from a plurality of sources, and a prioritisation module implemented in hardware and configured to prioritise the events for the processor, wherein the prioritisation module comprises one or more decision modules which each have a plurality of inputs associated with respective priorities, the method comprising: receiving respective event flags relating to events from respective sources at the inputs of at least one of the one or more decision modules; outputting, from OR logic of the at least one decision module, a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; for each of the at least one decision module, identifying which of the inputs of the decision module to receive an asserted flag has the highest priority; storing, in a respective output register of each of the at least one decision module, a source identifier of the source for which an asserted event flag is received at the identified input of the decision module; responsive to the processor receiving an asserted flag outputted by one of said one or more decision modules, the processor reading the source identifier stored in the output register of said one of the decision modules; and the processor using the source identifier to identify a source of an event to which the processor is to respond.
18. The method of claim 17 further comprising storing, in input registers, source identifiers of the sources of the event flags received at the inputs of the at least one decision module.
19. The method of claim 18 further comprising, for each of the at least one decision module, writing the source identifier from the input register corresponding to the identified input into the output register.
20. The method of any of claims 17 to 19 further comprising, responsive to the processor reading the source identifier from the output register of said one of said one or more decision modules: retrieving instructions relating to an event from the identified source; and processing the retrieved instructions at the processor to thereby respond to the event from the identified source.
21. A prioritisation module implemented in hardware and configured to be coupled to a processor configured to respond to events from a plurality of sources, wherein the prioritisation module is configured to prioritise the events for the processor, the prioritisation module comprising: one or more decision modules, wherein at least one of the one or more decision modules comprises: a plurality of inputs configured to receive respective event flags relating to events from respective sources, wherein each of the inputs is associated with a respective priority; OR logic configured to output a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; identification logic configured to identify which of the inputs to receive an asserted flag has the highest priority; and an output register configured to store a source identifier of the source for which an asserted event flag is received at the identified input; wherein the prioritisation module is configured to allow the processor to read the source identifier from the output register of one of said one or more decision modules for use in identifying a source of an event to which the processor is to respond.
22. The prioritisation module of claim 21 wherein each of the at least one decision module further comprises input registers configured to store source identifiers of the sources of the event flags received at the inputs.
23. The prioritisation module of claim 22 wherein the identification logic is configured to cause the source identifier from the input register corresponding to the identified input to be written into the output register.
24. The prioritisation module of any of claims 21 to 23, wherein event queues are configured to store data relating to events and to provide the event flags to the prioritisation module.
25. The prioritisation module of claim 24 wherein the event flags are not empty' flags of the event queues.
26. The prioritisation module of claim 24 or 25 wherein the source identifiers are queue identifiers.
27. The prioritisation module of any of claims 21 to 25 wherein the source identifiers are offsets into a lookup table, wherein the lookup table comprises memory addresses which are to be accessed by the processor to thereby respond to the events.
28. The prioritisation module of any of claims 21 to 27 wherein each of the at least one decision module comprises three inputs.
29. The prioritisation module of any of claims 21 to 28 wherein the prioritisation module comprises a single decision module.
30. The prioritisation module of any of claims 21 to 28 wherein the prioritisation module comprises a plurality of decision modules, wherein the output of the OR logic of at least one of the decision modules is coupled to an input of another one of the decision modules.
31. The prioritisation module of claim 30 wherein the prioritisation module comprises four decision modules arranged in a hierarchy comprising two levels; wherein a first level comprises a first of the decision modules and a second level comprises a second, a third and a fourth of the decision modules; wherein the outputs of the OR logic of the second, third and fourth decision modules are coupled to respective inputs of the first decision module, and wherein the OR logic of the first decision module is configured to output a flag to the processor, and wherein the output register of the first decision module is configured to store a source identifier which identifies a source of an event to which the processor is to respond.
32. The prioritisation module of claim 30 wherein the prioritisation module comprises thirteen decision modules arranged in a hierarchy comprising three levels; wherein a first level comprises a first of the decision modules; a second level comprises a second, a third and a fourth of the decision modules; and a third level comprises a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh, a twelfth and a thirteenth of the decision modules; wherein the outputs of the OR logic of the fifth, sixth and seventh decision modules are coupled to respective inputs of the second decision module, wherein the outputs of the OR logic of the eighth, ninth and tenth decision modules are coupled to respective inputs of the third decision module, wherein the outputs of the OR logic of the eleventh, twelfth and thirteenth decision modules are coupled to respective inputs of the fourth decision module, wherein the outputs of the OR logic of the second, third and fourth decision modules are coupled to respective inputs of the first decision module, and wherein the OR logic of the first decision module is configured to output a flag to the processor, wherein the output register of the first decision module is configured to store a source identifier which identifies a source of an event to which the processor is to respond.
33. The prioritisation module of any of claims 21 to 32 wherein the arrangement of which sources relate to event flags provided to which of the inputs of the at least one decision module of the prioritisation module is configurable.
34. The prioritisation module of any of claims 21 to 33 wherein the source identifiers are 8-bit identifiers.
35. A method of using a prioritisation module implemented in hardware to prioritise events for a processor which is configured to respond to events from a plurality of sources, wherein the prioritisation module comprises one or more decision modules which each have a plurality of inputs associated with respective priorities, the method comprising: receiving respective event flags relating to events from respective sources at the inputs of at least one of the one or more decision modules; outputting from OR logic of the at least one decision module, a flag corresponding to the result of a logical OR operation on the event flags received at the plurality of inputs; for each of the at least one decision module, identifying which of the inputs of the decision module to receive an asserted flag has the highest priority; storing, in a respective output register of each of the at least one decision module, a source identifier of the source for which an asserted event flag is received at the identified input of the decision module; and the prioritisation module allowing the processor to read the source identifier from the output register of one of said one or more decision modules for use in identifying a source of an event to which the processor is to respond.
36. The method of claim 35 further comprising storing, in input registers, source identifiers of the sources of the event flags received at the inputs of the at least one decision module.
37. The method of claim 36 further comprising, for each of the at least one decision module, writing the source identifier from the input register corresponding to the identified input into the output register.
38. Computer readable code for generating a computer system according to any of claims 1 to 16 or for generating a prioritisation module according to any of claims 21 to 34.
39. A computer readable storage medium having encoded thereon computer readable code for generating a computer system according to any of claims 1 to 16 or for generating a prioritisation module according to any of claims 21 to 34.