GB2517279A - Preamble structure - Google Patents

Preamble structure Download PDF

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Publication number
GB2517279A
GB2517279A GB1410979.7A GB201410979A GB2517279A GB 2517279 A GB2517279 A GB 2517279A GB 201410979 A GB201410979 A GB 201410979A GB 2517279 A GB2517279 A GB 2517279A
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United Kingdom
Prior art keywords
sequence
data structure
sequences
signal
synchronisation
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Granted
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GB1410979.7A
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GB201410979D0 (en
GB2517279B (en
Inventor
Alain Mourad
Belkacem Mouhouche
Daniel Ansorregui Lobete
Hongsil Jeong
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to GB1312217.1A priority Critical patent/GB2519498A/en
Priority to GB201313999A priority patent/GB201313999D0/en
Priority to GB201314337A priority patent/GB201314337D0/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB201410979D0 publication Critical patent/GB201410979D0/en
Publication of GB2517279A publication Critical patent/GB2517279A/en
Application granted granted Critical
Publication of GB2517279B publication Critical patent/GB2517279B/en
Application status is Expired - Fee Related legal-status Critical
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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61Network physical structure; Signal processing
    • H04N21/6106Network physical structure; Signal processing specially adapted to the downstream path of the transmission network
    • H04N21/6112Network physical structure; Signal processing specially adapted to the downstream path of the transmission network involving terrestrial transmission, e.g. DVB-T
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J13/00Code division multiplex systems
    • H04J13/0007Code type
    • H04J13/0055ZCZ [zero correlation zone]
    • H04J13/0059CAZAC [constant-amplitude and zero auto-correlation]
    • H04J13/0062Zadoff-Chu
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver
    • H04L27/2655Synchronisation arrangements
    • H04L27/2689Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation
    • H04L27/2692Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation with preamble design, i.e. with negotiation of the synchronisation sequence with transmitter or sequence linked to the algorithm used at the receiver
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042Detectors therefor, e.g. correlators, state machines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H04N21/2383Channel coding or modulation of digital bit-stream, e.g. QPSK modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0024Carrier regulation at the receiver end
    • H04L2027/0026Correction of carrier offset
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0083Signalling arrangements
    • H04L2027/0089In-band signals
    • H04L2027/0093Intermittant signals
    • H04L2027/0095Intermittant signals in a preamble or similar structure

Abstract

A data structure comprising a preamble portion and a data portion is provided. The preamble portion comprises one or more preamble symbols, and the data portion comprises one or more data symbols. The preamble portion comprises a synchronisation zone comprising two or more sequences for synchronisation. In one embodiment, the synchronisation zone comprises a first sequence based on a sequence ZC1, and a second sequence based on a sequence ZC2, wherein ZC1 and ZC2 are complimentary ZC sequences. In another embodiment, the synchronisation zone comprises M sequences based on a sequence ZCO located sequentially in the synchronisation zone. The M sequence form M/2 pairs of sequences, wherein one sequence from each of M/2-1 pairs of the M/2 pairs of sequences comprises +ZCO or —ZCO selected according to information to be signalled. In another embodiment, the synchronisation zone comprises M sequences located sequentially in the synchronisation zone, each being selected from a set of two or more different sequences according to information to be signalled. In another embodiment, the synchronisation zone comprises a repetition of two or more identical sequence blocks, each sequence block comprising one or more sequences. In another embodiment, the synchronisation zone comprises M sequences based on a sequence ZCO, wherein one or more of the M sequences comprise a cyclically shifted version of ZCO.

Description

PREAMBLE STRUCTURE

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates generally to a preamble structure, and methods, apparatus and systems for generating, detecting and decoding a preamble structure. More particularly, although not exclusively, the present invention relates to a preamble structure for detection, synchronisation and signalling for existing and future generation digital broadcasting systems, for example systems developed by the Digital Video Broadcasting (DVB) Project and/or the Advanced Television Systems Committee (ATSC).

Description of the Related Art

Digital broadcasting techniques allow various types of digital content, for example video and audio data, to be distributed to end users. A number of standards have been developed for this purpose, including a family of standards developed by the ATSC organization, including standards ATSC 1.0 and ATSC 2.0. The ATSC Digital Television (DTV) Standard, described in various documents, including P152 and A/53, available at http://www.atsc.org/, have been adopted for use in terrestrial broadcasting by various countries, including the United States, Canada and South Korea.

Recently, ATSC has begun developing a new standard, known as ATSC 3.0, for a delivery method of real-time and non-real-time television content and data to fixed and mobile devices. As part of this development, ATSC has published a Call for Proposals (CFP) document (TG3-52 Doc. #023r20, "Call for Proposals For ATSC-3.0 PHYSICAL LAYER, A Terrestrial Broadcast Standard", ATSC Technology Group 3 (ATSC 3.0), 26 March 2013), in which a stated goal is to identify technologies that could be combined to create a new physical layer of an ATSC 3.0 Standard. It is envisaged that the ATSC 3.0 system will be designed with a layered architecture and a generalized layering model for ATSC 3.0 has been proposed. The scope of the aforementioned CFP is limited to the base layer of this model, the ATSC 3.0 Physical Layer, which corresponds to Layer 1 and 2 of the ISO/IEC 7498-1 model.

It is intended that ATSC 3.0 will not require backward compatibility with existing broadcasting systems, including ATSC 1.0 and ATSC 2.0. However, the CFP states that, wherever practicable, the standard shall utilize and reference existing standards that are found to be effective solutions to meet the requirements.

Other existing standards developed for broadcasting digital content include a family of open standards developed and maintained by the Digital Video Broadcasting (DVB) Project and published by the European Telecommunications Standards Institute (ETSI). One such standard is DVB-T2, which is described in various documents, including ETSI EN 302 755 Vi.3.1, (Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2)"), and Technical Specification ETSI TS 102 831 Vi.2.1 (Digital Video Broadcasting (DVB); Implementation guidelines for a second generation digital terrestrial television broadcasting system (DVB-T2)").

In DVB-T2, data is transmitted in a frame structure. At the top level, the frame structure consists of super-frames, which are divided into a number of T2-frames. Each T2-frame is sub-divided into OFDM symbols, including a number of preamble symbols followed by a number of data symbols. In a T2-frame, the preamble symbols comprise a single P1 preamble symbol, followed by one or more P2 preamble symbols.

The P1 symbol, located at the beginning of a T2 frame, carries 7 bits for signalling, including Si signalling used to identify the format of the P2 symbols and S2 signalling used to signal certain basic transmission parameters. The P2 symbols, immediately following the P1 symbol, are used for fine frequency and timing synchronisation and channel estimation. The P2 symbols carry Li signalling information, and may also carry data. The Li signalling is divided into Li-pre signalling and Li-post signalling. The Li-pre signalling includes basic information about the T2 frame structure, and enables the reception and decoding of the Li-post signalling. The Li-post signalling provides sufficient information for the receiver to decode Physical Layer Pipes (PLP5) within the T2-frames, which carry data.

In digital broadcasting systems, in order to recognize and properly decode a received signal it is necessary to first perform synchronisation. Synchronization allows the receiver to identify the presence of a frame in the received signal and to identify the beginning of the frame. In addition, the values of one or more system parameters typically need to be signalled by the transmitter to the receiver to assist the receiver in decoding the signal.

Detection, synchronization and signalling information is typically provided in a preamble portion of a received signal. For example, in DVB-T2, synchronization and signalling is achieved using the P1 and P2 symbols.

What is desired is a preamble structure for detection, synchronization and signalling for use in existing and future generation digital broadcasting systems, for example systems developed by the Digital Video Broadcasting (DVB) Project and/or the Advanced Television Systems Committee (ATSC) (e.g. the ATSC 3.0 Standard). In particular, what is desired is a preamble structure that allows one or more of robust preamble detection, precise timing synchronisation, and signalling with low-overhead. For example, it is desirable to be able to perform synchronization in sub-optimal channel conditions, for example at very low Signal-to-Noise Ratios (SNRs), and in the presence of system imperfections, for example frequency offset.

SUMMARY OF THE INVENTION

It is an aim of certain exemplary embodiments of the present invention to address, solve and/or mitigate, at least partly, at least one of the problems and/or disadvantages associated with the related art, for example at least one of the problems and/or disadvantages described above. It is an aim of certain exemplary embodiments of the present invention to provide at least one advantage over the related art, for example at least one of the advantages described below.

The present invention is defined in the independent claims. Advantageous features are defined in the dependent claims.

Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, disclose exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, and features and advantages of certain exemplary embodiments and aspects of the present invention will be more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figures la and lb illustrate the phases of two complementary ZC sequences; Figures 2a and 2b illustrate the autocorrelation and cross-correlation properties of the ZC sequences illustrated in Figures la and lb; Figure 3 illustrates an exemplary frame structure that may be used in embodiments of the present invention; Figure 4 illustrates a first exemplary form of the synchronization structure illustrated in Figure 3; Figure 5 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 4; Figures 6a and 6b illustrate the shifts in correlation peaks caused by frequency offset for two complementary ZC sequences; Figure 7 illustrates a second exemplary form of the synchronization structure illustrated in Figure 3; Figure 8 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 7; Figure 9 illustrates a third exemplary form of the synchronization structure illustrated in Figure 3; Figure 10 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 9; Figure 11 illustrates a fourth exemplary form of the synchronization structure illustrated in Figure 3; Figure 12 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 11; Figure 13 schematically illustrates the elements and operations of an exemplary receiver side apparatus in an embodiment providing reduced complexity compared to the apparatus illustrated in Figure 12; Figure 14 illustrates an exemplary synchronization structure that may be used in exemplary embodiments of the present invention; Figure 15 illustrates certain results achieved using the synchronization structure illustrated in Figure 14; Figures 16a-c illustrate the detection probability performance of certain embodiments of the present invention measured in three scenarios; Figures 17a-c illustrate the time synchronization performance, shown as a Probability Density Function, of certain embodiments of the present invention in three scenarios; Figure 18 illustrates a further exemplary form of the synchronization structure illustrated in Figure 3; Figure 19 illustrates a yet further exemplary form of the synchronization structure illustrated in Figure 3; Figure 20 illustrates an exemplary embodiment in which a synchronization structure is transmitted in parallel with an additional signal; Figure 21 illustrates another exemplary embodiment in which a synchronization structure is transmitted in parallel with an additional signal; Figure 22 schematically illustrates the elements and operations for generating a modified ZC sequence according to an exemplary embodiment; Figure 23 illustrates the synchronization signal (magnitude, phase and spectrum) of a modified 70 sequence; Figure 24 illustrates the correlation properties of a modified ZC sequence; Figures 25-27 illustrate further exemplary embodiments of the present invention; Figure 28 illustrates an exemplary embodiment in which a synchronization structure is combined with an additional signal; Figure 29 illustrates an exemplary embodiment in which a synchronization structure is combined with an additional signal, and in which sequences of the synchronization structure component are used as pilots in the additional signal component; Figure 30 illustrates an exemplary spectrum of a ZC sequence and an exemplary spectrum of M repetitions of a 70 sequence; Figure 31 illustrates the operations performed at the transmitter of an exemplary embodiment to generate a signal of the form illustrated in Figure 29; Figure 32 illustrates the operations performed at the receiver side of an exemplary embodiment to process a received signal of the form illustrated in Figure 29; Figure 33 illustrates an exemplary embodiment in which each sequence block comprises two ZC sequences;

S

Figure 34 illustrates an exemplary embodiment in which each sequence block comprises four ZC sequences; Figure 35 illustrates another exemplary embodiment in which a synchronization structure is combined with an additional signal, and in which sequences of the synchronization structure component are combined with pilots in the additional signal component; Figure 36 illustrates simulation results when using the technique illustrated in Figure 35 combined with the embodiments illustrated in Figures 33 and 34; Figure 37 is a flow chart illustrating a method performed at the receiver side of an exemplary embodiment to process a received signal of the form illustrated in Figure 29; Figure 38 illustrates a first exemplary synchronisation structure based on repetitions of a single sequence including different cyclic shifts; Figures 39a and 39b illustrate a second exemplary synchronisation structure based on repetitions of a single sequence including different cyclic shifts; Figures 40a and 40b illustrate a third exemplary synchronisation structure based on repetitions of a single sequence including different cyclic shifts; and Figure 41 schematically illustrates one example of a circuit at the receiver for decoding a received synchronisation structure of the type illustrated in Figures 38, 39a, 39b, 40a and 40b.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE PRESENT

INVENTION

The following description of exemplary embodiments of the present invention, with reference to the accompanying drawings, is provided to assist in a comprehensive understanding of the present invention, as defined by the claims. The description includes various specific details to assist in that understanding but these are to be regarded as merely exemplaly.

Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention.

The same or similar components may be designated by the same or similar reference numerals, although they may be illustrated in different drawings.

Detailed descriptions of techniques, structures, constructions, functions or processes known in the art may be omitted for clarity and conciseness, and to avoid obscuring the subject matter of the present invention.

The terms and words used herein are not limited to the bibliographical or standard meanings, but, are merely used to enable a clear and consistent understanding of the invention.

Throughout the description and claims of this specification, the words "comprise", "include" and "contain" and variations of the words, for example "comprising" and "comprises", means "including but not limited to", and is not intended to (and does not) exclude other features, elements, components, integers, steps, processes, operations, functions, characteristics, properties and/or groups thereof Throughout the description and claims of this specification, the singular form, for example "a", "an" and "the", encompasses the plural unless the context otherwise requires. For example, reference to "an object" includes reference to one or more of such objects.

Throughout the description and claims of this specification, language in the general form of "X for Y" (whele Y is some action, process, operation, function, activity or step and X is some means for carrying out that action, process, operation, function, activity or step) encompasses means X adapted, configured or arranged specifically, but not necessarily exclusively, to do Y. Features, elements, components, integers, steps, processes, operations, functions, characteristics, properties and/or groups thereof described or disclosed in conjunction with a particular aspect, embodiment, example or claim of the present invention are to be understood to be applicable to any other aspect, embodiment, example or claim described herein unless incompatible therewith.

Certain embodiments of the present invention provide a preamble structure for performing detection, synchronization and signalling. In certain embodiments the preamble structure forms part of a frame structure or data structure suitable for a digital broadcasting system.

For example, certain embodiments provide a preamble structure that may be used in one or more existing and/or future generation digital broadcasting systems, for example systems developed by the Digital Video Broadcasting (DVB) Project and/or the Advanced Television Systems Committee (ATSC) (e.g. the ATSC 3.0 Standard). The skilled person will appreciate that the present invention is not limited to use in connection with any particular system or standard, and that various embodiments provide a preamble structure that may be used in any suitable type of digital broadcasting system.

Embodiments of the present invention may be implemented in the form of any suitable method, system and/or apparatus for use in digital broadcasting. For example, certain embodiments may be implemented in the form of a mobile/portable terminal (e.g. mobile telephone), hand-held device, personal computer, digital television andlor digital radio broadcast transmitter and/or receiver apparatus, set-top-box, etc. Any such method, system and/or apparatus may be compatible with any suitable existing or future digital broadcast system and/or standard, for example one or more of the digital broadcasting systems and/or standards referred to herein.

Certain embodiments may be implemented in the form of a system comprising a transmitter side apparatus and a receiver side apparatus. The transmitter side apparatus may be configured to generate a frame including a preamble structure and transmit, to the receiver side apparatus, a signal corresponding to the frame. The receiver side apparatus may be configured to receive the signal, detect the frame and perform frame synchronization using the preamble part of the frame, extract signalling contained in the preamble part of the frame, and perform any further frame decoding and/or processing. Certain embodiments may comprise a transmitter side apparatus only, a receiver side apparatus only, or a system comprising both a transmitter side apparatus and a receiver side apparatus.

A preamble structure disclosed herein may be generated using any suitable method comprising steps for generating such a preamble structure, or using any suitably arranged apparatus and/or system comprising means for generating such a preamble structure.

Frame detection and/or synchronization using a preamble structure disclosed herein may be performed using any suitable method comprising steps for performing frame detection and/or synchronization using such a preamble structure, or using any suitably arranged apparatus and/or system comprising means for performing frame detection and/or synchronization using such a preamble structure. Signalling may be extracted from a preamble structure disclosed herein using any suitable method comprising steps for extracting signalling from such a preamble structure, or using any suitably arranged apparatus andlor system comprising means for extracting signalling from such a preamble structure. The methods described herein may be implemented in any suitably arranged apparatus and/or system comprising means for carrying out the method steps.

In various exemplary embodiments described herein, frame detection and synchronization at the receiver is achieved using a number of sequences inserted by the transmitter into a preamble portion of a transmitted frame. In the embodiments described below, Zadoff-Chu (ZC) sequences, or modified ZC sequences, are used. However, the skilled person will appreciate that any other suitable type of sequence may be used (for example, any type of sequence having similar correlation properties to ZC sequences).

At the receiver, a received signal is correlated with one or more known sequences. The occurrence of a correlation peak indicates the presence of a corresponding sequence in the received signal, and hence allows the preamble to be detected. The location of the correlation peak allows the receiver to locate the position of the preamble, and hence perform frame synchronization.

Furthermore, in various exemplary embodiments described herein, signalling information may be carried in a frame by inserting different sequences into the preamble.

The signalling information may be in the form of any suitable type of information. For example, the signalling may be used to indicate a type of a frame (e.g. ATSC 3.0 frame or Future Extension Frame, FEF), to handle emergency alerts, or to carry elementary frame information to assist the receiver. Elementary frame information may comprise, for example, an antenna system configuration (e.g. Multiple-Input-Multiple-Output (Ml MO), Multiple-Input-Single-Output (MISO) or Single-Input-Single-Output (SISO)), a Fast Fourier Transform (FFT) size or Guard Interval (GI) length of the subsequent signalling or data symbols.

As mentioned above, a sequence in certain embodiments of the present invention may be in the form of a ZO sequence. A ZC sequence is a complex-values sequence, which may be defined by Equation 1 below.

un(n+1+2q) x(n) = euIT N Eq. 1 In Equation 1 above, n is the sequence index (n=0, 1 N-i), u, q and N are (integer) sequence parameters that may be changed to generate different sequences. N is the length of the sequence. In the following embodiments, it is assumed that q=0, although the skilled person will appreciate that embodiments of the present invention are not limited to this particular value.

The values of a ZC sequence have a constant amplitude (i.e. unity), but varying phase. A pair of complementary ZC sequences may be obtained by using a fixed value of N and pair of different values of u of the form {u1=a, u2=N-a}, where a is an integer. The values of a pair of complementary ZC sequences at corresponding sequence positions are complex conjugates, )(N.a(fl)=xa(fl) where * denotes complex conjugation.

Figures la and lb illustrate the phases of two exemplary complementary ZC sequences.

The sequence of Figure la uses parameter values of u=l and N=1024 and the sequence of Figure lb uses parameter values of u=1023 and N=1024 (i.e. a=1). Since the two 70 sequences illustrated in Figures la and lb are complementary, the phases at corresponding sequence positions have the same absolute value but opposite signs.

ZO sequences exhibit certain correlation properties that may be exploited in embodiments of the present invention. For example, the autocorrelation function of a given ZC sequence exhibits a very high and narrow peak at zero lag and exhibits noise-like characteristics elsewhere. Furthermore, the cross-correlation between two different ZC sequences (e.g. a pair of complementary sequences) exhibits noise-like characteristics. Figures 2a and 2b illustrate the autocorrelation and cross-correlation properties of the ZC sequences illustrated in Figures la and lb. As described in greater detail below, in embodiments of the present invention, correlation peak positions may be used for synchronization and the presence of different 70 sequences (e.g. two 70 sequences denoted 701 and 702) may be used for signalling.

Figure 3 illustrates an exemplary frame structure that may be used in embodiments of the present invention. The frame comprises a preamble zone located at the beginning of the frame and a data zone following the preamble zone. The preamble zone comprises a synchronization structure (or preamble structure) located at the beginning of the preamble zone and one or more additional preamble portions following the synchronization structure.

The synchronization structure comprises a number of sequences (e.g. ZO sequences) used for synchronization, and which may also be used for signalling. The additional preamble portions may be used to carry additional signalling. The data zone comprises one or more data regions for carrying data. Each of the additional preamble portions and data portions may comprise a symbol (e.g. an Orthogonal Frequency Division Multiplexing (OFDM) symbol) and may be preceded by a Guard Interval (GI). In the specific example illustrated in Figure 3, one additional preamble portion of length 8k and two data portions are shown, and the synchronization structure has a length of 1024 samples. The length of a GI may be set to a value suitable for eliminating inter-symbol-interference (ISI) caused by multi-path channels.

For example, the GI length may be set to be at least the maximum multi-path delay spread.

A number of examples of the form of the synchronization structure illustrated in Figure 3 will now be described.

Figure 4 illustrates a first exemplary form of the synchronization structure illustrated in Figure 3. In this embodiment, the synchronization structure comprises two different superimposed sequences, each of length N. In this embodiment the first sequence is based on a first ZO sequence, the first ZC sequence being denoted ZC1 and given by Equation 1 with certain values of u and N, and the second sequence is based on a second ZC sequence, the second 70 sequence being denoted 702 and comprising the complementary sequence of zol.

As mentioned above, two sequences are inserted into the synchronization structure, the first being based on sequence ZOl and the second being based on sequence Z02. In this embodiment, the sequence based on ZC1 may comprise one of two alternatives, as follows.

The first alternative comprises a first sequence, denoted ZC1, equal to ZC1 (i.e. ZC1(n)=ZC1(n), Vn). The second alternative comprises a second sequence, denoted ZCV, having values equal in magnitude, but opposite in sign, to values of ZC1 (i.e. ZCV(n)= -ZOl (n), Vn). Similarly, in this embodiment, the sequence based on Z02 may comprise either a first sequence, denoted ZC2 (wherein ZC2(n)=ZC2(n), Vn), or a second sequence, denoted ZCT (wherein Z02(n)= -Z02(n), Vn).

In this embodiment, one bit of information may be signalled by inserting certain combinations of sequences 701+, ZCV, ZC2+ and 707 into the synchronisation structure, for example as shown in Table 1 below.

Sequence based on 701 Sequence based on 702 Bit value signalled 701k ZC2 0 701k ZC2 1 701-ZC2 1 701-702-0

Table 1

In the example shown in Table 1, when sequences of "opposite signs" (e.g. ZC1 and ZC2) are inserted into the synchronisation structure, a first value (e.g. 1) is signalled and when sequences of the same sign" are inserted into the synchronization structure, a second value (e.g. 0) is signalled. Although the sequences ZC1 and ZC2 are known a priori at the receiver, and the receiver knows that one sequence based on 701 and one sequence based on 702 have been inserted into the preamble structure, the receiver does not know which of sequences 701+, 701-, 702+ and 702-have been inserted. However, the receiver may perform a correlation procedure to determine which of sequences ZC1+, Z01, Z02+ and ZCT have been inserted, thereby determining the signalled value.

The transmitter may generate the synchronization structure by selecting the appropriate sequences based on ZC1 and ZC2 according to the value to be signalled. The nth sample of the synchronization structure may be obtained by adding the nth values of the two selected 11.

sequences. The amplitudes of the resulting values may be scaled to achieve a certain signal power level. The frame is then completed by inserting the synchronization structure, along with any other required signalling and data.

The frame is used to form a baseband signal which is up-converted to a certain frequency (e.g. Radio Frequency (RF)) to obtain a signal for transmission by the transmitter. The receiver receives the signal and down-converts the signal to obtain a baseband signal corresponding to the frame. In order to perform synchronization, the receiver correlates the baseband signal with each of the known sequences ZC1 and ZC2 to detect corresponding peaks, which may be used to confirm the presence of the synchronization structure (and hence the frame) in the received signal, and to identify the location of the synchronization structure (and hence the beginning of the frame) in the received signal.

Figure 5 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 4. One problem that occurs in digital broadcasting systems, for example the system described above, is that a frequency offset may occur as a result of a difference in frequency between the oscillators in the transmitter and receiver used for up-conversion and down-conversion. One effect of frequency offset is the occurrence of shifts in the positions of the correlation peaks obtained when correlating the received signal with the known sequences ZC1 and ZC2. The shift is given by Equation 2 below. Eq.2 8W

In Equation 2 above, S is the magnitude of the shift in samples, N is the ZC sequence parameter, Al is the frequency offset, and BW is the bandwidth of the system. The direction of the shift will depend on the value of the sequence parameter u. In particular, the shift will be leftwards (i.e. towards lower numbered samples) if u>N12, and will be rightwards (i.e. towards higher numbered samples) if u<N/2.

Figures 6a and Sb illustrate the shifts in correlation peaks caused by frequency offset for two complementary ZC sequences. Figure 6a illustrates the case in which u<N12 resulting in a rightward shift, and Figure 6b illustrates the case in which u>N/2 resulting in a leftward shift.

The shift in the correlation peaks caused by frequency offset means that, when frequency offset occurs, the position of a correlation peak of a single ZC sequence does not accurately represent the location of the synchronization structure, and therefore precise frame synchronization is relatively difficult. However, by detecting correlation peaks of two complementary ZC sequences, precise frame synchronization may be simplified.

Specifically, since, for any pair of complementary ZC sequences, one of the sequence will satisfy u<N12 and the other sequence will satisfy u>N/2, then the correlation peak of one of the sequences will shift leftwards by a certain amount and the correlation peak of the other sequence will shift rightwards by the same amount. Therefore, the mean position of the (shifted) correlation peaks for a pair of complementary ZC sequences will give the (non-shifted) position without the effects of frequency offset.

Returning to Figure 5, in the receiver, a first correlator correlates the received (baseband) signal with the known sequence ZC1 to obtain a first correlation function (e.g. the correlation function illustrated in Figure 6a). The first correlator outputs the first correlation function to a first threshold detector, which detects the position, P1, of any peak in the first correlation function by determining a position at which the first correlation function exceeds a certain threshold. The first threshold detector outputs the determined position of the correlation peak (the peak with respect to ZC1) to a distance and synchronization position calculator.

In a similar manner, a second correlator correlates the received signal with the known sequence ZC2 to obtain a second correlation function (e.g. the correlation function illustrated in Figure Sb). The second correlator outputs the second correlation function to a second threshold detector, which detects the position, P2, of any peak in the second correlation function by determining a position at which the second correlation function exceeds a threshold. The second threshold detector outputs the determined position of the correlation peak (the peak with respect to ZC2) to the distance and synchronization position calculator.

The distance and synchronization position calculator computes the distance, D=1P2-P11, between the positions of the two peaks determined by the first and second threshold detectors. The distance and synchronization position calculator also computes the mean position of the peaks P=(P1+P2)/2. The distance and synchronization position calculator outputs the determined mean position, P, which provides a time position reference for performing synchronization. In addition, the distance and synchronization position calculator outputs the determined distance, D, to a frequency offset estimator. Based on Equation 2 above with S=D12, the frequency offset estimator estimates the frequency offset using Equation 3 below. Eq.3

In Equation 3, the variables have the same meanings as in Equation 2.

The frequency offset estimator outputs the estimated frequency offset, zSf, to a phase corrector. The phase corrector also receives the values of the peaks of the first and second correlation functions from the first and second threshold detectors, and uses the estimated frequency offset to correct the phases of the two peaks. The phase corrector outputs the phase-corrected values of the two peaks to a phase comparator, which compares the phases of the two peaks to determine the signalling bit. In particular, the phases of the peaks depend on which sequences ZC1+, ZC1, ZC2+ and ZCT were inserted into the synchronization structure. In the present embodiment, the phase difference between the peaks, which is relatively easy to detect, provides sufficient information to determine which of values 0 and 1 in Table 1 above is signalled.

Figure 7 illustrates a second exemplary form of the synchronization structure illustrated in Figure 3. In this example, the synchronization structure has a total length N and is divided into two portions (e.g. two portions of length N12 each). The first portion is located at the beginning of the synchronization structure and comprises two different superimposed sequences, each of length N12. These first and second sequences may be selected in a similar manner as the sequences in the synchronization structure described above in relation to Figure 4 (except for the lengths of the sequences). However, in the example illustrated in Figure 7, the first sequence comprises sequence ZC1 and the second sequence comprises sequence 702 (i.e. without selecting between ZC1+and 701-, or between 702+ and 702-).

The second portion is located at the end of the synchronization structure and comprises a single sequence of length N/2. This third sequence is selected from 701 or 702 according to the value of a bit to be signalled. For example ZC1 is selected as the third sequence if a first value (e.g. 0) is to be signalled, and ZC2 is selected as the third sequence if a second value (e.g. 1) is to be signalled.

In the embodiment illustrated in Figure 7, the first part of the synchronization structure comprising two superimposed complementary 70 sequences is used to provider resilience to frequency offset, and the second part of the synchronization structure comprising a single ZO sequence selected from two possible ZO sequences is used to provide one bit of signalling with relatively good Bit Error Rate (BER). In certain embodiments, the power between the first and second parts of the synchronization structure may be adapted for BER or detection adjustment.

Figure 8 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 7. The top part of Figure 8 illustrates the operations relating to the first part of the synchronization structure providing resilience to frequency offset, and the bottom part of Figure 8 illustrates the operations relating to the second part of the synchronization structure providing signalling. In certain embodiments, each of the duplicated elements schematically illustrated in Figure 8 may be implemented by a single component.

In the top part of Figure 8, the received signal is correlated with known sequences ZC1 and ZC2 by respective first and second correlators to obtain first and second correlation functions, as illustrated on the left-hand side of the top of Figure 8. The graphs on the top left of Figure 8 show only the part of the correlation function for the first part of the received signal, corresponding to the first part (N12 samples) of the synchronization structure. The first and second correlation functions are output to respective first and second threshold detectors, which detect the positions, P1 and F2, of respective peaks in the first and second correlation functions and output the detected positions to a synchronization position calculator. The synchronization position calculator computes the mean position of the peaks, P=(P1+P2)/2, and outputs the determined mean position, F, which provides a time position reference for performing synchronization.

In the bottom part of Figure 8, the part of the received signal corresponding to the second part of the synchronization structure (e.g. N12 samples after the determined start of the first part of the synchronization structure) is correlated with known sequences ZC1 and ZC2 by respective first and second correlators to obtain first and second correlation functions. Since the second part of the synchronization structure comprises only one of two possible sequences, ZC1 and ZC2, only one of the first and second correlation functions will include a peak (since the cross-correlation of ZC1 and ZC2 exhibits noise-like characteristics). The bottom left of Figure 8 shows only the correlation function including a peak (in this example the correlation function corresponding to correlation with ZC2).

The first and second correlation functions are output to respective first and second threshold detectors, which detect the positions of any peaks in the first and second correlation functions and output the result to a decision block. The decision block decides on the signalled bit based on the outputs of the threshold detectors. For example, when a peak occurs only in the correlation function output by the first correlator (corresponding to correlation with ZC1), the decision block determines that the second part of the synchronization structure comprises sequence ZC1 and therefore outputs a bit decision 0.

Conversely, when a peak occurs only in the correlation function output by the second correlator (corresponding to correlation with ZC2), the decision block determines that the second part of the synchronization structure comprises sequence ZC2 and therefore outputs a bit decision 1.

The exemplary embodiments illustrated in Figures 4-8 have relatively high detection capability and are relatively robust to frequency offset. The signalling capability of the specific embodiments illustrated in Figures 4-8 is 1 bit.

Figure 9 illustrates a third exemplary form of the synchronization structure illustrated in Figure 3. In this embodiment, the synchronization structure, of total length N, comprises a concatenation of M sequences, each of length N/M. The first (M/2)+1 sequences each comprise a first ZC sequence, and the last (M/2)-1 sequences each comprise a ZC sequence selected from either the first ZC sequence or a second ZC sequence. In the illustrated embodiment, the first and second ZC sequences are each based on a single ZC sequence. Specifically, the first ZC sequence, denoted ZC, is equal to ZC (i.e. ZC(n)=ZC(n), Vn), and the second ZC sequence, denoted ZC, comprises a sequence having values equal in magnitude, but opposite in sign, to values of ZC (i.e. Z0(n)= -ZC(n), Vn).

Each sequence of the last M/2-1 sequences is used to signal one respective bit of information, thereby allowing the synchronization structure to signal M/2-1 bits of information. Specifically, each sequence in the last M/2-1 sequences is selected as ZC if the corresponding bit to be signalled has a first value (e.g. 0), and is selected as ZC if the corresponding bit to be signalled has a second value (e.g. 1).

Figure 10 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 9. At the receiver, the received signal, r, is correlated with known sequence ZC by a correlator. The resulting (complex-valued) correlation function is shown on the bottom of Figure 10, with the magnitude and phase components shown separately. The magntitude of the correlation function comprises M peaks, corresponding to the M sequences in the preamble structure.

The phase of the correlation function varies linearly (with discontinuities corresponding to a phase of 2t, at which the phase wraps back to zero) as a result of frequency offset between the transmitter and the receiver. When there is no frequency offset, the phase of the correlation function would be a constant value.

The correlation function is input into a chain of M-1 delay elements, each of which delays its input by a number of samples equal to the length of each sequence in the synchronization structure, L=N/M. The output of the correlator is input into the first delay element in the chain, and the output of each delay element is input into the next delay element in the chain, until the last delay element. Thus, the output of the correlator comprises a signal with a delay of zero, and the output of delay element p (p=l, 2 M-1) comprises a signal with a delay of pxL samples.

The output of the correlator and the outputs of the delay elements are input into a set of M/2 multipliers. Specifically, multiplier f (f=1, 2 M/2) multiplies a pair of signals, the first signal of the pair having been subjected to a delay of (f-1)xL and the second signal of the pair having been subjected to a delay of (M-f)xL. For example, the least delayed signal is multipled by the most delayed signal by the first multiplier, the next least delayed signal is multipled by the next most delayed signal by the second multiplier, and so on.

Next, in order to extract the signalling information, the outputs of the multipliers are input into a phase comparer. The phase comparer isolates a single peak from each of the M/2 signals received from respective multipliers. Specifically, the phase comparer receives the output of the qth multiplier, and from this signal, isolates the peak that was formed by multiplying the peaks corresponding to the qth and (M-f÷1)th sequences in the original correlation function (f=1, 2 M/2). It is noted here that the effects of any frequency offset are cancelled in the peaks isolated by the phase comparer. This is because multiplication of the complex-valued signals results in addition of the phases, and since the phase varies linearly over the correlation function the phases of peaks corresponding to the fth and (M-f+1)th sequences will sum to the same value for all values off.

The phase comparer uses the phase of the peak isolated from the output of the (M/2)th multiplier (i.e. the peak that was formed by multiplying the peaks corresponding to the middle two sequences) as a reference phase. The phase comparer then compares the reference phase with each phase of each peak isolated from the output of each of the other multipliers to obtain a respective signalling bit. Specifically, if the phase of an isolated peak is the same as the reference phase, then a corresponding signalling bit is determined to have a first value (e.g. 0), and if the phase of an isolated peak is different from the reference phase, then a corresponding signalling bit is determined to have a second value (e.g. 1).

An explanation of the above operations may be facilitated with reference to Figure 9, which illustrates a specific case of M=8. The middle two sequences (sequences 4 and 5) are paired (i.e. the correlation peaks corresponding to these sequences are multiplied together by a certain multiplier and the resulting multiplied peak are isolated by the phase comparer).

This middle pair sequences are always set to the same sequence (ZC). Therefore, the reference phase derived from this pair of sequences will be fixed.

On the other hand, each of the first three sequences is paired with a corresponding sequence in the last three sequences (e.g. sequence 1 is paired with sequence 8, sequence 2 is paired with sequence 7, and sequence 3 is paired with sequence 6). Although each of the first three sequences is set to the same fixed sequence (ZC), each of the last three sequences is selected from two possible sequences (7C and 70-). Therefore a phase derived from a certain pair of sequences, other than the middle pair, will depend on the selection of the relevant sequence in the last three sequences.

Returning to Figure 10, the phase comparer outputs the determined bit information to a combiner. The combiner also receives the outputs of each multiplier. The multiplier is configured to combine all peaks in phase using the bit information provided by the phase comparer. The combiner outputs the bit information and combined peak information to a decision block. The decision block makes a decision regarding the presence of a synchronization structure in the received signal based on the maximum peak level. By making a decision based on combined peaks, the decision block may make a decision with higher reliability than using a peak of a single sequence.

The exemplary embodiment illustrated in Figures 9 and 10 is relatively robust to frequency offset. The signalling capability of the specific embodiments illustrated in Figures 9 and 10 is 3 bits.

Figure 11 illustrates a third exemplary form of the synchronization structure illustrated in Figure 3. In this embodiment, the synchronization structure, of total length N, comprises M sequences, each of length L=N/M samples. Each sequence is selected from two possible sequences, for example a first 70 sequence, denoted 700, and a second 70 sequence, denoted ZOl. Each sequence is used to signal one bit of information according to whether ZOO or ZOl is selected. For example, if a sequence is selected as ZOO, then a first value (e.g. 0) is signalled, and if a sequence is selected as 701, then a first value (e.g. 1) is signalled. Thus, the synchronization structure illustrated in Figure 11 may be used to signal up to M bits. In the specific example illustrated in Figure 11, in which 8 sequences are selected as ZOO, ZOl, ZOO, ZOl, ZOl, ZOO, ZOO, and ZOl, respectively, an 8-bit sequence 01011001 may be signalled.

Figure 12 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the synchronization structure illustrated in Figure 11. Specifically, the apparatus comprises first and second correlators for correlating the received signal with known sequences ZOO and ZOl, respectively. The apparatus further comprises two chains of delay elements, each chain comprising M-1 delay elements, and each delay element configured for delaying its input by L samples (equal to the length of each sequence in the synchronization structure) to generate an output. The first chain of delay elements is used for delaying the correlation function output by the first correlator, and the second chain of delay elements is used for delaying the correlation function output by the second correlator.

The apparatus further comprises a combiner unit comprising 2M individual combiners. Each combiner computes a signal S based on the outputs of the correlators and delay elements according to Equation4 below.

S = Xb2÷10) x -1. -i) Eq. 4 In Equation 4 above, the set of M values b 0=1, 2, 3 M) each comprise a one-bit value selected from 0 and 1, x0(i) denotes the output of the first correlator delayed by ixL samples, and x10) denotes the output of the second correlator delayed by ixL samples. Each of the 2M combiners computes a signal according to Equation 4 above using a unique combination of bit values {b1, b2, b3 bM}. For example, in the specific case of M=8 as illustrated in figure 12, examples of the signals computed by three of the combiners are indicated below.

Combiner 0 (CO or 000000000): x0(O)x0(7)+x(1)x(6)+x0(2)x0(5)+x0(3)x0(4) Combiner 129 (C129 or Cl 0000001): x1(O)x1 (7)+x0(1)x0(6)+x0(2)x0(5)+x0(3)x0(4) Combiner 255 (C255 or Cliii 1111): x1(O)x1(7)+x1(1)x1(6)+x1(2)x1(5)+x1(3)x1(4) The apparatus further comprises a decision block, which is configured to detect when a peak is higher than a threshold value, and to output the combination of bits that gave the highest peak.

In the specific example illustrated in Figures 11 and 12, the received signal is combined as follows. The combined outputs of the correlators comprise 8 peaks separated by N/M samples (e.g. 1024/8=128 samples). The peaks will have different phases due to frequency offset between the transmitter and the receiver. However, the phases have a constant slope shift. For example, peak m has a phase of mxZ, where Z is the phase of the first peak (see the bottom pait of Figure 10). The peaks in phase are summed, for example as x(O).x(7)+x(l)x(6)+x(2)x(5)+x(3).x(4). Using this formula, all of the sums will have the same phase of 8Z. This phase may be used to provide an estimate of the frequency offset (in a small range).

Using Equation 4 above, in order to compute the signal for a single combiner, the number of multiplication operations required is equal to (M/2) and the number of addition operations required is M/2-1. In order to compute the signal for all 2M combiners, the total number of multiplication operations is equal to (M/2).2M and the total number of addition operations is equal to (M/2_1)2M. For example, for M=8, the number of multiplications is equal to 1024 and the number of additions is equal to 768. For M=4, the number of multiplications is equal to 32 and the number of additions is equal to 16.

In certain embodiments, the total number of multiplications may be significantly reduced. For example, for each term (value of i) in the sum given by Equation 4, there are only four possible combinations of the bit values b2÷1 and b2÷2. Therefore, for each value of i, the following four terms may be pre-computed: = x0(i) x x0(M -1 -1) Eq. 5a PI,Oi = x0(J) x x1(M -1-1) Eq. 5b m,io = x1(i) x x0(M -1-1) Eq. 5c = x1(i) x x1(M -1 -1) Eq. 5d Pre-computing these four terms for each of the M/2 value of i requires a total of 2M multiplications.

In order to compute a signal according to Equation 4 for a particular combiner using a particular combination of bit values {b1, b2, b3 b, then it is only necessary to add together four of the pre-computed terms, without performing any additional multiplications.

For example, for each term (value of I) of the sum given by Equation 4, a single pre-computed value is retried as follows: if b2÷1=O and b2÷2=O, then pre-computed value is retrieved; if b2+1=O and b2+2=1, then pre-computed value p is retrieved; if b2+1=1 and b2+2=O, then pre-computed value p is retrieved; and if b2+1=1 and b2+2=1, then pre-computed value Pi,ii is retrieved.

The resulting M/2 pre-computed values are then added together. Thus, the number of addition operations required is equal to M/2-1.

The above process is then repeated for each possible combination of bit values {b1, b2, b3, bM} such that the above process is performed 2M times in total. However, the pre-computation of values only needs to be performed once. Thus, in order to compute a signal for all 2M combiners, the total number of multiplication operations is equal to 2M and the total number of addition operations is equal to (M/2_1).2M. Accordingly, the number of addition operations is the same, but the number of multiplication operations is reduced from (M/2).2M to 2M (i.e. a reduction by a factor of 1/4.2M) A reduction in complexity and/or processing time at the receiver may therefore be achieved.

Figure 13 schematically illustrates the elements and operations of an exemplary receiver side apparatus when using the technique described above for reducing the number of multiplications. In Figure 13, the circles represent respective multipliers, each of which is used to compute and output a particular value to be stored as a pre-computed value. Each multiplier receives two inputs, each input comprising either (i) the output, xO, from the first correlator, or a delayed version thereof, or (ii) the output, xl, from the second correlator, or a delayed version thereof. The actual inputs of each multiplier depend on which pre-computed value each multiplier is used to compute, based on Equations 5a-d. Only four multipliers, for computing values Po.oo, Po,oi, Po.io, and Po,ii, are shown in Figure 13.

In certain configurations the exemplary embodiments illustrated in Figures 11-13 may be less robust to frequency offset than the embodiments illustrated in Figures 4-10. However, the embodiments illustrated in Figures 11-13 may provide higher signalling capability than the embodiments illustrated in Figures 4-10. For example, the signalling capability of the specific embodiments illustrated in Figures 11-13 is 8 bits.

In the embodiment illustrated in Figure 4, the synchronization structure comprises two superimposed ZC sequences. However, in alternative embodiments, two sequences may be transmitted consecutively, without being superimposed (e.g. in different time slots). For example, Figure 18 illustrates a further exemplary form of the synchronization structure illustrated in Figure 3. In the structure illustrated in Figure 18, a first ZC sequence is transmitted in a first time slot (e.g. a first portion of the synchronization structure) and a second ZC sequence is transmitted in a second time slot (e.g. a second portion of the synchronization structure following the first portion). The first sequence may be selected from one of two possible sequences (e.g. ZC1 and ZC2). The second sequence is selected as the sequence of the two possible sequences that was not selected for the first sequence.

Accordingly, in this embodiment, one of the pairs of sequences [ZC1, ZC2] and [ZC2, ZC1] is selected. This selection may be used to signal one bit of information.

Figure 19 illustrates a yet further exemplary form of the synchronization structure illustrated in Figure 3. In this embodiment, similar to the embodiment illustrated in Figure 18, a number of sequences are transmitted consecutively. Specifically, four sequences are transmitted consecutively, wherein each sequence is selected from one of two possible sequences (e.g. ZC1 or ZC2). The first two sequences in the embodiment of Figure 19 may be selected according to the same method as used to select the two sequences in the embodiment of Figure 18, thereby signalling one bit of information. Each of the last two sequences in the embodiment of Figure 19 may be selected according to a differential coding method in order to transmit two additional bits (one bit per sequence). Specifically, each sequence of the last 21.

two sequences is selected as being either the same as, or different to, the immediately preceding sequence. The particular selection (same sequence or different sequence) defines the value of the signalling bit. Thus, the embodiment illustrated in Figure 19 may be used to signal up to three bits of information.

The skilled person will appreciate that the principles used in the embodiments illustrated in Figures 18 and 19 may be generalised to transmitting any suitable number of sequences consecutively, either exclusively or in combination with transmitting two or more sequences simultaneously (e.g. superimposed).

The embodiments illustrated in Figures 4-13 and 18-19 may provide a detection capability that is at least as good as DVB-T2. Various embodiments may be selected according to one or more factors, for example depending on the requirements of resilience to frequency offset and/or signalling capability.

Figure 14 illustrates an exemplary synchronization structure that may be used in exemplary embodiments of the present invention. Figure 15 illustrates certain results achieved using the synchronization structure illustrated in Figure 14. In order to absorb the maximum delay due to frequency offset, the first Guard Interval (GI) immediately following the synchronization structure (e.g. the GI located between the synchronization structure and the first additional preamble portion shown in Figure 3) is extended. Accordingly, the first GI in the frame has a length that is greater (by an amount F) than the lengths of the other GIs in the frame. For example, the guard interval extension may be set equal to E=2T0, where T0 is the maximum shift for the maximum allowable frequency offset (allowing for positive and negative frequency offset).

The technique illustrated in Figure 14 may be applied to various embodiments of the present invention, for example, at least with one or more of the techniques illustrated in Figures 9-13.

In certain embodiments, a synchronization structure, for example according to any of the above-described embodiments, may be transmitted alone (i.e. without another signal being transmitted at the same time as the synchronization structure signal). However, in certain other exemplary embodiments, a synchronization structure, for example according to any of the above-described embodiments, may be transmitted in parallel (e.g. superimposed) with another signal, such that the transmit power is shared between the synchronization structure signal and the other signal. For example, the synchronisation structure signal may be scaled by a factor G (O<G<1), and the other signal may be scaled by a factor 1-G. The resulting signals may then be added together to form a combined signal for transmission.

The value of G may be selected according to any suitable criteria, for example according to design considerations or applications. The choice as to whether the synchronization structure should be transmitted alone or in parallel with another signal may be made dynamically, for example during use, or may be fixed according to any suitable criteria, for example according to design considerations or applications.

Figures 20 and 21 illustrate exemplary embodiments in which a synchronization structure is transmitted in parallel with an additional signal. For example, Figures 20 and 21 respectively illustrate the synchronization structures illustrated in Figures 18 and 19 being transmitted in parallel with an overlay signal. The skilled person will appreciate that synchronization structures other than those of Figures 18 and 19, including the various other synchronization structures disclosed herein, may be transmitted in parallel with another signal, for example in a similar manner as illustrated in Figures 20 and 21.

In certain embodiments, the additional signal may comprise a signal for carrying physical layer (Li) signalling. For example, the additional signal may be in the form of one or more Orthogonal Frequency Division Multiplexing (OFDM) symbols. The skilled person that, in the embodiments described herein, an OFDM symbol may be replaced with any other suitable type of multi-carrier symbol. In one specific example, the additional signal comprises a single OFDM symbol for carrying Li signalling and the synchronization structure is used for synchronization and carrying one or more bits of additional signalling.

One problem with transmitting a synchronization structure and an additional signal in parallel is that each of these parts will interfere with the other, likely resulting in a decrease in performance. Figure 28 illustrates an exemplary embodiment in which a synchronization structure is combined with an additional signal in which interference of the kind mentioned above may be reduced or eliminated.

The top row of Figure 28 illustrates the additional signal in the form of an OFDM symbol.

Each block in the top row of Figure 28 represents a different carrier of the OFDM symbol. As illustrated, some of the carriers (e.g. every fourth carrier in the example of Figure 28) are used to carry pilots, denoted P, for allowing the receiver to perform channel estimation. The remaining carriers are used to carry data, denoted D. The middle row of Figure 28 illustrates the synchronization structure. In this embodiment, the synchronization structure is in the form of an OFDM symbol comprising the same carriers as the OFDM symbol of the additional signal. Each block in the middle row of Figure 28 represents a different carrier of the OFDM symbol. As illustrated, in the synchronization structure symbol, the carriers corresponding to the pilots in the additional signal symbol (e.g. every fourth carrier in the example of Figure 28) carry one or more sequences (e.g. ZC sequences in the example of Figure 28). The remaining carriers contain zero values.

Sequences are inserted into the carriers of the synchronization structure symbol such that the resulting time-domain signal comprises M repetitions of a sequence block, each sequence block comprising one or more sequences. For example, the bottom row of Figure 28 illustrates the time-domain form of the synchronization structure in an example in which each sequence block comprises a single ZC sequence, denoted ZC1.

In some embodiments, the additional signal and the synchronization structure may be combined by using the sequences of the synchronization structure as pilots. Figure 29 illustrates an exemplary embodiment in which a synchronization structure is combined with an additional signal, and in which sequences of the synchronization structure component are used as pilots in the additional signal component. In this case, the additional signal and the synchronization structure may be summed to form the combined signal.

In certain embodiments, the power of the ZC sequences may be boosted in order to improve the performance of synchronization and/or channel estimation. In certain embodiments, the power of the part of the signal carrying the data may not need to be boosted, for example because one or more error correcting codes may be applied to the data.

In certain embodiments, the sequences inserted into the synchronization structure component may be selected from a set of two or more different sequences, for example in order to signal information. For example, a sequence may be selected from two different ZC sequences to signal one bit of information. In certain embodiments, each sequence repetition comprises the same ZC sequence (possibly selected from a set of two or more different sequences).

A combined signal of the form illustrated in Figure 29 provides several advantages. For example, in certain embodiments, the additional signal component and the synchronization structure component of the signal do not interfere with each other. Since the ZC sequences of the synchronization structure component experience no interference from the data of the additional signal component, very good synchronization sensitivity may be achieved.

Conversely, since the data of the additional signal component experiences no interference from the synchronization structure component, very good detection of data (e.g. low Bit Error Rate) may be achieved.

Furthermore, in certain embodiments, since the sequence used for synchronization is also used for channel estimation (i.e. the ZC sequence is used as a pilot), high overhead efficiency may be achieved.

Furthermore, if the Peak-to-Average Power Ratio (PAPR) of the ZC sequences is less than the PAPR of the additional signal then the PAPR of the combined signal will be no higher than the PAPR of the additional signal. This will typically be the case since the PAPR of a ZC sequence (which has a relatively flat spectrum) is typically relatively low.

In addition, in certain embodiments, channel estimation may be very reliable, for example due to (i) the absence of interference between the ZC sequences of the synchronization structure component and the data of the additional signal component, and (ii) because of the spectral properties of the ZC sequences (e.g. the ZC spectrum is relatively flat).The spectra of various ZC sequences are described below, with reference to Figure 30.

Figure 30 illustrates an exemplary spectrum of a ZC sequence and an exemplary spectrum of M repetitions of a ZC sequence. Specifically, the top pad of Figure 30 illustrates the spectrum of a ZC sequence of length N=64 and having a value of u=1, and the bottom left part of Figure 30 illustrates the spectrum of four repetitions of the ZC sequence whose spectrum is illustrated on the top part of Figure 30 (i.e. having a total length of 4x64=256 samples in the time domain). The bottom right part of Figure 30 illustrates a zoomed-in portion of the spectrum illustrated in the bottom left part of Figure 30.As illustrated, the spectra of the single ZC sequence and ZO sequence repetition are relatively flat. The spectrum of the ZC sequence repetition comprises an envelope having the same shape as the spectrum of the single ZC sequence. Within the envelope, the spectrum comprises a number of zeros located between peaks, as shown on the bottom right part of Figure 30. In general, in the frequency domain, a repetition of M ZC sequences occupies 1/M of the spectrum of a single corresponding ZC sequence.

As noted above, ZC sequences have very good cross-correlation and auto-correlation properties for allowing accurate detection and synchronization. Furthermore, a repetition of M ZC sequences, each of length L, provides a detection capability that is almost equal to a single ZC sequence of length MxL.

Figure 31 illustrates the operations performed at the transmitter of an exemplary embodiment to generate a signal of the form illustrated in Figure 29. First, the transmitter fills the data carriers of the frequency domain signal with data (for example Li signalling cells).

Next, the pilot carriers (e.g. every fourth carrier) of the frequency domain signal are filled with repetitions of a ZC sequence. Specifically, the pilot carriers are filled with repeated ZC sequence frequency response. Next, a time domain signal is generated by passing the filled frequency domain signal through an Inverse Discrete Fourier Transform (IDFT) unit, for example in the form of an Inverse Fast Fourier Transform (IFFI) unit. Next, after any required signal processing has been applied to the time domain signal, the time domain signal may be transmitted to a receiver side.

Figure 32 illustrates the operations performed at the receiver side of an exemplary embodiment to process a received signal of the form illustrated in Figure 29. First, the received signal is separately correlated with two known sequences (701 and ZC2) by a 70 correlator until a peak is detected. In this embodiment, since the received signal comprises only one of the two sequences (ZC1 or ZC2) then only one of the correlations will result in a peak. Next, one bit of signalling (e.g. an EWS bit) is extracted by determining which of the two sequences (ZC1 or ZC2) produced the peak.

Next, the position of the peak is used to perform synchronization. For example, the position of the peak is output to a Discrete Fourier Transform (e.g. Fast Fourier Transform (FFT)) unit, which is configured for converting the received time domain signal into a frequency domain signal. The position of the peak received from the 70 correlator allows the FFT unit to locate the beginning of the signal and therefore perform the FFT correctly.

Next, the frequency domain signal is output from the FFT unit to a channel estimation and equalization unit, which extracts the ZC sequences from the relevant carriers of the frequency domain signal and used the extracted ZC sequences as pilots to perform channel estimation and equalization.

Next, the equalised signal is output by the channel estimation and equalization unit to a Low Density Parity Check (LDPC) decoding unit, which decodes the data part of the signal to extract the data (e.g. Li signalling).

In the example illustrated in Figure 28, each sequence block comprises a single ZC sequence. However, in other embodiments, each sequence block may comprise two or more sequences. For example, Figure 33 illustrates an exemplary embodiment in which each sequence block comprises two 70 sequences, and Figure 34 illustrates an exemplary embodiment in which each sequence block comprises four ZC sequences.

In the embodiment illustrated in Figure 33, each sequence block comprises (i) a first sequence comprising a 70 sequence selected from ZC1 and 702, and (ii) a second sequence comprising a ZO sequence selected from ZC1 and ZC2 that was not selected for the first sequence. The selection of either [ZC1, ZC2] or [Z02, ZC1] for the first and second sequences may be made according to a one bit value to be signalled, for example in a similar manner as described above in relation to Figure 18.

In the embodiment illustrated in Figure 34, each sequence block comprises (i) a first sequence comprising a ZC sequence selected from ZC1 and ZC2, (ii) a second sequence comprising a ZC sequence selected from ZC1 and ZC2 that was not selected for the first sequence, and (Ui) third and fourth sequences, each comprising a ZC sequence selected from ZC1 and ZC2. The first and second sequences may be selected in a similar manner as described above in relation to Figure 33 to signal one bit. The third and fourth sequences may each be selected according to the value of a respective bit to be signalled, for example directly or in a differential manner as described above in relation to Figure 19, to signal two additional bits (making three bits in total).

The sequences ZC1 and ZC2 in the embodiments illustrated in Figures 33 and 34 may be complementary ZC sequences. In this case, a method may be applied to estimate and correct any frequency offset, as described above.

In the embodiments illustrated in Figures 33 and 34, different ZC sequences are mixed in the synchronization structure (for example to allow the effects of frequency offset to be reduced or eliminated, or to allow two or more bits to be signalled). The resulting spectrum of the mixed ZC sequences may be less flat (constant) than the spectrum of an individual ZC sequence. On the other hand, pilots are typically provided with constant amplitude in order to achieve good channel estimation. Therefore, if mixed ZC sequences are used as pilots, then the performance of channel estimation may be reduced.

Figure 35 illustrates another exemplary embodiment in which a synchronization structure is combined with an additional signal, and in which sequences of the synchronization structure component are combined with pilots in the additional signal component. This arrangement may improve channel estimation performance in cases in which mixed ZC sequences are used, for example the embodiments illustrated in Figures 33 and 34.

As illustrated at the top of Figure 35, pilots, denoted P, are inserted into certain carriers (e.g. every fourth carrier) of the additional signal component, and data, denoted D, is inserted into the remaining carriers. As illustrated in the middle part of Figure 35, ZC sequences are inserted into certain carriers in the synchronization structure component (specifically, the carriers corresponding to pilots in the additional signal component).

As illustrated at the bottom of Figure 35, in the combined signal, the carriers corresponding to the pilots/ZC sequences carry a weighted sum of a pilot sequence (F) and ZC sequences (ZC). For example, these carriers may carry a signal given by ZCxG + Px''(1-G), where G is a weighting parameter (OcGC1). The factorsG anth(1-G) are used to achieve constant power. For example, the value of G may be configurable or predefined. The value of G may be the same for each carrier, or may be different for different carriers. The remaining carriers, not containing pilots/ZC sequences contain the data (without any weighting).

In the embodiment illustrated in Figure 35, if the pilots, P, have constant amplitude, then the flatness of the weighted sum of the pilot and sequences will be less than or equal to the flatness of the sequences alone. In particular, if the spectrum of the sequences is not completely flat, then the flatness of the weighted sum will be more flat than the sequences alone, thereby improving the performance of channel estimation.

Figure 36 illustrates simulation results when using the technique illustrated in Figure 35 combined with the embodiments illustrated in Figures 33 and 34.

Figure 37 is a flow chart illustrating a method performed at the receiver side of an exemplary embodiment to process a received signal of the form illustrated in Figure 29. In a first step 3301, the received signal is separately correlated with a set of two or more known sequences. In a next step 3303, it is determined whether a peak is detected in the correlation functions. If a peak is not detected in step 3303, then the method returns to step 3301. If a peak is detected in step 3303, then the method moves to step 3305.

In step 3305, the position of the peak is estimated, the sequence that produced the peak is determined, and a signalling value is extracted according to the determined sequence. The estimated peak position may be corrected, for example to eliminate or reduce the effects of frequency offset (for example using two corresponding peaks of ZOl and ZC2). The corrected peak position is provided to subsequent method step 3311, described further below.

In a next step 3307, the signalling value is used to determine or calculate a corresponding configuration. For example, the signalling value may indicate whether or not the received signal is based on a specific standard (e.g. ATSC 3.0). The signalling value may indicate an antenna configuration (e.g. MIMO/MISO/SISO) being used. In a next step 3309, it is determined whether the signalled configuration corresponds to the configuration of the receiver. If it is determined in step 3307 that the signalled configuration does not correspond to the configuration of the receiver, then the method returns to step 3301. This may occur, for example, in the case that the received signal is based on a standard that is incompatible with the receiver. If it is determined in step 3307 that the signalled configuration does correspond to the configuration of the receiver, then the method moves to step 3311.

In step 3311, lEFT processing is performed on the received time domain signal to obtain a corresponding frequency domain signal. In particular, IFFT is performed at the position corresponding to the peak position estimated in previous step 3305 described above.

In a next step 3313, channel estimation is performed using the sequences and/or pilots extracted from the frequency domain signal. For example, the frequency response of the channel may be obtained by interpolating values of the frequency response at the frequencies of the carriers carrying the sequences and/or pilots. In a next step 3315, the frequency domain signal is equalized using the estimated channel obtained in step 3313. In a next step 3317 data is extracted from the equalized signal to obtain Li signalling.

A technique for generating modified ZC sequences (i.e. bandwidth-limited ZC sequences) that may be used in various embodiments of the present invention will now be described. For example, modified ZC sequences may be used in place of one or more of the ZC sequences used in various embodiments of the present invention, for example the embodiments disclosed herein.

Figure 22 schematically illustrates the elements and operations for generating a modified ZC sequence according to an exemplary embodiment. Figure 23 illustrates the synchronization signal (magnitude, phase and spectrum) of a modified ZC sequence (e.g. a sequence generated according to the embodiment illustrated in Figure 22). Figure 24 illustrates the correlation properties of a modified ZC sequence (e.g. a sequence generated according to the embodiment illustrated in Figure 22).

In Figure 22, a ZC sequence of length N is generated and output to a Fast Fourier Transform (FFT) unit, which transforms the generated ZC sequence to the frequency domain. The frequency-domain ZC sequence (illustrated in the left-hand graph in Figure 22) is output to an insertion unit, which inserts K/2 zeros at each edge, for bandwidth limitation. The value of K may be selected according to any suitable criteria, for example performance or design considerations. The resulting bandwidth-limited sequence (illustrated in the middle graph in Figure 22) is output to an inverse-FFT (lEFT) unit, which transforms the bandwidth-limited frequency-domain sequence to the time-domain using an IFFT of length N+K to output a bandwidth-limited time-domain ZC sequence of length N+K. This sequence is then output to a power normalizer, which normalizes the power, P, of the sequence to any desired or required value (e.g. P=1). Figure 23 illustrates that the modified signal has a PAPR of -2.32dB.

Figures 25-27 illustrate further exemplary embodiments of the present invention. In these embodiments, a synchronization structure is transmitted in parallel with an overlay signal, as described above. The designs of the synchronization structure and the overlay signal may be selected to achieve an overall signal providing combined benefits and/or advantages of both the synchronization structure and the overlay signal.

As illustrated in Figure 25, the synchronization structure comprises a form similar to the embodiment illustrated in Figures 18 and 20, except that two Bandwidth-Limited ZC (BLZC) sequences, for example generated as described above, are used. For example, each BLZC sequence may comprise 5512 samples such that the total length of the synchronization structure is 11024. The skilled person will appreciate that these values are merely exemplary.

As illustrated in Figure 26, the synchronization structure comprises a form similar to the embodiment illustrated in Figures 19 and 21, except that two Bandwidth-Limited ZC (BLZC) sequences, for example generated as described above, are used. For example, each BLZC sequence may comprise 2756 samples such that the total length of the synchronization structure is 11024. The skilled person will appreciate that these values are merely exemplary.

As illustrated in Figure 27, the structure has a total length of 8k. The synchronization structure comprises 8 ZC sequences, each having a length of 1394 samples. An extension of the Guard Interval of 128 samples is added to mitigate the effects of frequency offset. The total length is 11152 (11024+128) samples. The skilled person will appreciate that these values are merely exemplary.

The detection probability performance of certain embodiments of the present invention has been measured in three scenarios, as illustrated in Figures 16a-c. First, embodiments of the present invention provide much better performance in an ideal case, for example an Additive White Gaussian Noise (AWGN) ideal case (÷7dB gain). Second embodiments of the present invention provide better performance in a practical case (multipath channel and frequency offset), for example TU6+5OkHz offset (+1dB gain). Third, embodiments of the present invention suffer little degradation in a worst case, for example TU6+500kHz offset (-0.8dB loss).

Figures 17a-c illustrate the time synchronization performance, shown as a Probability Density Function (PDF), of certain embodiments of the present invention in three scenarios.

As shown, certain embodiments of the present invention may provide better precision (less variance). Furthermore, certain embodiments of the present invention are resilient to frequency offsets, moving the centre point out of 0 (±1 1).

In various embodiments described above, a synchronisation structure of a frame structure comprises a number of ZC sequences. For example, the synchronisation structure may comprise identical repetitions of a "basic block" wherein a basic block comprises one or more ZC sequences. In the case that a basis block comprises two or more sequences, the basic block may comprise two or more different sequences. In any event, one or more sequences forming a basic block may be selected from two or more different sequences according to information to be signalled, for example based on direct coding or differential coding. Examples of a synchronisation structure comprising repetitions of a basic block are illustrated in Figures 33 and 34.

In cases where different sequences are used, the receiver typically requires different correlation circuits in parallel to correlate the received signal with the different sequences.

Furthermore, different sequences may get affected differently by frequency offsets.

Therefore, in certain embodiments, it may be advantageous to use a synchronisation structure based on a single sequence.

Figures 38-41 illustrate various exemplary embodiments in which the synchronisation structure comprises cyclically shifted versions of the same sequence. A cyclically-shifted sequence may be obtained, for example, by shifting the last m samples of the sequence to the beginning of the sequence.

In a first case, when a received signal containing a sequence is correlated with a copy of the same sequence, a correlation peak appears in the correlation function at a certain position.

In a second case, when a signal containing a sequence that is cyclically-shifted by m samples is correlated with a copy of the non-shifted sequence, a correlation peak appears in the correlation function that is shifted by m samples compared to the first case. For example, displacing the last sample of a sequence to the first position will displace the correlation peak 1 sample ahead in time for that sequence.

When a received signal containing M repetitions of the same sequence is correlated with a copy of the sequence, M correlation peaks appear in the correlation function. The correlation peaks are separated by a number of samples equal to the length, N, of the sequence.

However, if one or more of the sequence repetitions are cyclically shifted, then the correlation peaks corresponding to those sequences will be shifted by corresponding amounts. If the nth sequence is cyclically shifted by an amount Sh(n) and the (n+1)th sequence is cyclically shifted by an amount Sh(n+1), then the separation between peaks corresponding to the nth and (n+1)th sequences will be equal to N+Sh(n)-Sh(n+1).

For example, Figure 38 illustrates a case in which there are four sequence, comprising repetitions of a sequence ZC0 of length 128, where the first sequence has been cyclically shifted forwards one sample, the last sequence has been cyclically shifted backwards one sample, and the other two sequences are not cyclically shifted. In this example, as illustrated in Figure 38, the distance between the first two peaks is 127, the distance between the last two peaks is 129, and the distance between the middle two peaks is 128.

In certain embodiments, different combinations of shifts, that give specific delay peak patterns (i.e. patterns of displacement of the correlation peaks resulting from the cyclic shifting), may be used to signal information. For example, Figures 39a and 39b illustrate an example comprising eight sequences, comprising repetitions of a sequence ZC0 of length 128. As illustrated in Figure 39a, certain sequences are cyclically shifted using a certain combination of shifts such that consecutive correlation peaks in the resulting correlation function are separated by 125, 126, 127, 128, 127, 126 and 125 samples, respectively. This delay peak pattern may be used, for example, to signal a first bit value (e.g. 0). On the other hand, as illustrated in Figure 39b, certain sequences are cyclically shifted using a different combination of shifts such that consecutive correlation peaks in the resulting correlation function are separated by 131, 130, 129, 128, 129, 130 and 131 samples, respectively. This different delay peak pattern may be used, for example, to signal a second bit value (e.g. 1).

Using the above technique, it is possible in principle to signal multiple bits, for example up to N2 bits. However, there may be non-orthogonality between some combinations, and it may be preferable in certain embodiments to use only orthogonal combinations. Furthermore, relatively high shift values may degrade correlation performance, and so it may be preferable in certain embodiments to avoid relatively high shift values. Therefore, the number of bits that may be practically signalled may be lower than the theoretical maximum in certain embodiments.

However, in certain embodiments, it is possible to signals more bits, for example by shifting the sequences using different shift combinations, resulting in different delay peak patterns, for example delay peak patterns that differ in the order of the delays between peaks. One example is illustrated in Figures 40a and 40b.

Figure 41 schematically illustrates one example of a circuit at the receiver for decoding a received synchronisation structure described above in relation to Figures 38-40. Since the synchronisation structure is based on a single sequence with different shifts, only one correlator and a delay circuit is required at the receiver. The different possible delay peak patterns and their respective meanings are known a priori at the receiver. In general, the receiver combines all possible delay patterns and selects the one having the highest value.

This technique allows for simultaneous preamble detection and signalling decoding.

As illustrated in Figure 41, the receiver comprises a slide window correlator that receives a signal comprising the synchronisation structure as a first input, and a ZC reference signal comprising the known sequence on which the synchronisation structure is based as a second input. The slide window correlator correlates the synchronisation structure with the reference signal and outputs the result to a delay circuit. The delay circuit is configured to delay the input signal to generate a number of delayed signals, each delayed signal being delayed by an amount corresponding to one of the possible delays in the known delay peak patterns. The delayed signals output from the delay circuit are added together in combinations corresponding to the different possible delay peak patterns. For example, in the example illustrated in Figure 41, a first adder adds together a first set of delayed signals, and a second adder adds together a second set of delayed signals. The output of each adder is input to a comparer, which identifies which adder output has the highest value. The comparer then determines which delay peak pattern is present in the synchronisation structure from the identified adder, and outputs the corresponding bit value. The comparer also outputs the peak value, which indicates the presence of the synchronisation structure.

Although Figure 41 illustrates a case in which the synchronisation structure may include two possible delay patterns, representing 1 bit of signalling, the skilled person will appreciate that, in alternative embodiments, N different patterns may be used for signalling log2(N) bits.

In certain embodiments described above, a sequence is selected from two possible sequences to signal one of two possible values (i.e. signal one bit of information). However, the skilled person will appreciate that, in other embodiments, a sequence may be selected from more than two sequences (e.g. s sequences) to signal one of more than two (e.g. s) possible values (i.e. signal more than one bit of information, for example log2(s) bits).

In certain embodiments described above (e.g. the embodiments illustrated in Figures 4 and 5), by using two superimposed sequences, it is possible to estimate the frequency offset and to correct for the estimated frequency offset. The skilled person will appreciate that this technique may be applied to any of the embodiments described herein, unless incompatible therewith. Furthermore, in certain embodiments described above (e.g. the embodiments described in Figures 9 and 10), by using multiple (non-superimposed) sequences based on the same sequence, it is possible to mitigate the effects of frequency offset. The skilled person will appreciate that this technique may be applied to any of the embodiments described herein, unless incompatible therewith.

For example, the frequency offset techniques described herein may be applied to any synchronisation structure composed of two or more different shifted sequences, where the structure being transmitted is known at the receiver. The skilled person will appreciate that the frequency offset techniques described herein may be applied to any combination involving 2 right and left sequences under frequency offset conditions. These techniques may be applied regardless of whether the different shifted sequences are transmitted at the same time (i.e. are superimposed in the synchronisation structure) or at different times (i.e. are located sequentially in the synchronisation structure).

It will be appreciated that certain embodiments of the present invention may be implemented in the form of hardware, software or any combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage, for example a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape or the like.

It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs comprising instructions that, when executed, implement certain embodiments of the present invention.

Accordingly, certain embodiments provide a program comprising code for implementing a method, apparatus or system as claimed in any one of the claims of this specification, and a machine-readable storage storing such a program. Still further, such programs may be conveyed electronically via any medium, for example a communication signal carried over a wired or wireless connection, and embodiments suitably encompass the same.

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention, as defined by the appended claims.

Claims (55)

  1. Claims 1. A data structure comprising a preamble portion and a data portion, wherein the preamble portion comprises one or more preamble symbols, wherein the data portion comprises one or more data symbols, wherein the preamble portion comprises a synchronisation zone comprising two or more sequences for synchronisation.
  2. 2. A data structure according to claim 1, wherein the sequences comprise Zadoff-Chu (ZC) sequences.
  3. 3. A data structure according to claim 1 or 2, wherein the synchronisation zone comprises a first sequence based on a sequence ZC1, and a second sequence based on a sequence ZC2, wherein ZC1 and ZC2 are complimentary ZC sequences.
  4. 4. A data structure according to claim 3, wherein ZC1 and ZC2 are superimposed in the synchronisation zone.
  5. 5. A data structure according to claim 3 014, wherein the first sequence is selected from sequences +ZC1 and -ZC1 and/or the second sequence is selected from sequences +ZC2 and -ZC2, wherein the first sequence and/or the second sequence are selected according to information to be signalled.
  6. 6. A data structure according to claim 3, 4 or 5, wherein the synchronisation zone comprises a third sequence, wherein the third sequence is selected from a set of two or more sequences according to information to be signalled.
  7. 7. A data structure according to claim 6, wherein the third sequence is selected from sequences based on ZC1 and ZC2 according to information to be signalled.
  8. 8. A data structure according to claim 1 012, wherein the synchronisation zone comprises M sequences {ZC,} i=O, 1, 2 M-1, located sequentially in the synchronisation zone, wherein each of the M sequences is based on a sequence ZCO, wherein the M sequence form M/2 pairs of sequences ZC and ZCM.i.I, i=O, 1, 2 M/2-1, wherein one sequence from each of M/2-1 pairs of the M/2 pairs of sequences comprises a first sequence(+ZCO) or a second sequence (-ZCO) selected according to information to be signalled.
  9. 9. A data structure according to claim 8, wherein the other sequence from each of the M/2-1 pairs of the M/2 pairs of sequences comprises a fixed sequence.
  10. 10. A data structure according to claim 8 or 9, wherein both sequences of the remaining pair of the M/2 pairs of sequences each comprise fixed sequences.
  11. 11. A data structure according to claim 1 012, wherein the synchronisation zone comprises M sequences {ZC,} i=0, 1, 2 M-1, located sequentially in the synchronisation zone, wherein each of the M sequences is selected from a set of two or more different sequences according to information to be signalled.
  12. 12. A data structure according to claim 11, wherein each of the M sequences comprises one of 2 different sequences selected to signal one of 2 respective n-bit values.
  13. 13. A data structure according to claim 12, wherein each of the M sequences is selected from a set of sequences comprising a first sequence based on a sequence ZC1 and a second sequence based on a sequence ZC2 to signal a one-bit value.
  14. 14. A data structure according to claim 11, 12 or 13, wherein one or more of the M sequences are selected based on differential coding.
  15. 15. A data structure according to claim 14, wherein an ith sequence ZC is selected to be the same as a preceding sequence ZC.1 to signal a first value, and wherein the ith sequence ZC is selected to be different from the preceding sequence ZC.1 to signal a second value.
  16. 16. A data structure according to any of claims 8 to 15, wherein each of the M sequences are the same length.
  17. 17. A data structure according to any preceding claim, wherein the data portion comprises one or more guard intervals of length l, wherein the preamble portion comprises a guard interval of length 12 immediately following the synchronisation zone, wherein 12>11.
  18. 18. A data structure according to claim 17, wherein 12-11»=2T0, where T0 is a time shift corresponding to a predetermined maximum allowable frequency offset.
  19. 19. A data structure according to claim 18, wherein the predetermined maximum allowable frequency offset is dependent on the length of the sequences.
  20. 20. A data structure according to claim 1 or 2, wherein the synchronisation zone comprises a repetition of two or more identical sequence blocks, each sequence block comprising one or more sequences.
  21. 21. A data structure according to claim 20, wherein each sequence block comprises a sequence selected from a set of two or more sequences according to information to be signalled.
  22. 22. A data structure according to claim 21, wherein the sequence selected from a set of two or more sequences according to information to be signalled is selected based on differential coding.
  23. 23. A data structure according to claim 20 or 21, wherein each sequence block comprises a single sequence.
  24. 24. A data structure according to claim 20, 21 or 22, wherein each sequence block comprises two or more different sequences.
  25. 25. A data structure according to any preceding claim, wherein an overlay signal is superimposed over the synchronisation zone.
  26. 26. A data structure according to claim 25, wherein the synchronisation zone is scaled such that the transmit power of the synchronisation zone is equal to P0xG and the overlay signal is scaled such that the transmit power of the overlay signal is equal to Pox(1-G).
  27. 27. A data structure according to claim 25, wherein the synchronisation zone comprises two or more carriers, each carrier of the synchronisation zone having a respective frequency, wherein the overlay signal comprises two or more carriers having frequencies corresponding to the frequencies of the carriers of the synchronisation zone.
  28. 28. A data structure according to claim 27, wherein every pth carrier of the synchronisation zone carries an identical sequence block and the remaining carriers of the synchronisation zone carry zeros, such that the synchronisation zone in the time domain comprises repetitions of the sequence block.
  29. 29. A data structure according to claim 28, wherein the carriers of the overlay signal corresponding to the carriers of the synchronisation zone carrying zeros are used to carry data.
  30. 30. A data structure according to claim 29, wherein the carriers of the overlay signal corresponding to the carriers of the synchronisation zone carrying sequence blocks are used to carry pilots.
  31. 31. A data structure according to claim 30, wherein the carriers of the synchronisation zone carrying sequence blocks are scaled by a factor F and the carriers of the overlay signal carrying pilots are scaled by a factor 1-F.
  32. 32. A data structure according to claim 1 or 2, wherein the synchronisation zone comprises M sequences, wherein each of the M sequences comprises a sequence based on a sequence ZCO, wherein one or more of the M sequences comprises a cyclically-shifted version of ZCO.
  33. 33. A data structure according to claim 32, wherein the cyclic shifts are selected according to information to be signalled.
  34. 34. A data structure according to claim 33, wherein the cyclic shifts are selected so as to produce a correlation peak delay pattern corresponding to information to be signalled.
  35. 35. A method for synchronising a received data structure, the method comprising the steps of: -receiving a data structure; -correlating a synchronisation zone of the received data structure with a first sequence based on a sequence ZC1 to obtain a first correlation signal, and correlating the synchronisation zone of the received data structure with a second sequence based on a sequence 702 to obtain a second correlation signal, wherein 701 and 702 are complimentary 70 sequences; -detecting the position P1 of a peak in the first correlation signal, and detecting the position P2 of a peak in the second correlation signal; -calculating the mean position P=(P2-P1)/2 of the positions of the peaks in the first and second correlation signals; and -performing synchronisation of the data structure using the mean position P as a time position reference.
  36. 36. A method according to claim 35, comprising the further steps of: -calculating a difference D=1P2-P1I between the positions of the peaks in the first and second correlation signals; -estimating a frequency offset Af=(D/2)(BW/N) using the calculated difference D, where BW is the bandwidth of the system in which the data structure was transmitted and N is the length of the sequences ZC1 and ZC2; and -correcting the phases of the peaks in the first and second correlation signals using the estimated frequency offset.
  37. 37. A method according to claim 36, comprising the further steps of: -detecting the phases of the phase-corrected peaks in the first and second correlation signals; and -decoding information based on the detected phases.
  38. 38. A method according to claim 37, wherein the step of detecting the phases comprises comparing the phases of the phase-corrected peaks in the first and second correlation signals; and wherein the step of decoding information comprises decoding information based on the phase difference.
  39. 39. A method according to any of claims 35 to 38, comprising the further steps of: -correlating the synchronisation zone of the received data structure with the first sequence to obtain a third correlation signal, and correlating the synchronisation zone of the received data structure with the second sequence to obtain a fouith correlation signal; -detecting a peak in one of the third and fourth correlation signals; and -decoding information based on which of the third and fourth correlation signals a peak is detected.
  40. 40. A method according to any of claims 35 to 39, wherein the data structure comprises a data structure according to any of claims 3 to 7.
  41. 41. A method for synchronising a received data structure, the method comprising the steps of: -receiving a data structure; -correlating a synchronisation zone of the received data structure with a sequence based on a sequence ZCO to obtain a correlation signal comprising M peaks P, i=O, 1,2 M-1; -multiplying pairs of peaks P and PM.j.l, i=O, 1, 2 M/2-1 of the correlation signal to obtain M/2 multiplied peaks; -decoding information based on the phases of the multiplied peaks.
  42. 42. A method according to claim 41, wherein the step of decoding information comprises: -comparing the phases of each of (M/2)-lmultiplied peaks with the phase of the remaining multiplied peak used as a reference multiplied peak; and -decoding the information based on the comparisons.
  43. 43. A method according to claim 42, comprising the further steps of: -determining a set of multiplied peaks that are in-phase; -combining two or more multiplied peaks that are in-phase to obtain a combined peak; and -determining the presence of the synchronisation zone based on the magnitude of the combined peak.
  44. 44. A method according to claim 41, 42 or 43, wherein the step of multiplying pairs of peaks comprises: -obtaining M delayed correlation signals, wherein each delayed correlation signal is obtains by delaying the correlation signal by an amount ixD, i0, 1, 2 M- 1, wherein D is equal to the length of the sequence ZC0; -multiplying pars of delayed correlation signals; and -isolating a peak in each multiplied pair of correlation signals.
  45. 45. A method according to any of claims 41 to 44, wherein the data structure comprises a data structure according to any of claims S to 10.
  46. 46. A method for synchronising a received data structure, the method comprising the steps of: -receiving a data structure; -correlating a synchronisation zone of the received data structure with a first sequence based on a sequence ZC1 to obtain a first correlation signal; -correlating the synchronisation zone of the received data structure with a second sequence based on a sequence ZC2 to obtain a second correlation signal; -obtaining a first set of M delayed correlation signals x0(i), wherein each delayed correlation signal of the first set is obtains by delaying the first correlation signal by an amount ixD, i=0, 1,2 M-1, wherein D is equal to the length L of the sequence ZC1; -obtaining a second set of M delayed correlation signals x1(j), wherein each delayed correlation signal of the second set is obtains by delaying the second correlation signal by an amount jxD, j=0, 1, 2 M-1, wherein 0 is equal to the length L of the sequence ZC2; -obtaining 2M combined signals, wherein each combined signal S is computed according to Equation 4, where the M values b, i=0, 1, 2 M-1 each comprises a value selected from a first value (0) and a second value (1), wherein each combined signal is obtained using a unique combination of values {b}; -detecting one or more peaks in the combined signals; and -determining the combination of values {b} associated with the combined signal that includes the peak with the largest magnitude.
    S = > Xj,2÷1 (1) x x52÷2 (M -1 -1) Equation 4
  47. 47. A method according to claim 46, wherein the data structure comprises a data structure according to claim 11.
  48. 48. A method for synchronising a received data structure, the method comprising the steps of: -receiving a data structure; -correlating a synchronisation zone of the received data structure with a first sequence based on a sequence ZC0 and using a slide window correlator to obtain a correlation signal; -delaying the correlation signal to obtain two or more delayed signals; -obtaining two or more combined signals, wherein each combined signal is obtained by combining a respective set of delayed signals, wherein the delayed signals forming each set of delayed signal are delayed by amounts corresponding to delays of respective predetermined delay peak patterns; -comparing the magnitudes of the combined signals; -determining a signalling value based on a result of the comparison.
  49. 49. A method according to claim 48, wherein the data structure comprises a data structure according to any of claims 32 to 34.
  50. 50. A method for generating a data structure, the method comprising the steps of: inserting one or more preamble symbols in a preamble portion of the data structure; inserting one or more data symbols in a data portion of the data structure; and inserting a synchronisation zone comprising two or more sequences for synchronisation in the preamble portion.
  51. 51. An apparatus for generating a data structure, the apparatus comprising: -a preamble inserter for inserting one or more preamble symbols in a preamble portion of the data structure; -a data inserter for inserting one or more data symbols in a data portion of the data structure; and -a sequence inserter for inserting a synchronisation zone comprising two or more sequences for synchronisation in the preamble portion.
  52. 52. An apparatus for synchronising a received data structure, the apparatus comprising: -a receiver for receiving a data structure; -a correlator for correlating a synchronisation zone of the received data structure with a first sequence based on a sequence ZC1 to obtain a first correlation signal, and for correlating the synchronisation zone of the received data structure with a second sequence based on a sequence ZC2 to obtain a second correlation signal, wherein ZC1 and ZC2 are complimentary ZC sequences; -a peak detector for detecting the position Fl of a peak in the first correlation signal, and detecting the position P2 of a peak in the second correlation signal; -a position calculator for calculating the mean position P=(P2-Pl)/2 of the positions of the peaks in the first and second correlation signals; and -a synchroniser for performing synchronisation of the data structure using the mean position P as a time position reference.
  53. 53. An apparatus for synchronising a received data structure, the apparatus comprising: -a receiver for receiving a data structure; -a correlator for correlating a synchronisation zone of the received data structure with a sequence based on a sequence ZOO to obtain a correlation signal comprising M peaks P, i=O, 1, 2 M-1; -a multiplier for multiplying pairs of peaks F and PM.j.1, i=O, 1, 2 M/2-1 of the correlation signal to obtain M/2 multiplied peaks; -a decoder for decoding information based on the phases of the multiplied peaks.
  54. 54. An apparatus for synchronising a received data structure, the apparatus comprising: -a receiver for receiving a data structure; -a first correlator for correlating a synchronisation zone of the received data structure with a first sequence based on a sequence ZC1 to obtain a first correlation signal; -a second correlator for correlating the synchronisation zone of the received data structure with a second sequence based on a sequence ZC2 to obtain a second correlation signal; -a first delay module for obtaining a first set of M delayed correlation signals x0(i), wherein each delayed correlation signal of the first set is obtains by delaying the first correlation signal by an amount ixD, i=O, 1, 2 M-1, wherein D is equal to the length L of the sequence ZC1; -a second delay module for obtaining a second set of M delayed correlation signals x1(fl, wherein each delayed correlation signal of the second set is obtains by delaying the second correlation signal by an amount jxD, j=O, 1, 2 M-1, wherein D is equal to the length L of the sequence ZC2; -a combiner for obtaining 2M combined signals, wherein each combined signal S is computed according to Equation 4, where the M values b, i=O, 1, 2 M-1 each comprises a value selected from a first value (0) and a second value (1), wherein each combined signal is obtained using a unique combination of values {b}; -a peak detector for detecting one or more peaks in the combined signals; and -a decoder for determining the combination of values {b} associated with the combined signal that includes the peak with the largest magnitude.S = t x,2÷1 (1) x -1-i) Equation 4
  55. 55. An apparatus for synchronising a received data structure, the apparatus comprising: -a receiver for receiving a data structure; -a slide window correlator for correlating a synchronisation zone of the received data structure with a first sequence based on a sequence ZCO to obtain a correlation signal; -a delay module for delaying the correlation signal to obtain two or more delayed signals; -a signal combiner for obtaining two or more combined signals, wherein each combined signal is obtained by combining a respective set of delayed signals, wherein the delayed signals forming each set of delayed signal are delayed by amounts corresponding to delays of respective predetermined delay peak patterns; -a comparator for comparing the magnitudes of the combined signals; -a decoder for determining a signalling value based on a result of the comparison.
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