GB2511541A - Field effect transistor device - Google Patents

Field effect transistor device Download PDF

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Publication number
GB2511541A
GB2511541A GB1304048.0A GB201304048A GB2511541A GB 2511541 A GB2511541 A GB 2511541A GB 201304048 A GB201304048 A GB 201304048A GB 2511541 A GB2511541 A GB 2511541A
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Prior art keywords
laaio3
electron
srtio3
hole
gas
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GB1304048.0A
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GB201304048D0 (en
GB2511541B (en
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Stuart Holmes
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Toshiba Europe Ltd
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Toshiba Research Europe Ltd
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Priority to GB1304048.0A priority Critical patent/GB2511541B/en
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Priority to JP2014044370A priority patent/JP5710814B2/en
Priority to US14/198,987 priority patent/US20140253183A1/en
Publication of GB2511541A publication Critical patent/GB2511541A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass
    • H10N99/03—Devices using Mott metal-insulator transition, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details

Abstract

A semi-metallic structure comprising a LaA1O3 / SrTiO3 heterostructure 19 is used for fabricating a field effect transistor active layer. The LaAIO3 ­/SrTiO3 heterostructure comprises a two-dimensional hole gas 21 at the LaAIO3 ­ surface and a two-dimensional electron gas 23 at the interface between the TiO2 terminated SrTiO3 substrate surface and the LaAIO3 layer. The electron and hole gasses are generated under red or infrared photo illumination at a temperature of less than -243oC.

Description

I
Field effect (Eftusistor device
FIEJJ) Embodiments of the present invention are concerned with the field of semitnetals and their use in electronic devices.
BACKGROUND
1 0 Field effect transistor (PET) devices usc an electric held to modulate the conductivity of a conduction channel, Metaloxide-semiconductoi' field-effect transistors (MOSF'E'l's) are currently the most common type of transistor used iii digital and analogue circuits.
Complementary metal-ox udc-scniicouduc.or (CMOS) devices employ complementary pail's of MOSFETs as logic gates. Logic devices employing CMOS schemes are widely used iii the electronics industry.
There is a continuing need to improve the efficiency and reduce the size of CMOS devices.
BRIEF DESCRIPTION OF'i' DRAWiNGS
Embodiments will now be described with rerence to the following figures: Figure 1 is a schematic of a structure according to an embodiment; Figure 2 is a schematic of the band structure of a structure according to an embodiment; Figure 3(a) is an electronic device according to an embodiment in an "off state" configuration; Figure 3(b) is an electronic device according to an embodiment in an "on state" N-type configuration; Figure 3(c) is an electronic device according to an embodiment in an "on slate" Ptype configuration; Figure 4 is an electronic device according to an embodiment; Figure 5(a) shows the persistent pliotoconductivity in three devices according to an embodiment; Figure 5(b) allows the inagnetoresistance in Pvc devices according to an embodiment; Figure 6(a) shows Shubnikov-de Haas oscillations of the magnetoresistance of a device according to an embodiment; Figure 6(b) shows a fit of Landau level harmonic index against I/B for the Shubnikov-de ilnas minima shown in Figure 6(a); Figure 7 shows magnetic field modulation measurements for a device according to an embodiment; Figure 8(a) shows hole density enhancement for negative gate bias for a device according to an embodiment; Figure 8(b) shows electron density depletion with negative gate bias for a device according to an embodiment; Figures 8(c) and (d) show changes in resistivity with gate bias for two devices according to an embodiment; and Figure 9 shows Hall resistance measurements for a device according to an embodiment.
ugl'AILED DES'CRLPTION OF"I'Iffl DRAWINGS In an embodiment, a semi-metallic structure is provided, said structure comprising an LaAIO3 -SrTiO3 heterostructure, said LaA1O3 -SrTiO3 heterostructure comprising a two-dimensional hole gas and a two-dimensional electron gas.
The structure may exhibit persistent photoconductivity following illumination with a red or infrared illumination source. The structure may exhibit persistent photocoiiductivity following a illumination with a red or infrared illumination source at temperatures below -243°C. The structure may exhibit persistent photoconductivity following illumination with a red light emitting diode. l'he structure may exhibit persistent photoconductivity following illumination with a light emitting diode with a peak wavelength of G3Onm.
The LaA1O3 -SrTiO3 heterosti-ucturo niay comprise an SrTiO3 substrate and an LaAIO3 surthce layer. The SrTiO3 substrate and LaAIO] surface layer may have perovskite structures. The LaAIO3 surface layer may comprise alternating layers of (LaOf and (AlO»=y. The LaAIO3 surface layer may comprise alternating overlying layers of (LaO and (A102y, The alternating 1 0 layers of (LaOf and (Al02) may overlie each other in the [00 lJ direction. The SrTiO3 substrate may comprise alternating layers of Ti02 and SrO. The SrTiO3 substrate may comprise alternating overlying layers of Ti02 and SrO, The alternating layers of Ti02 and SrO may overlie each other in the [0011 direction. The LaAIO3 surface layer comprises a surface, The LaAIO3 surface layer may be terminated at the surface by a layer of A102.
rue LaAIO3 SrTiO3 heterostructure comprises an interface. The interface may comprise a layer of (LaO)' adjacent to a layer of Ti02. The SrTiO3 substrate may be terminated at the interface by a layer of Tb2. The LaAIO3 layer may be terminated at the interface by a layer of (L.aO. The electron gas may be located at the interface. The hole gas may be located at the surface. The thickness of the LaAIO3 surface layer may be between 3 and 10 unit cells inclusive.
The thickness of the LaAIO3 surface layer between the surface and the LaATO3/SrTiO3 interface may be 10 unit cells. The thickness of the SrTiO3 substrate may be up to 1mm. The thickness of the SrTiO3 substrate layer may be between 500 microns and 1mm.
In another embodiment, an electronic device is provided. The electronic device comprises a seini-nielallic structure, said structure comprising an LaAIO3 -SrIi03 lieterostructure, said LaAIO3 -Srl'i03 heterostructure comprising a Pvo-dimensional hole gas and a two-dimensional electron gas. The electronic device may further comprise a first back-gate electrode on a surface of s-aid SrTiO3 substrate; a first source electrical contact; and a first drain electrical contact. The first source electrical contact and the first drain electrical contact may be in ohmic contact with both the two-dimensional hole gas and the two-dimensional electron gas. The device may comprise a voltage source configured to apply a bias voltage between the back-gate electrical contact and ground. The device may comprise a voltage source configured to apply a bias voltage between the first source electrical contact and the back-gate electrode. The device may comprise a voltage source configured to apply a voltage bias between the soul-ce electrical contact and the drain electrical contact. The hole density of the two-dimensional hole gas may increase and the electron density of said two-dimension electron gas may decrease upon application of a negative bias voltage to the back-gate electrode relative to the source electrical contact. The hole density of the two-dimensional hole gas may increase and the electron density of said two-dimension electron gas may decrease upon application of a negative bias voltage to the backgate.
The electronic device may further comprise a front gate electrode. The front gate electrode may be on the surface of the LaAIO3 surface layer, The front gate electrode may comprise MgO, A1203 or SrTiO3. The device may comprise a voltage source configured to apply a bias voltage between the front gate electrode and the source electrical contact. The density of holes in the hole gas may be modulated by modulating the bias voliage applied to the front gate electrode relative to the source electrical contact. The density of holes iii the hole gas may decrease upon application of a positive bias voltage to front gate electrode relative to the source electrical contact, In yet another embodiment, a method for fabricating a scull-metal structure is provided, wherein said semi-metallic structure comprises an LaAIO3 -Sr'1i03 heterostructure comprising a two-dimensional hole gas and a two-dimensional electron gas. The fabrication method comprises: depositing LaAIO3 on a Ti02 terminated SrTIO3 substrate, wherein said depositing is performed under an oxygen pressure of at least i03 mbar and at a temperature of at least 800°c; heating said structure to a temperature of at least 800°c, and cooling said structure to ambient temperature, wherein said heating and cooling of said structure arc performed while exposing said structure to an oxygen pressure of greater than 0.lmbar; and illuminating said structure using a red or infrared illumination source at temperatures less than -243°C. The illuminating may be done using a red light illuminating source. The illuminating may be done using an LED with a peak wavelength of 630nm.
The fabrication method may further conlpt'isc loi'ming a back-gate electrode on a first surface of said heterostructure; forming a source electrical contact such that said source electrical contact is in ohmic contact with both said two-dimensional hole gas and said two-dimensional electron gas; and forming a drain electrical contact such that said drain electrical contact is in ohmic contact with both said two-dimensional hole gas and said two-dimensional electron gas. The fabrication method may also comprise forming a front-gate electrode on a second surface of said heterostructure. The Thbrication method may comprise depositing single atomic layers of LaAIO3. The fabrication method may comprise pulsed laser deposition growth of LaAIO3, The pulsed laser deposition growth may be epitaxiaL Figure I shows a schematic of a structure 19 according to an embodiment. The structure comprises a substrate 13 of SrTiO3, overlying which is positioned a layer 11 of LaAlO3, The layer 11 of LaAIO3 interfaces dh-eel[y with the SrTiO3 substrate 13 such that there exists an interface 15 between them. The layer 11 of LaAIO3 comprises a surface 17. Tn an embodiment, the thickness between the interface 15 and the surface 17 of the layer 11 of LaAIO3 is 3 to 10 unit cells. In an embodiment, the thickness of the SrTiO.3 substrate 13 is 500 pm to 1mm.
The SrT1O3 substrate and LaAIO3 layer of the structure shown in Figure 1 are perovskite structures, Perovskite structures are structures with the general formula ABX3 having the crystal structure of CaTiO3. The cubic unit cell of this crystal structure comprises cations "A" located at corner positions (0,0,0); smaller cations "B" at body centred positions (1/2, 1/2, 1/2); and anions "X" at face centred positions (1/2, 1/2, 0). The structure of the perovskite unit cell gives rise to a layered crystal structure. For example, in the [001] direction, LaAIO3 comprises alternating overlying layers of (Al02) and (LaO)'. Similarly, in the [001] direction, SrTiO3 comprises alternating overlying layers of Ti02 and SrO.
In an embodiment, the surface 17 of structure 19 comprises a layer of (Al03)'. Equivalently, the LaAlO3 layer 11 is terminated at the surface 17 by a layer of (AlO2). In another embodiment, the interface 15 comprises a layer of (LaO)+ overlying a Layer of Ti02. Equivalently, the LaAlO3 layer 11 is terminated at the interface 15 by a layer of' (LaO) and the SrTiO3 substrate 13 is terminated at the interface by a layer of Ti02. The layer of LaO)t interfaces directly with the layer of Ti02.
Structures, such as that shown in Figure 1, comprising more than one crystalline material with a perovakite structure, are known as perovskite heterostrucutres. At the interface between Iwo crystalline materials (heterointerfaee), a layer belonging to one of the materials is overlying a layer belonging to the other. Differences in the electrical properties of the two materials can give rise to changes in hand structure neal' the interface and alter the electrical properties of the bulk material.
In an embodiment, the structure of figure 1 is characterised in that it is insulating in the dark at low temperatures but becomes conducting upon illumination with a red or infrared illumination
U
source, exhibiting a strong persistent photoconductivity effect with below band gap excitation.
In a further embodiment, the structure comprises both a high-mobility electron gas at the heterointerface 15 and a high inability hole gas at the (Al02) terminated surface 17 of the LaAIO3 layer II. In yet a further embodiment, due to the close spacing between the electron and hole gases, Ike seinimetallic system is unstable towards exciton formation leading to Bose-Einstein condensation. Thus, the slt'ucture has an excitonic insulating grotmd stale. However, the high mobility two-dimensional hole gas, in coexistence with an election gas at the hetero-interface, is stabilized by illumination with a red or infrared light emitting diode, In this embodiment, the LaAIO3 surface layer can then sustain the large built-in electric fields required (-lV/nm), to form a stable electron-hole gas and the structure exhibits spatially separated electron-hole bilayer behaviour in this excited state.
In an embodiment, in order to excite the structure 19 from its excitonic insultating ground state to its excited bilayer (semi-metal) state, structure 19 is illuminated with a red or infrared light emitting diode. In another embodiment, the structure 19 is illuminated with a red tight emitting diode, In a further embodiment the structure 19 is illuminated with a red light emitting diode with a peak wavelength of 630nm.
i a the structures according to the shove described embodiments, the hole mobility at the surface of the heteorostructure is high enough that a spin-split band structure can be observed in moderate applied magnetic fields. However, electrons still play a significant role at the LaAIO3/SrTiO3 interface in the overall transport properties leading to electron-dominated semimetallic behavior. In an embodiment, the quantum mobility of the hole gas is greater than 10,000 cm2/Vs at 1.7K. In another embodiment, the FlaIl mobility of the electron gas is greater 26 than 1,000 cm2/Vs at 1,7K.
Figure 2 shows the schematic band structure of the structure shown in Figure 1, according to an embodiment. l'he band structure shows the Ti02 terminated SrTiO3-LaAIO3 interface showing the surface hole gas and the election gas at the interface. l'he x-axis indicates distance from the surface of the structure 17; increasing x corresponds to increasing distance from the surface 17.
The y-axis indicates band energy; increasing y corresponds to increasing energy. The Fermi level E is indicated, From the band structure it is evident that the structure is a semi-metal. The valence band of SrTiO3 curves below the Fermi level near the interface 15 such that there is electron density 23 in the valence band at the interface. Consequently, the structure comprises a 36 two-dimensional electron gas at the interface 15. Conversely, the conduction band of LaAIO3 curves above the Fermi level at the surface 17 of the heterostructure such that there are vacancies 21 in the conduction band at the surface. Consequently, the structure comprises a two-dimensional hole gas at the surface 17.
S In an embodiment, the carl-icr density of the electron gas is greater than lxlOUcm_2. In another embodiment, the carrier density of the hole gas is greater than lxi &cin2.
Structures according to embodiments described above comprise high mobility conducting oxide interfaces with electron behavior and surfaces with hole like behavior. Such structures can host Bose-Einstein condensed excitonic insulators and find applications in logic devices such as the CMOS oniplementary metal oxide semiconductors) schemes that now dominate the electronics industry. Closely spaced electron-hole gases also provide a practical system for a superconducting state.
Figure 3 shows three configurations of an electronic device according to an embodiment. The electronic device comprises the LaAIO3/SrTiO3 heterostructure 19 shown in Figure 1 and described above, with layer 11 of LaAIO3 and SrTiO3 substraie 13 which directly interface at lieteroEpterface 15; a source ohmic contact 41; a drain ohmic contact 43; and a hackgate electrical contact 45.
The source ohmic contact 41 and drain ohmic contact 43 interface directly with both LaAIO3 layer 11 and SrTiO3 substrate 13. Both contacts 41,43 are in ohmic contact with both surface 17 and interface 15. Both contacts interface directly with respective leads (not shown). The device comprises a voltage source configured to apply a voltage bias between the drain and source contacts.
The backgate electrode 45 interfaces directly with a surface of the SrTiO3 substrate. The baekgatc electrode interfaces directly with a lead (not shown). i'he device comprises a voltage source configured to apply a voltage bias (baekgate voltage) 47 between the backgate electrode and ground (baekgate voltage). Examples of commercially available devices suitable for supplying the back-gate voltage are Keithley 2602 and Keithley 236 source-measure-units.
In an embodiment, the source 41, drain 43 and back gate 45 electrical contacts comprise evapourated titanium gold. In a further embodiment, the electrical contacts are unannealed. In a an embodiment, the device comprises a Hall-bar patterned mesa with source and drain contacts; two contacts for resistivity and two contacts for the Hall effect.
Jn an embodiment, the source and drain contacts are separated by less than l400pm. In an embodiment, the LaAIO3 surface byer is 3 to 10 unit cells thick. In another embodiment, the SrTiO3 substrate 13 is 500 m to 1mm thick.
Figure 3(a) shows the device according to an embodiment in an "off state" configuration. In this configuration the baekgate voltage (VbgO) is zero (with respect to ground). The structure 19 is in an insulating state, upon application of a voltage bias between source 41 and drain 43 electrical contacts, a current will not flow between them; the device is "off'.
According to one embodiment, in this configuration, structure 19 is in the excitonic insulating ground state described above. In this embodiment, structure 19 comprises neither an electron 23 nor a hole gas 21 and hence there are no mobile charge carriers in the structure.
According to another embodiment, in this configuration, structure t9 is in the electron-hole hilayer excited state (semi-metal state) described above, In this embodiment, the structure 19 comprises both an electron ga.s 23 at the interface 15 and a hole gas 21 at the surface 17. While there are mobile charge carriers in the structure 19, the device is configured such that at Vh5O, neither the carrier density in the hole gas 21 nor the carrier density in the electron gas 23 is sufficient to enable conduction.
Figure 3(b) shows an "on state" N-type configuration of the electronic device described above according to an embodiment. A positive voltage bias is applied to the backgate electrical contact relative to ground (baekgate voltage, Vbg).
In this configuration, the structure 19 is in the electron-hole bilayer excited state (semi-metal state) dcscribcd above and comprises both liolc 21 and an electron gas 23. A positive backgatc voltage 47 enhances the electron density in the two-dimensional electron gas 23 and depletes the hole density in the hole gas 21 relative to their respective densities at VbO. The electron density at the backgate voltage of the configuration shown Figure 3(h) is sufficiently large as to enable conduction via the electron gas 13.
When a bias voltage is applied between source 41 and drain 43 electrical contacts, a current flows between the two electrical contacts via a conduction channel comprising the two dimensional electron gas 23 at the interface 15 of the structure 19. thus, the device acts as an N-type electrical conductor.
hi an embodiment, the baekgate voltage of the configuration of Figure 3(c) is sufficiently positive as to deplete the hole gas 21 such that the density of holes is insufficient for electrical conduction through the structure to occur via the hole gas 21, Tn another embodiment, the backgate voltage of the configuration of Figure 3(c) is sufficiently positive as to enhance the electron gas 21 such that the electron density is sufficient to enable electrical conduction through structure 19 via the electron gas 21.
In an embodiment, the magnitude of the bias voltage required to obtain the configuration of figure 3(b) can be modulated by adjusting the layer thickness of the SrTiO3 substrate 13 and/or the thickness of the LaAIO3 surface layer. In an embodiment, the backgate voltage is larger than V. Figure 3(c) shows an "on state" P-type configuration of the electronic device according to an embodiment. The backgate voltage \1b5 47 is negative.
In this configuration, the structure 19 is in the electron-hole bilayer excited state (semi-metal state) described above and comprises both a hole 21 and an electron gas 23. A negative backgate voltage enhances the hole density iii the two-dimensional hole gas and depletes the electron density in the electron gas relative to their values at VbgO. The hole density at the backgate voltage of the configuration shown Figure 3(c) is sufficiently large to enable conduction via the hole gas 21.
When a bias voltage is applied between source 41 and di-ain electrical 43 contacts, electrical current flows via a conduction channel comprising tile t\VO dimensional hole gas 21 at the surface 17 of the structure 19, Thus the device acts as an P-type electrical device.
ln an embodiment, the baekgatc voltage of the configuration of Figure 3(c) is sufficiently negative as to deplete the electron gas such that the density of electrons is insufficient for electrical conduction via the electron gas 23. In another embodiment, the backgate voltage of the configuration of Figure 3(c) is sufficiently negative as to enhance the hole gas 21 such that the electron density is sufficient to enable electrical conduction through structure 19 via hole gas 21.
In an embodiment, the magnitude of the bias voltage required to obtain the configuration of figure 3(e) can be modulated by adjusting the layer thickness of the SrTiO3 substrate 13 and/or the thickness of the LaAIO3 surface layer II. In an embodiment, the backgato voltage is loss than 0 V. In one embodiment, the "off state" of the device comprises the structure 19 in its excitonic insulating ground state, described above. In this embodiment, in order to switch between the "off state" and one of the "on states" described above, in addition to applying a backgate voltage bias, the device is illuminated with a red or infrared LED. In an embodiment, the illumination is carried out at temperatures of less than -243 °C. In another embodiment, the device is illuminated with a red LED with a peak wavelength of 630um.
In another embodi neat, the "off state" of the device comprises the structure 19 is in its seminietal state. In this embodiment, the device is configured such that at a baekgatc voltage of zero, the electron density or hole density of either election gas 23 or hole gas 21 respectively is insufficient to enable electrical conduction through the structure. In this embodiment, switching of the device from the "off state" to one of the "on states" described above requires the application of a non-zero backgate voltage bias alone. Examples of commercially available devices suitable for supplying the back-gate voltage are Keithley 2602 and Keithley 236 source-measure-units.
lhe all-oxide device according the embodiment of Figure 3 exhibits combined N and P-type conducting behaviour. Switching between the two "on states" can be achieved by modulating the backgate voltage 47.
Figure 4 shows an electronic device in accordance with another embodiment The electronic device comprises the T,aAlO3/SrTIO3 heterostructure 19 shown in Figure 1 and described above, with LaA1O3 layer 11 and SrTiO3 substrate 13 which directly interface at heterointerface 15; a source ohmic contact 41; a drain ohmic contact 43; and a backgate electrical contact 45.
The source ohmic contact 41 and drain ohmic contact 43 interface directly with both LaAIO3 layer 11 and SrTiO3 substrate 13. Both contacts 41,43 are in olunic contact with both surface 17 and interface 15, Both contacts interface directly with respective leads (not shown). The device comprises a voltage source configured to apply a voltage bias between the drain and source contacts (not shown).
The backgate electrode 45 interfaces directly with a surface of the SrTiO3 substrate. The backgate electrode interfaces directly with a lead (not shown). A voltage bias 47 can be applicd between the backgate electrode and ground. Examples of commercially available devices sutable for supplying the back-gate voltage are Keithley 2602 and Keithley 236 source-measure-units, In an embodiment, the source 41, drain 43 and back gate 45 electrical contacts comprise evapourated titanium gold. In a further embodiment, the electrical contacts are unannealed. In an embodiment, the device comprises a Hall-bar patterned mesa with source and drain contacts, two contacts for resistivity and two contacts for the Hall effect, In an embodiment, the source and drain contacts are separated by less than l400pm. In an embodiment, the LaAIO3 surface layer is 3 to 10 uhf cells thick. Ta another embodiment, the SrTiO3 suhsti'atc 13 is 500 tm to 1mm thick.
The electronic device further comprises a front gate electrode 49. The front gate electrode 49 is insulated. The metal electrode interfaces directly with an insulator 51 which iii turn interfaces directly with the surface 17 of the LaAlO3 layer 11. A lead (not shown) interfaces directly with the fi-ont gate electrode 49. A voltage bias may be applied to the gate electrode relative to the source electrical contact (front gate voltage).
In an embodiment, the insulator 51 comprises a high-dielectric-constant material. In a further embodiment, the insulator 51 comprises MgO, A1203 or SrTiO3. In an embodiment the gate electrode 49 comprises!i-Au.
Whcn structure 19 is in its. .eini-metallic hilayet' excited state (semi-metal state), discussed above, the density of holes in the two-dimensional hole gas 21 can he modulated by adjusting the voltage applied to the front gate 53. relative to the source electrical contact (flora gate voltage). When the front gate voltage is negative, the hole gas is enhanced as electrons are repelled from the surface of the structure 19. Consequently, the hole density increases and conduction via the hole gas increases. When the front gate voltage is positive, electrons are attracted to the surface of the structure. Thus, the number of holes decieases and the density of the hole gas decreases. In this case, the conductivity of the hole gas decreases.
CMOS (complementary metal-oxide semiconductor) devices employ pairs of N-and P-type field effect transistor devices to form logic gates. CMOS schemes are vel1 known iii the art and will not be discussed iii detail here. The device according to the embodiment of Figure 3 may be employed in such a scheme; the N-type "on-state" may be utilized in place of a N-type metal- oxide-semiconductor NMOS) and the P-type "on state" maybe used in place of a P-type metal-oxide-semiconductor.
Structures and devices according to the embodiments described herein have wide a band gap between valence and conduction bands. Wide band gaps are advantageous in electronic devices as they ensure that the operation of such devices is possible even at high temperatures. When small band gaps are present in a device, increased temperatures can result in thermal population 1 5 of the conduction band which may alter carrier density and therefore the conduction properties of the device. Further, the band gap is direct meaning thtt the devices according to the embodiments described above are optically sensitive.
As MOSFET devices become increasingly small, quantum mechanical tunneling between the gate electrode and the conduction channel through the gate insulator can occur, leading to increased power consumption. High-k materials prevent leakage due to tunneling even at high gate capacitance and are therefore increasingly used in MOSFET devices as gate oxide materials. Materials \vith a high dielectric constant, k, enable the production of smaller devices without reduction in device reliability and gate current leakage. Compatibility with high-k materials is therefore desirable. Structures according to the embodiments described herein are compatible with materials with a high dielectric constant. Indeed, SrTiO3 has a dielectric constant of 300 at room temperature.
The electron carrier density of the structures and devices according to the embodiments discussed above is greater than lxl0'3cm2. Higher electron calTier density correlates with decreased resistivity in the forward bias. Larger carrier densities may therefore lead to improved efficiency in electronic devices.
Preparation [a an embodiment, the LaAIO3/SrTiO3 heterostructure is fabricated by expitaxial pulsed laser deposition of LaAIO3 on single crystal, hO2 terminated SrTiO3 substrates. An example of a laser suitable for use in pulsed laser deposition is a KrF exeimer laser operating at 248nm and a laser fluenee of-1 J/em2.
in an embodiment, the StTiO3 substrate is 500 pm to 1mm thick. In a further embodiment, single atomic layers of (single crystal) LaAIO3 are deposited at temperatures of at least 800 °C tinder oxygen at a pressure of at least i03 mbar. In yet a Thither embodiment, the layer of deposited 1aAlO3 is 3 to 10 unit cells thick.
In an embodiment, the structure is annealed by exposing it to oxygen pressure of at least 0.1 mbar at a temperature of at least 800 °C and cooling to ambient temperatures under the same oxygen pressure. In an embodiment, the structure is then illuminated using a red or infrared light emitting diode. An example of an LED suitable for use iii illumination of the structure is a red LED providing 63Onni wavelength illumination. In an embodiment, the illumination is carried out at a temperature of less than -243 °C.
In an embodiment, an electronic device is fabricated from the L.aAlOj/SrTiOj heterostructure prepared as described above. In an embodiment, Hall-bar shaped mesas are farmed using optical photolithography and Ar ion beam etching to remove the unwanted LaAIO3 from the mesa. In a further embodiment, a back gate is thennally evaporated onto the back of the SrTiO3 substrate.
In an embodiment, the back gate comprises titanium gold. In an embodiment, ohmic source and drain contacts are thermally evapourated onto the device. In an embodiment, the source and drain contacts comprise titanium gold. In an embodiment they are not annealed. In an embodiment source and drain contacts fabricated such that they are separated by less than 1400 p.m and the channel width is less than 80 u. In an embodiment, they are fabricated such that they are in ohmic contact with both electron gas and hole gas.
In an embodiment, a tiont gate electrode consisting of fl-Au is forrncd on the surtäce of the LaAlO3 surface layer.
In an embodiment, voltage probes ale fabricated from Ti-Au with thickness 20 nni of Ti and nm ofAu.
Experimental Results Three devices A, B and C according to an embodiment of the present invention were prepared by pulsed laser deposition of LaAIO3 on single crystal, 1102 terminated SrTiO3 substrates.
Single atomic layers of' (single crystal) LaATO3 were deposited at 800 °C under oxygen at 10 mbar. A KrF excinier laser (at 248 urn) was used for the ablation of' the LaAlO3 targeL material at a laser tlucncc of' 1 J/ctn2.
After growth the samples were exposed to a high oxygen pressure (-0.1 inbar) for in-situ annealing at 800 °C for 15 minutes. It was then cooled to ambient temperature at the same 1 0 oxygen pressure.
A, B and C were formed from a single growth of 10 unit cells of LaAIO3. Hall bar shaped mesas were formed using optical photolithography and Ar ion-beam etching. A titanium gold (Ti-Au) back gate was thermally evaporated on the back of the 500 pm thick SrTiO3 substrate so that a substrate bias (Vbg) could be applied to the device. The SrTiO3 substiate remained insulating after all levels of processing. The source and drain ohmic contacts were fabricaLed with thermally evaporated but unannealed l'i-Au. These contacts are suitable as both electron and hole gas contacts.
No leakage current (from -30 to -I-SO Vh) was observed between the back gate contact and the source-drain contacts. The channel width was 80 tm, the voltage probes had length-to-width ratios of 4.2 and the source and drain contacts were separated by 1400 pm.
Hall bar devices were measured with a source-diain current of 100 nA at 33 lIz. The gate voltage was supplied either from a Keithley 2602 or Keithley 236 source-measure-unit through a low pass filter. A magnetic field could be applied from -8 to 8 1' with a variable temperature range from 300 K to 1.7K. 1'he temperature was measured with a calibrated cernox sensor close to the device. An in-situ LED provided red (630 nm) wavelength illumination. The ac voltages corresponding to R, and were preamplified then measured with Stanford SRR3O lockin amplifiers, The samples were insulating in the dark at low temperature. This is due to the the 1O mbar partial pressure of 02 during growth combined with the high pressure anneal. The three devices were illuminated in-situ by a red LED (630 am peak wavelength) at the base temperature of 1.7K.
Figure 5(a) shows the persistent conductivity effect in the three electronic devices A, B and C. In the main figure, resistivity is plotted as a function of temperature. Results are shown for device A before (labelled "dark") and after (labelled "light") illumination and for device B before illumination.
The low resistance state after illumination is stable until the temperature is increased above 40 K. However, minor abrupt changes in device A do occur (-1 OK) in device A on warming as can be seen in figure 5(a). Initially the resistance of device A goes beyond the measurement range as the temperature is lowered, but via a PPC effect the sample becomes semimetallic at 1.7 K having a similar conductance values to other devices from the same wafer. In the case of device A the PPC effect remains stable over a relatively long period (dpaldt <+1.5 io QIo per second) of measurement time (t l0 s) at 1.7 K. Device B follows a similar resistivity (Po) trend Pa T2 (for temperature T >77 K) to Fermi liquid behaviour of an electron gas. Fermi 1 5 liquid behaviour is well known in the art and will not be discussed here.
In the inset to figure 5(a), conductivity o after illumination (sr_axis) is plotted againsi the conductivity o before illumination (x-axis) for all three devices A, B and C at 1.7K, i.e. the before and after illumination conductivities for the three nominally identical devices. In all cases the conductivity increases (indicated by the shaded area) persistently to 4000 tS after illumination at 1.7 K. The persistent photoconductivity (PPC) effect is stronger in devices that are insulating in the dark at 1.7 K. Devices fabricated in the same growth chamber with a low oxygen pressure growth (10.6 inbar) show no PPC effect.
Figure 5(b) shows the magnetoresistance in a perpendicular magnetic field at 1.7 K for devices A and B. The change in magnetoresistance AR.1 is plotted as a thnction of magnetic field, B. The zero field resistivities (Pa) are indicated for the two devices; Po = 208Q / SQR for device A and Pc = 208Q / SQR for device B. The magnetoresistance for device B is plotted for a perpendicular field and the magnetoresistance for device A is indicated for both perpendicular and parallel fields (the parallel field giving rise to negative ARC).
Magnetoresistance (MR) measurements were made up to 8 T with an ac current of 100 nA at 33 Hz. Oscillatory structure is present in the magnetoresistance of device A from the surface hole gas in a perpendicular magnetic field (B), i.e. along the [001] direction of SrTIO3. The oscillation is superimposed on a positive magnetoresistance due to electron and hole multiband conduction contributing to a large classical background resistivity. These oscillations are due to the Shubnikov-de Haas effect on the hole gas at the surface of the LaAIO3 layer, The Shubnikov-de Haas effect is vell known in the art and will not be discussed in detail here. The oscillatory structure in device A disappears with a negative background MR when the field is applied in-plane (i.e. parallel). This is known from the art to be consistent with Lwo-dimetisional behaviour. Device B shows a similar positive magnetoresistance in a perpendicular field without an oscillatory structure superimposed on it.
I 0 Figure 6a shows the magnetoresistance for device A, with a parabolic background subtracted to enhance oscillatory structure due to the Shubnikov-de flaas effect, plotted as a function of magnetic field, for three values of the backgate voltage Vb8: VbgS, 0 and+50 at 1,7K. The dotted lines show the minima at u= 4 and 6 for Vb = 0 V. Other filling factors are labeled. A spin-splitting is apparent at odd filling factors 3, 5 and 7. Shubnikov-deHaas oscillations from the hole gas can be clearly seen down to a Landau level filling factor (u) of 12 and are periodic in 1/B. The oscillations start at B I T, corresponding to a quantum mobility (Jig) of 10,000 cm2/Vs.
Figure 6(b) shows a fit of landau level harmonic index against 1/B for the SllLlbnikov-de Haus minima at thrce different back gatc voltages Vbg -SV, OV and -I-50V. A Fast Fourier Transform (FF1') of the oscillatory structure due to the hole gas in lID is shown in the inset for the ease of = 0 V-Fast Fourier Transform of Shuhnikov-dellaas oscillations is a standard technique for determining fundamental fields, multiple subband effects including spin and the actual carrier densities. The quantum mobility (Lq) of the carriers involved can also be determined from the FF1'. If the 1⁄4 width at 1⁄4 height of the peak in the FFT is B, then: 2 SB providing that the Shubnikov-deHaas oscillations in p for a band (electron or hole) with a carrier density of if I p (B)oc.cos( ) n3 can be described by: 2cR Another common niethod is to apply a (4113 1) 1 14= FVF to dpIdB, iii which case 2 oR I'he second harmonic in thc FFT is due to spin-splitting at u=3, 5 and 7 being included iii the field domain of the FFT. The results show that the hole gas has no Berry phase and the oscillations are strictly 1/B periodic. The fundamental field (SF) is 6.5 T with a harmonic peak at 13 1'. Ihis harmonic peak is a mathematical artifact arising from including spin-splitting in the magnetic field domain for the FFT, rather than being a second hole subband or due to a higher density electron gas. The /2 width at LA height of the F power spectrum peak (6B) is 0.9±0.1 T corresponding to a quantum mobility Pq 13500±1500 cm2/V.s. There is a systematic shift of the oscillatory structure depending on carrier accumulation or depletion, confirming tile hole-like behaviour of these oscillations in response to a back gate field.
Figure 7 shows the analogue signal dRJdB in device A for Yb; = 0 V at 1.7 K up to 5 T. The dotted lines show tile Shuhnikov deT-laas minima positions (labeled by filling factor) expected for a hole carrier density of 3 101] cm2. The inset shows the same data set with a polynomial to order B2 subtracted from dR,JdB. The units ott the axes for the inset are the same as the main graph. This technique is an alternative method of measuring oscillatory niagnetoresistance behavior. A dc current ( 100 nA) is applied to the source-drain contacts and a small ac magnetic field (typically up to 10 mT) is applied to the device on top of the steady magnetic field. Analogue dRjdB measurements for device A iii a modulated magnetic field (16 mT at 33 Hz in this case) show a weak Shubnikov-deHaas effect signal due to the large background signal (originating from R. -B2). The same oscillatoiy structure as observed in figure 6a can be secn, albcit in dR,JdB which has a phase changc in thc oscillations of g/2 compared to Figure 8 (a) shows the change in hole density (P) with gate bias Vbg in device A at 1.7K, The hole density is enhanced with a negative gate field. Two diffei'ent cool-downs (300 K to 1.7 K) are shown. Assuming that the valence band Fermi surface formed from 0 2p states is circular eBE then the hole density (P) can be calculated from: h where g is the valley degeneracy and g2 is the spin degeneracy. BF is the fundamental field of the Shubnikov-deflaas oscillations where the Landau Level harmonic index is 1. The valence band valley degeneracy is assumed to be 1, however this assumption does not change the interpretation that a hole gas with density loll cni2 is present in the structure.
Note that the hole-like Shubnikov-del-Iaas effect is not due to a hole-like clcctron orhit on the SrTiO3 Fermi surface at the intcrface that shrinks in extremal area with increasing the Fermi k vector (for example \vith positive gate field or illumination). This would require either an indirect band structure in SrTiO] or an artificially periodic structure on the length scale of the (LaO)-(AI0f perovskite planes.
Figure 8(b) shows the change in electron density NH,H with gate bias 4 in device B at 1.7 K. Again, two different cool-downs (300 K to 1.7 K) are shown. In this case, cool-down 1 is at Vb5 0 V and cool-down 2 is for Vbg = -30 V (bias cool-down). The electron gas is depleted with a negative gate field. With tile electron gas in enhancement mode an initia[ decrease in the carrier density is observed For the case of a bias cool down (cool-down 2 with 30 Vbg) designed to enhance any hole gas. Cool-down I (no bias on cooling; no hole-enhancement) does not show this effect. The capacitance of the electron gas is 1.7 l0' em2/V and the capacitance ofthe hole gas is 0.2 1010 csn2/V. This difference is due to efficient screening of the backgate field by the electron gas at the LaAIO3/SrTiO3 interface and confirms the spatial separation of the two charge systems, as shown in Figure 2. A strong hysteretic behavior is observed in RLX when changing the voltage on the backgate and this is paitly explained by the ferroeleetric response of the SrTiO3 substrate, All the devices tend to insulating behavior for strong electron depletion (-Vhg) but can be reset' at low temperatures via the PPC effect at Yb5 = 0 V. 1 5 Figures 8 (c) and (d) show are the corresponding changes in resistivity with backgate voltage V5 for device A and B respectively. Both are dominated by the electron density and i-esistivity decreases as electron density increases (see Figure 8(b)).
Figure 9 shows the Hall resistance of device B as a function of magnetic field 1.7 K up to 8 Tat V5= +10 V. The dotted line shows the expected behaviour for a single carrier type with a density of 1.7 1011 cm2. The inset shows the Hall constant (dRx3fdB) with noise (±2.5 % of the signal at 8 1) due to digital differentiation. Device B has a non-linear Hall resistance with magnetic field. The Hall resistance is magnetic field anti-symmetric, i.e. R(-B) = however occasional devices show a finite Hall voltage at zero field due to contact mis-alignment effects.
at zero field in device B is < 1.4 Q, tIns corresponds to a measured voltage of< 0.14 jiV for nA current. The non-linear Hall resistance (not due to mixing of the componeiit is due to a parallel conduction cffcct due to the electron and hoic gas that are connected in parallel via the Ti-Au Ohmic contacts.
The hole density cannot be uniquely determined fiom the Hall effect due to the dominance of the parallel conducting electron gas. From figures 8(c) and (d), devices A and B show an electron gas depleting with a negative gate field. [he Hall resistance (R) shows a linear behavior in magnetic field (up to -2 T) and the electron density (N) can be determined from dRX)JdB, see figure Sb. The non-linear Hall slope seen above 2 T in device B (figure 9) confirms the multiple carrier conduction effects, albeit electron dominated. The electron density is I.7 iD'3 cm in device B with a corresponding Hall electron mobility of 1500 cm2tV.s. This mobility is known from the art to be consistent with n-type conduction albeit with slightly higher mobility here.
At the high 02 pressure (1O mhar) used during the growth of these devices the electron gas is confined at or close to the LaAIO3/SrTiO3 interface and the structure is low in oxygen vacancies that would provide a source of n-type dopant. The electron gas is isolated from the unoccupied valence states at the surface through an insulating LaAlO3 layer without the influence of a high oxygen vacancy background. This combination of effects with such a clean system observed here is expected to be semimetallic from the polar catastrophe mechanism, with the Ti 3d-like conduction band at the interface and the 0 2p valence band partially full of electron states at the surface, as shown iii figure 2. The polar catasnophe mechanism is well knowi in the art and will 1 5 not be discussed here. The clean system reduces the tunneling or more likely hopping of electrons from the interface into the 0 2p valence band at the surface. Thc PPC effect with below band gap photons enhances both the electron gas and the hole gas and is partly an extrinsic charge effect in origin where the thermal barrier (kT) is 35 meV The hole mobility in principle should be lower than the electron gas reported at n-type interfaces, however the electron gas can screen potential fluctuations at the LaAIO3/SrTiO3 interface partly accounting for a high hole mobility. The Shubnikov-dcHaas effect shows a spin-splitting at odd Landau level filling factors and points to the importance of spin in understanding the structure of the 0 2p valence band.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. lndced, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents arc intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
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