GB2506275B - Method and system to fix early mode slacks in a circuit design - Google Patents
Method and system to fix early mode slacks in a circuit designInfo
- Publication number
- GB2506275B GB2506275B GB1315088.3A GB201315088A GB2506275B GB 2506275 B GB2506275 B GB 2506275B GB 201315088 A GB201315088 A GB 201315088A GB 2506275 B GB2506275 B GB 2506275B
- Authority
- GB
- United Kingdom
- Prior art keywords
- slacks
- circuit design
- early mode
- fix
- fix early
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/035,125 US9058456B2 (en) | 2012-09-25 | 2013-09-24 | Method and system to fix early mode slacks in a circuit design |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1217030.4A GB2506179A (en) | 2012-09-25 | 2012-09-25 | Fixing early mode slacks in a circuit design |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201315088D0 GB201315088D0 (en) | 2013-10-09 |
GB2506275A GB2506275A (en) | 2014-03-26 |
GB2506275B true GB2506275B (en) | 2014-08-20 |
Family
ID=47190511
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1217030.4A Withdrawn GB2506179A (en) | 2012-09-25 | 2012-09-25 | Fixing early mode slacks in a circuit design |
GB1315088.3A Expired - Fee Related GB2506275B (en) | 2012-09-25 | 2013-08-23 | Method and system to fix early mode slacks in a circuit design |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1217030.4A Withdrawn GB2506179A (en) | 2012-09-25 | 2012-09-25 | Fixing early mode slacks in a circuit design |
Country Status (1)
Country | Link |
---|---|
GB (2) | GB2506179A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9058456B2 (en) | 2012-09-25 | 2015-06-16 | International Business Machines Corporation | Method and system to fix early mode slacks in a circuit design |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011097460A1 (en) * | 2010-02-04 | 2011-08-11 | Qualcomm Incorporated | Segment and bipartite graph based apparatus and method to address hold violations in static timing |
US20120167030A1 (en) * | 2010-12-22 | 2012-06-28 | Advanced Micro Devices, Inc. | Method and apparatus for addressing and improving holds in logic networks |
US8255851B1 (en) * | 2008-06-24 | 2012-08-28 | Marvell Israel (M.I.S.L) Ltd. | Method and system for timing design |
-
2012
- 2012-09-25 GB GB1217030.4A patent/GB2506179A/en not_active Withdrawn
-
2013
- 2013-08-23 GB GB1315088.3A patent/GB2506275B/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8255851B1 (en) * | 2008-06-24 | 2012-08-28 | Marvell Israel (M.I.S.L) Ltd. | Method and system for timing design |
WO2011097460A1 (en) * | 2010-02-04 | 2011-08-11 | Qualcomm Incorporated | Segment and bipartite graph based apparatus and method to address hold violations in static timing |
US20120167030A1 (en) * | 2010-12-22 | 2012-06-28 | Advanced Micro Devices, Inc. | Method and apparatus for addressing and improving holds in logic networks |
Non-Patent Citations (1)
Title |
---|
Sutanthavibul S, Shragowitz E, " An adaptive timing driven layout for high speed VLSI", Processing of the ACM/IEEE design automation conference, Olranso, June 24-8, 1990, col. conf. 27, pages 90-95, ISBN: 978-0-89791-363-8 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9058456B2 (en) | 2012-09-25 | 2015-06-16 | International Business Machines Corporation | Method and system to fix early mode slacks in a circuit design |
Also Published As
Publication number | Publication date |
---|---|
GB2506275A (en) | 2014-03-26 |
GB201315088D0 (en) | 2013-10-09 |
GB2506179A (en) | 2014-03-26 |
GB201217030D0 (en) | 2012-11-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 20140909 |
|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20170823 |