GB2501347A - Processing data samples using thermometer codes - Google Patents

Abstract

An analogue to digital converter produces a series of values, Yn, encoded as thermometer codes. The values may be from a differential serial signal. The sequence of values is processed to produce one of two output values, -1 and +1, from each input value Yn. The values are processed as thermometer codes without converting them to another format. The processing may involve, for each value, Yn, determining if the magnitude of the next value, Yn+1, is greater than a threshold. If so, Yn is decreased if Yn+1 is positive and increased if Yn+1 is negative. The value of Yn is then compared with a threshold to determine which of the two output values it represents. This may be used as a feed forward equalizer. The required thermometer code comparator and increment circuits may be constructed from multiplexors with two inputs.

Description

METHOD OF PROCESSING DATA SAMPLES AND CTRCUTTS THEREFOR

The present invention relates to data manipulation and in particular incrementing, decrementing and comparing binary coded numbers. The invention encompasses the manipulation of thermometer codes and the performance of arithmetic operations thereon and in particular the implementation of thermometer code arithmetic in a receiver used in high speed data transfer applications.

The ever increasing complexity and speed of digital hardware, together with constraints of chip real estate and space, have made the problems of interconnecting components increasingly difficult in applications having a need for high speed communication. In many intensive data transfer environments such as super computers and switch or router back planes, high speed serial transceivers, known as SerDes (serialiser/deserialiser) are commonly used to achieve high speed data transfer for chip-to-chip, board-to-board applications and even within a chip. SerDes run at speeds of several hundred Mega-bits per second (Mb/s) to Giga-bits per second (Gb/s) . Typically, interconnections are implemented using analog based technology and, in order to avoid the use of a plurality of parallel connections between devices, a single differential analogue path is used running at a high data rate.

One exemplary arrangement is specified by IEEE 802.3/AE/P.

Certain serdes may incorporate a feed forward eguaiiser in addition to the more common decision feedback egualiser often used as a data slicer. The purpose of a feed forward equalizer is to remove the effect of the future data sample from a current data sample. Ordinarily a guantized feed forward equaliser (FFE) will apply a correction to the data sample when the future sample is above or below a threshold representing a slicing level of the FFE.

In a typical ADO-based SerDes configuration, the differential signal from a transmitter arrives at an Analogue-Digital converter (ADO) in a receiver and the signal amplitude is sampled once per symbol. The samples are processed to determine whether the differential signal is positive or negative, and to extract sufficient timing informaticn in order tc determine if the sample pcint is optimised. In an exemplary realisation of the ADO, the sample itself can have 14 different values which are all equally spaced representations of the signal amplitude, centred on zero but not containing zero (since there is no representation for the differential signal being zero) . The ADO has thirteen levels (for 14 possible sample values) as follows: -6.5, -5.5, -4.5, -3.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +3.5, +4.5, +5.5, and +6.5.

In accordance with the prior art, the ADO output values are represented in Table 1 below as two's complement 4 bit codes, with an implicit 0.5 bit offset The left hand bit for each value is the sign bit; a 1 represents a negative sample value, while a 0 represents a positive sample value. The remaining three bits are a standard binary weighted code representing the magnitude of the sample.

Sample Value 1110 -6.5 1101 -5.5 1100 -4.5 1011 -3.5 1010 -2.5 1001 -1.5 1000 -0.5 0000 +0.5 0001 +1.5 +2.5 0011 +3.5 +4.5 0101 +5.5 +6.5

Table 1

In the above sign magnitude binary (i.e., 4-bit code) implementation, processing a series of samples (1(0), 1(1), 1(2) 1(n), Y(n-I-l) ) from the ADC typically involves a limited set of arithmetic operations, namely, increment, decrement and magnitude compare. As illustrated in the flow diagram of Figure 1, the FFE operation on a sample 1(n) involves comparing the magnitude of the next consecutive sample Y(n +1) to a first threshold thl, conditionally incrementing or decrementing 1(n) to produce an adjusted value (Yadjust(n)) bearing the feedforward correction and comparing the adjusted value to a second threshold value (th2) to determine whether symbol(n) is +1 or -1. Because Y(n+1) can have a positive or negative value, the first magnitude compare step potentially involves two comparison steps; a first comparison (100) to a positive threshold (+thl) followed by a seoond comparison (10l)to a negative threshold value (-thl) if the magnitude of sample value Y(n+1) is less than the positive threshold value (+th).

The selcted y(n) value is then forwarded to the data slicer for oomparison (102) with a second threshold, being for example the present slicing level of a DFE. This will decide the final symbol value here defined as +1 or -1.

An example of a circuit realization of the above implementation is shown in Figure 2. The oircuit oomprises a sign magnitude to Us complement stage (20) (In order to simplify the computation), an incrementer stage (22), a decrementer stage (24) a magnitude compare stage (26) and multiplexing stage (28) and a re-conversion to sign magnitude format stage (30) . As can be seen, this realization is complex involving many components with considerable logic path depth which in turn adversely affects the speed of the circuit. For example, the circuit realisation a magnitude compare operation has a maximum logic path of five, while each of the magnitude increment and decrement operations has a logic depth of two.

Many ADOs output values as a multi-bit thermometer code rather than binary code. The main advantage of the thermometer code is that it is monotone, i.e., between individual codes, there exists only a transition of one bit from one code state (e.g., zero) to the other code state (e.g., one). For example, given a three-bit binary code transition from 011 (decimal 3) to 100 (decimal 4) wherein the MSB bit transitions from zero to one arid the other bits transition from one to zero, the corresponding thermometer code transition will be 00000111 to 00001111. Since only one bit transitions from a zero to a one in the thermometer oode, less errors typically would 000ur in any output signal that the thermometer code may represent thus yielding an advantage in the thermometer code as compared with the binary code. However, in comparison to binary code, a thermometer code does not represent numbers efficiently in terms of the number of bits required. For instance, an 8-bit thermometer code can represent any one of 9 different numbers (including 0) while a typical 8-bit binary code can represent 256 different numbers. Therefore, the thermometer code output of an A/D converter is usually converted by an encoding circuit to a more compact and useful binary code before further processing of sample values or before being transmitted as data to external circuits. However it has been found that the logic required to recode the magnitude portion of the thermometer code output can introduce significant delay into the signal processing due to the use of multiple registers to store output values prior to conversion. In high speed SerDes applications, any such further delays in signal processing are undesirable.

As data rate requirements increase still further, there is a need to provide improved techniques for processing sample values that can be implemented with simple logic with minimal delay.

Examples of the invention will now be described with reference to the accompanying drawings, of which: Figure 1 is a flow diagram of a conventional algorithm comprising a set of operations performed on a sample value output from an analog to digital converter (ADC) Figure 2 is a diagram of a circuit realisation of the algorithm illustrated in the flow diagram of Figure 1; Figure 3 is a block diagram of a circuit realisation of a magnitude compare operation in accordance with the present invention; Figure 4 is a blook diagram of a cirouit realisation of a magnitude increment and decrement operation in accordance with the present invention; Figure 5 is a diagram of a circuit realisation of the algorithm illustrated in the flow diagram of Figure 1 and in accordance with the present invention; Figure 6 is a block diagram of a receiver circuit, in which the invention may be used; and Figure 7 shows an exemplary FFE/DFE.

The present invention provides apparatus and method as set forth in the claims.

Tn particular, the present invention, in one aspect thereof, provides a method of processing data comprising receiving a series of data samples (Y(l) Y(2) Y(n), Y(n+l)), each sample being represented as an N-bit thermometer code, wherein the most significant bit thereof represents the sign of the data sample value Y(n) and the remaining N-i bits represent the magnitude of the data sample; and executing a predetermined seguence of arithmetic operations directly on the series of N-bit thermometer code data samples to determine one of two values for each data sample, without any recoding of the thermometer code data samples.

Advantageously in some applications step of executing a predetermined sequence of arithmetic operations comprises for each data sample 1(n), comparing the magnitude of the next consecutive data sample Y(n +1) in the series of data samples to a first threshold (thi); if the magnitude of Y(n+1) is less than the first threshold (thi), setting an adjusted value (Yadjust (n)) of data sample 1(n) to the value of data sample Y(n) ; if the magnitude of data sample Y (n+1) is not less than the threshold (thi), determining the sign of the data sample Y(n+1) from the F453 of 1(n+i); inorementing or deorementing the value of Y(n) in dependence on the sign of the data sample Y(n+1); comparing the magnitude of the adjusted value of Y(n) (Yadjust (n)) to a second threshold value (th2); determining one of two values for data sample Y(n) on the basis of the comparison with the second threshold value (th2) The threshold may be specified as a binary code.

Further advantage ensues in some applications where a comparing step comprises providing a plurality of two input multiplexers arranged in cascaded stages, there being one stage for each bit of said binary code and each multiplexer in a stage receiving a respective bit at its select input in order of bit significance; each multiplexer of a first stage receiving a pair of thermometer code bits of consecutive significance, excepting the multiplexer which receives the bit of least significance which also receives a permanently high bit value and likewise excepting the multiplexer which receives the bit of greatest significance which also receives a permanently low bit value, each multiplexer of said stage providing its selected output; and each multiplexer of a next stage receiving a pair of outputs from a previous stage; wherein the outputs of said first stage of multiplexers are selected by the binary code bit of least significance and wherein the outputs of said next stage of multiplexers are selected by the binary code bit of next significance, the output of a final stage of said multiplexers being by the binary code bit of greatest significance to produce an output representative of said comparison.

vantage ensues in some applications where the step of incrementing or decrementing the value of Y(n) in dependence on the sign of the data sample Y(n+1 comprises; decrementing the value of Y(n) to provide an adjusted value (Yadjust (n)) of data sample 1(n) if the MSB of Y(n+l) has a positive value; or incrementing the value of Y(n) to provide an adjusted value (I adjust (n)) of data sample 1(n), if the MSB of I(n+l) has a negative value.

Moreover, a step of incrementing or decerementing may comprise providing a plurality of multiplexers receiving bits of said thermometer code, each multiptexer receiving a first bit of a certain significance at a first input; a seoond bit of two greater significance than said certain signifioance at a second input; and providing a select input to each multiplexer to provide an increment if said first input of each multiplexer is selected by said select input and a decrement if said second input of each multiplexer is selected by said select input.

Furthermore, a multiplexer may receive a permanently high value at its first input and a thermometer code bit of next to least signifioance at its second input. Yet further, a multiplexer may receive a permanently low value at its second input and a thermometer code bit of next to greatest significance at its second input.

To yet further advantage in some applications the step of determining one of two values for data sample 1(n) on the basis of the comparison with the second threshold value (th2) may comprise determining that data sample 1(n) has a value of +1, if the magnitude of the adjusted value of 1(n) (I adjust (n)) is greater than the second threshold (th2); or determining that data sample 1(n) has a value of -1, if the magnitude of the adjusted value of 1(n) (1 adjust (n)) is not greater than the second threshold (th2) . The N-bit thermometer code may be a 7-bit code.

The present invention in another aspect thereof provides a magnitude comparator for comparing a value represented by a thermometer code with a value represented by a binary code including a plurality of two input multiplexers arranged in cascaded stages, there being one stage for each bit of said binary code and each multiplexer in a stage receiving a respective bit at its select input in order of bit signifioance; each multiplexer of a first stage receiving a pair of thermometer code bits of consecutive significance, excepting the multiplexer which receives the bit of least significance which also receives a permanently high bit value and likewise excepting the multiplexer which receives the bit of greatest significance which also receives a permanently low bit value, each multiplexer of said stage providing its selected output; and each multiplexer of a next stage receiving a pair of outputs from a previous stage; wherein the outputs of said first stage of multiplexers are selected by the binary code bit of least significance and wherein the outputs of said next stage of multiplexers are selected by the binary code bit of next significance, the output of a final stage of said multiplexers being by the binary code bit of greatest significance to produce an output representative of said comparison.

Moreover in a further aspect of the present invention a method for comparing a value represented by a thermometer code with a value represented by a binary code includes the steps of providing a plurality of two input multiplexers arranged in cascaded stages, there being one stage for each bit of said binary code and each multiplexer in a stage receiving a respective bit at its select input in order of bit significance; each multiplexer of a first stage receiving a pair of thermometer code bits of consecutive significance, excepting the multiplexer which receives the bit of least significance which also receives a permanently high bit value and likewise excepting the multiplexer which receives the bit of greatest significance which also receives a permanently low bit value, each multiplexer of said stage providing its selected output; and each multiplexer of a next stage receiving a pair of outputs from a previous stage; wherein the outputs of said first stage of multiplexers are selected by the binary code bit of least significance and wherein the outputs of said next stage of multiplexers are selected by the binary code bit of next significance, the output of a final stage of said multiplexers being by the binary code bit of greatest significance to produce an output representative of said comparison.

In a yet further aspect thereof, the present invention provides an incrementer/decrementer for a thermometer code including a plurality of multiplexers receiving bits of said thermometer code, each multiplexer of said incrementer/decrementer receiving a first bit of a certain significance at a first input; a second bit of two greater significance than said certain significance at a second input; and a select input, the incrementer/deorementer providing an increment if said first input of each multiplexer is selected by said select input and a decrement if said second input of each multiplexer is selected by said select input.

Advantageously, the inorementer/decrementer includes a multiplexer receiving a permanently high value at its first input and a thermometer code bit of next to least significance at its second input. :0 advantage the incrementer/decrementer includes a multiplexer receiving a permanently low value at its second input and a thermometer code bit of next to greatest significance at its second input.

The present invention in yet another aspect thereof provides a method of incrementing/decrementing a thermometer code includes providing a plurality of multiplexers receiving bits of said thermomener code, each multiplexer receiving a first bit of a certain significance at a first input; a second bit of two greater significance than said certain significance at a second input; and providing a select input to each multiplexer to provide an increment if said first input of each ii multiplexer is selected by said select input and a decrement if said second input of each multiplexer is selected by said select input. Advantageously, a multiplexer receives a permanently high value at its first input and a thermometer code bit of next to least significance at its second input and to advantage a multiplexer receives a permanently low value at its second input and a thermometer code bit of next to greatest significance at its second input.

In the algorithm underlying the present invention, the ADO output values are represented as a 7-bit thermometer code, rather than the sign magnitude 4 bit code described above. As explained above, thermometer code output of an ADO is generally converted to a more compact code before any processing of the data occurs. The present invention eliminates any reguirement for conversion from thermometer code, instead performing arithmetic functions directly between sign thermometer code data and sign binary code data. Hence, the logic reguired to recode the output values and the conseguential delays are eliminated. Furthermore, the logic required to implement the thermometer code arithmetic operations is very simple and involves substantially shorter logic paths than that used to implement the binary sign magnitude operations described above.

As in the prior art described above, the ADO has thirteen levels (for 14 possible sample values) centred around, but not including, zero. The ADO output sample values are represented as a 7-bit thermometer code as set out in Table 2 below. Again the F4SB represents the sign of the sample value, "1" for a negative value and "0" for a positive value, while the remaining 6 bits are a thermometer coded representation of the magnitude of the sample value.

ADO Output Sample Value 1111111 -6.5 1011111 -5.5 1001111 -4.5 1000111 -3.5 1000011 -2.5 1000001 -1.5 1000000 -0.5 0000000 +0.5 0000001 +1.5 0000011 +2.5 0000111 +3.5 0001111 +4.5 0011111 +5.5 0111111 +6.5

Table 2

However as stated above, the algorithm of present invention advantageously performs arithmetic operations directly on the thermometer code output of the ADC rather than recoding to binary data. The flow diagram of Figure 1 would be equally applicable to the present invention since the underlying algorithm is not changed, however as will be appreciated the implementation thereof has been simplified and made more efficient by direct processing of the thermometer code without any recodiflg.

The operation of the exemplary embodiment will now be described in the context of operation on a sample value Y(n) As in he prior art, the operation on Y(n) involves comparing the magnitude of the next consecutive sample Y(n +1) to a first threshold thl. Tf the magnitude of Y(n+1) is less than the threshold (thi), the adjusted value Yadjust (n) is taken as the sample value Y(n) and the process proceeds to the second magnitude compare step. If the magnitude of Y(n+1) is not less than the threshold (thi), the sign bit of Y(n+1) is examined to determine whether on not Y(n+1) has a positive value (i.e. the :13 MSB is 0). If Y(n+l) is determined to be positive, the value of 1(n) is decremented to produce the adjusted value I adjust (n) and the process proceeds to the second magnitude compare step.

Tf Y(n-l) is not positive (i.e., F4SB is 1), then the value of 1(n) is incremented to produce the adjusted value I adjust (n) and the process proceeds to the second magnitude compare step.

The second magnitude compare (data slicing) is equivalent to that shown in the flow chart of Figure 1, with the magnitude of the adjusted value I adjust (n) being ccmpared tc a second threshold in order to determine whether the symbol (n) is +1 or -1. In this instance, the use of the sign magnitude numbers to determine whether the sample is positive or negative simplifies the first magnitude compare step in that a single comparison step only is ever required. If the sample is above the positive threshold (i.e., the magnitude of 1(n-J) is not less than thl and Y(n+l) is positive), a first action is taken (i.e., 1(n) is decremented) . If the sample is below the negative threshold (i.e., the magnitude of Y(n-I-l) is not less than thi and Y(n-I-l) is not positive), a second action is taken (i.e., 1(n) is incremented. If the sample is neither above the positive threshold or below the negative threshold (i.e., the magnitude of Y(n-l) is less than thi), a third action is taken (i.e., no increment or decrement is made and 1(n) is taken as the adjusted value Iadjust(n)) An example of a circuit realization of the magnitude compare operation used in the above algorithm and in accordance with the present invention is shown in Figure 3 comprising a series of 2:1 multiplexers as the functional elements. The threshold values thl and th2 are 3-bit binary codes and the operand is the 7-bit thermometer code output from the ADO. As shown in Figure 3, the 6 LSB bits of the thermometer code (i.e., the bits representing the magnitude of the sample) are input to a first series of four 2:1 MtJXs 302-305, while the first (LSB) bit of the binary code threshold (THO) serves as the control input. The second bit of the threshold code (TEll) is the control input to a second series of two Muxes 310 and 311, the inputs of which are the respective outputs of the first series cf MUXS 302-305 while the third (MSB) of the binary threshold code (TH3) is the control input to MUX 314 which receives the respective outputs of the second series of MUXes 310 and 311 at its input.

The circuit operates as follows. If the threshold (th) has a value 000 (i.e., decimal 0), then ElI input of MUX 305 is selected as all sample magnitudes are greater than zero. If the threshold code (th) is 010 (i.e., decimal 2), then bit 2 of the 7-bit thermometer code is set by setting the first input of MUX 304. As can be seen from Table 2, this bit is set for all samples having a magnitude of 2.5 or more. Similarly, if the threshold code (th) is 011 (i.e., decimal 3), then bit 3 of the 7-bit thermometer code is set by setting the second input of MUX 304. Again, as can be seen from Table 2, this bit is set for all samples having a magnitude of 3.5 or more. Finally, if the threshold code (th) is ill (decimal 7), then the tO input of MUX 402 is set as no sample will have a value greater than 7. In this way, advantageously only those bits of the 7-bit thermometer code sample that require examination in order to determine the magnitude compare are selected depending on the value of the threshold. In other embodiments, particularly if the code length were longer, it may be advantageous to group the bits and perform a corresponding selection of a group. That group could then be subject to further bit or group selection in a cascaded structure.

Since the magnitude compare function is configured entirely using basic 2:1 MUXs, the circuit is very cost effective to realise. In addition, since a 2:1 MUX oan be regarded having a single gate delay, the delay through the magnitude compare circiit is just three gates which compares very favourably with the corresponding oircuit of Figure 2 which has a maximum logic depth of five.

The other types of operation used in the algorithm underlying the present invention are magnitude increment and decrement. These functions can also be accomplished directly on the thermometer code output of the ADO and realised with simple circuit elements. A magnitude increment corresponds to shifting the code to the left, with a 1' being shifted in from the right. A decrement corresponds to shifting the code to the right, with a 0' being shifted in from the left.

An example of a circuit that can produce a magnitude increment or decrement directly on the thermometer code output of the ADO is shown in Figure 4, again comprising a series of six 2:1 multiplexers 402-412 as the functional elements. There is only one instance of this circuit required in the serdes, since it functions either to increment or to decrement and which is performed may be determined by the sign bit of the thermometer code; the result of the threshold comparison may control a further MUX to select between the incremented/decremented value of Y(n) and the unmodified value.

If the thermometer code is 0000000, selecting the HI input of MUX 412 will produce a magnitude increment at its output, a magnitude decrement from this value not being possible. For thermometer code 1000000, selecting the HI input of MLIX 412 will produce a magnitude decrement, a magnitude increment not being possible. For thermometer code 0000011, selecting bit 2 of MLIX 408 will produce a magnitude increment, while selecting bit 4 of MUX 408 will produce a magnitude decrement. The same MUX selections are used for a thermometer code 1000011, selecting bit 2 of F4UX 408 will produce a magnitude decrement while selecting bit 4 of MUX 408 will produce a magnitude increment. For a thermometer code of 0111111 or 1111111, selecting the LED input of Mlix 612 produces a respective decrement and increment, an increment from 0111111 not being possible and a decrement from 1111111 not being possible. As with the circuit of Figure 3, the only components are basic 2:1 Muxs and so each of a magnitude increment and decrement can be achieved with a single gate delay. The full listing of the output of the circuit of Figure 3 is set out in table 3 below.

Thermometer Code Select Increment Select Decrement (left) (right) 000000 000001 000000 000001 000011 000000 000011 000111 000001 000111 001111 000011 001111 011111 000111 011111 111111 001111 111111 111111 011111

Table 3

Figure 5 shows how the thermometer code magnitude compare arrangement of Figure 3 and the thermometer code increment/decrement arrangement of Figure 4 may be deployed to implement the algorithm of Figure 1.

A thermometer code incrementer 501 (as described with reference to Figure 4) increments the present sample value and a thermometer code decrementer 502 (also as described with reference to Figure 4) decrements the present sample value which is selected as a modified value for onward transmission by multiplexer (MUX 503 depends upon the sign bit 504 of the sample. As mentioned above, since the increment/decrement circuitry for the thermometer code is the same, in some embodiments a single instance may be with increment or decrement directly selected. Next, a thermometer code magnitude compare block (505) (as described with reference to Figure 3) compares a next sample value with the first threshold and the output selects either the modified or unmodified value of the current sample dependent upon the outcome via MUX 506. Finally a second thermometer code magnitude compare block (507) (also as described with reference to Figure 3) compares the selected adjusted current sample value with the second threshold to provide the symbol output.

The present invention is useful in a SerDes circuit and indeed was developed for that application. Nonetheless, it should be understood that the invention may be used in other applications. A block diagram of a SerDes receiver circuit 1, which forms part of an integrated circuit, in which the present invention may be used is shown in Figure 6. The invention may nonetheless be used in other applications.

In the receiver circuit 1 of Figure 6 the input data is sampled at the baud-rate, digitized and the equalization and clock & data recovery (CUR) performed using numerical digital processing techniques. This approach results in the superior power/area scaling with process of digital circuitry compared to that of analogue, simplifies production testing, allows straightforward integration of a feed-forward egualizer and provides a flexible design with a configurable number of filter taps in the decision feedback equaliser. The circuit has been implemented in 65nm CMOS, operating at a rate of 12.5Gb/s.

The receiver circuit 1 comprises two baud-rate sampling ADDs (analogue to digital converters) 2 and 3, a digital 2-tap FIT (feed forward egualiser) 4 and digital 5-tap DFE (decision feedback equaliser) 5 to correct channel impairments.

The SerDes section of the integrated circuit, which includes the receiver circuit 1 is also provided with a transmitter, connected to transmit data over a parallel channel to that which the receiver circuit 1 is connected to receive data. The transmitter may comprise a 4-tap FIR filter to pre-compensate for channel impairments. In many applications the integrated circuit transmitting data to the receiver circuit 1 uses pre-compensation but in other applications the receiver circuit 1 works without pre-compensation being used at the other end.

The receiver 1 cf Figure 6 is now described in more detail. The received data is digitized at the baud-rate, typically 1.0 to 12.5 Gb/s. using a pair of interleaved track and hold stages (T/H) 6 and 7 and a respective pair of 23 level (4.5 bit) full-flash ADOs 2 and 3 (i.e. they sample and convert alternate bits of the received analogue data waveform) . The two track & hold circuits enable interleaving of the half-rate ADCs and reduce signal related aperture timing errors. The two ADOs, each running at 6.25 Gb/s for 12.5 Gb/s incoming data rate provide baud-rate quantization of the received data. The ADO's dynamic range is normalized to the full input amplitude using a 7-bit automatic gain control (AGO) circuit 8. A loss of signal indication is provided by loss of signal unit 9 that detects when the gain control signal provided by the AGO is out-of-range. An optional attenuator is included in the termination block 10, which receives the signals from the transmission channel, to enable reception of large signals whilst minimizing signal overload.

The digital samples output from the ADOs 2 and 3 are interleaved and the resulting stream of samples is fed into a :19 custom digital signal processing (DSP) data-path that performs the numerical feed-forward equalization and decision-feedback equalization.

An advantage of applying the egualization digitally is that it is straightforward to include feed-forward equalization as a delay-and-add function without any noise-sensitive analogue delay elements. The FFE tap weight is selected before use to compensate for pre-cursor 151 and can be bypassed to reduce latency. Whilst many standards require pre-cursor de-emphasis at the transmitter, inclusion at the receiver allows improved bit error rate (BER) performance with existing legacy transmitters.

The exemplary prior art FFE is shown in Fig.7. The FFE serves to make an estimate of the future data bit value based up a selected slicing level, such as by assessing the sign of the raw ado sample; a positive sample is assumed to be a 1 and a negative sample a 0.

The DFE 5 uses au unrolled non-linear cancellation method ["Techniques for High-Speed implementation of Non-linear cancellation" S.Kasturia IEEE Journal on selected areas in Communications. June 1991] . The data output (i.e. the ls aud Os originally transmitted) is the result of a magnitude comparison between the output of the FFE and a slicer-level dynamically selected from a set stored in a set of pre-programmed registers. The values are determined by a control circuit (not shown in Figure 1) from the waveforms of test patterns sent during a setup phase of operation. The magnitude comparison is performed by a magnitude comparator 18 connected to receive the output of the FFE 4 and the selected slicer-level; it outputs a 1 if the former is higher than the latter and a 0 if it is lower or equal, thereby forming the output of the DFE 5.

The slicer-level is selected from one of 2n possible options depending on the previous n bits of data history. The history of the bits produced by the magnitude comparator 18 is recorded by a shift register 19 which is connected to shift them in. The parallel output of the shift register is connected to the select input of a multiplexer 20 whose data inputs are connected to the outputs of respective ones of the set 17 of registers holding the possible slicer-levels.

Unrolled tap adaption is performed using a least mean square (LMS) method where the optimum slicing level is defined to be the average of the two possible symbol amplitudes (-Fl-i) when proceeded by identical history bits. (For symmetry the symbols on the channel for the bit values 1 and 0 are given the values +1 and -1) Although 5-taps of DPE were chosen for this implementation, this parameter is easily scaleabie and performance can be traded-off against power consumption and die area. In addition, the digital equalizer is testable using standard ATPG (automatic test pattern generation) and circular built-in-self-test approaches.

Although in the embodiments described above, the ADO has thirteen levels and the ADO output sample values are represented as a 7-bit thermometer code, it should be understood that any other appropriate number of levels and corresponding thermometer bit codes may be used in dependence on the application requirements in a particular instance.

Further, although the present invention has been described in the context of ADOs used in a SerDes receiver, it should be understood that the present invention may be used with any ADO in applications involving simple arithmetic operations such as those described above.