GB2499615A - Waveform generation - Google Patents
Waveform generation Download PDFInfo
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- GB2499615A GB2499615A GB1203038.3A GB201203038A GB2499615A GB 2499615 A GB2499615 A GB 2499615A GB 201203038 A GB201203038 A GB 201203038A GB 2499615 A GB2499615 A GB 2499615A
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- frequency clock
- waveform
- state
- higher frequency
- time period
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- 230000007704 transition Effects 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims description 33
- 239000013078 crystal Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Abstract
A predetermined waveform is generated using a lower frequency clock signal (16) and a higher frequency clock signal (18). The waveform transitions between first and second states (12,14) in synchrony with timing signals (18-1 to 18-Â11) of the higher frequency clock signal (18). The higher frequency clock is operated if the waveform will transition between the first and second states (12, 14) before the next timing signal (16-2) of the lower frequency clock. The higher frequency clock is powered down if the waveform will not transition between the first and second states (12, 14) before the next timing signal (16-3) of the lower frequency clock. The predetermined waveform can thus be generated having higher resolution but with lower power consumption. A state-change count is set at the beginning of the first state (12) and reduced by one for each high clock timing signal. On the low clock timing signal a power-save count is implemented. At a synchronisation point (16-2) the counts are compared with the result determining if higher speed clock is powered down.
Description
-1 -
Waveform Generation
The present invention relates to a method of generating a predetermined waveform and a device for generating a predetermined waveform.
5 Waveforms such as digital signals or pulse wide modulation (PWM) signals can be used to transmit data or to provide control signals to electrical components. In some devices, a waveform can be generated by transitioning a signal, such as a voltage level, between states in synchrony with the timing signals of a clock for the device (e.g. in synchrony with timing signals provided by a crystal oscillator of the 10 device).
In such devices, the time complexity or resolution of the generated waveform is dependent on the length of time between timing signals of the clock. A higher frequency clock (having shorter time periods between its timing signals) is able to provide a more time complex or higher resolution waveform than a lower 15 frequency clock (having longer time periods between its timing signals). Thus, in situations where greater time complexity or higher resolution are desired, higher frequency clocks are generally desirable.
However, the Applicants have identified that devices which use higher frequency clocks may consume greater amounts of power than devices which use 20 lower frequency clocks. This greater power consumption can, for example, be due to the fact that device operations which occur on each timing signal of the clock occur more frequently with higher frequency clocks than with a lower frequency clocks. Thus, in situations where lower power consumption is desired, lower frequency clocks are generally desirable.
25 The Applicants have accordingly identified that traditionally there was a balance to be struck between using higher frequency clocks to generate waveforms having greater time complexity and higher resolution and using lower frequency clocks for lower device power consumption.
It would, however, be desirable to provide a way in which to generate 30 waveforms having greater time complexity and higher resolution without correspondingly increasing device power consumption.
The Applicants therefore believe that there remains scope for improvements in the way that waveforms are generated.
According to an aspect of the present invention there is provided a method 35 of generating a predetermined waveform using a higher frequency clock and a
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lower frequency clock, the waveform transitioning between first and second states in synchrony with timing signals of the higher frequency clock, the method comprising:
operating the higher frequency clock if the waveform will transition between 5 said states before the next timing signal of the lower frequency clock; and powering down the higher frequency clock if the waveform will not transition between said states before the next timing signal of the lower frequency clock.
This aspect of the invention extends to a device for generating a predetermined waveform using a higher frequency clock and a lower frequency 10 clock, the device being configured to transition the waveform between first and second states in synchrony with timing signals of the higher frequency clock, the device further being configured to:
operate the higher frequency clock if the waveform will transition between said states before the next timing signal of the lower frequency clock; and 15 power down the higher frequency clock if the waveform will not transition between said states before the next timing signal of the lower frequency clock.
The Applicants have accordingly identified a way in which to generate a predetermined waveform having greater time complexity and higher resolution but with reduced power consumption. In particular, by operating a higher frequency 20 clock if the waveform will transition between the states before the next timing signal of a lower frequency clock, the predetermined waveform can be generated having a time complexity and resolution that is based on the higher frequency clock.
However, by powering down the higher frequency clock if the waveform will not transition between the states before the next timing signal of a lower frequency 25 clock, the predetermined waveform can be generated with reduced power consumption.
In one set of embodiments, the generated waveform forms part of a digital signal, wherein the first state comprises a first digital level (e.g. a "high" digital level) 30 and the second state comprises a second digital level (e.g. a "low" digital level).
According to another aspect of the present invention there is provided a method of generating a predetermined waveform using a higher frequency clock and a lower frequency clock, the waveform transitioning between first and second states in synchrony with timing signals of the higher frequency clock, the method 35 comprising:
-3-
operating the higher frequency clock if the waveform is in said first state;
and powering down the higher frequency clock if the waveform will not transition from the second state to the first state before the next timing signal of the lower 5 frequency clock.
This aspect of the invention extends to a device for generating a predetermined waveform using a higher frequency clock and a lower frequency clock, the device being configured to transition the waveform between first and second states in synchrony with timing signals of the higher frequency clock, the 10 device further being configured to:
operate the higher frequency clock if the waveform is in said first state; and power down the higher frequency clock if the waveform will not transition from said second state to said first state before the next timing signal of the lower frequency clock.
15 As discussed above, the Applicants have identified a way in which to generate a predetermined waveform having greater time complexity and higher resolution but with reduced power consumption. Furthermore, in the above aspects, by operating the higher frequency clock if the waveform is in the first state, the higher frequency clock can be used to maintain the waveform in the first state. 20 In a set of embodiments the waveform comprises a pulse width modulation
(PWM) signal, wherein the first state comprises the PWM signal being active (e.g. alternating between "low" and "high" digital levels) and the second state comprises the PWM signal being inactive (e.g. being fixed at a "low" or "high" digital level). The PWM signal, when active, may have any suitable frequency f but in a set of 25 embodiments f is in the range 490 Hz - 516 kHz. This range of frequencies may be used, for example, for motor (e.g. AC motor) control, lighting (e.g. LED) control and audio signals.
In embodiments of either aspect of the present invention, the waveform may be in the first state for a first time period (tp1), with the first time period being defined 30 in the device that generates the waveform by an integer number of timing signals of the higher frequency clock. For example, if the timing signals of the higher frequency clock are at 50 ms intervals and tpi is 0.5 seconds, then the first time period may be defined in the device by the number 10. Similarly, the waveform may be in the second state for a second time period (tp2), with the second time period 35 being defined in the device that generates the waveform by an integer number of
-4-
timing signals of the higher frequency clock. For example, if the timing signals of the higher frequency clock are at 50 ms intervals and tp2 is 1 second, then the second time period may be defined in the device by the number 20. As will be appreciated, tpi and tp2 may be the same value or may be different values. These embodiments 5 provide a simple but effective way to define the waveform.
In embodiments of the present invention, the first time period (tp1) and second time period (tp2) may also be equal in time to an integer number of timing signals of the lower frequency clock. This increases the likelihood of waveform state transitions being aligned with timing signals of the lower frequency clock. 10 In embodiments of the present invention, the waveform may be repeated a first number (np) of times so as to generate a train of pulses. Individual pulses or pulse trains may be repeated a second number (nt) of times to generate a series of pulses or pulse trains. The start of the respective pulses or pulse trains may be separated by a third time period (tt), with the third time period being defined in the 15 device that generates the waveform by an integer number of timing signals of the higher frequency clock. For example, if the timing signals of the higher frequency clock are at 50 ms intervals and t, is 5 seconds, then the third time period may be defined in the device by the number 100. These embodiments again provide a simple but effective way to define a signal comprising the waveform. 20 In embodiments of the present invention, the third time period (tp3) may also be equal to an integer number of timing signals of the lower frequency clock. This again increases the likelihood of waveform state transitions being aligned with timing signals of the lower frequency clock.
In embodiments of the present invention, any or all of the parameters f, tpi, 25 tp2, np, n, and t, may be predetermined, and may be stored in or provided to the device that generates the waveform. The parameters may be provided to the device by an external host and may be reconfigurable either by the device that generates the waveform or by the external host. This allows for the waveform to be modified from time to time to provide various signals.
30 In embodiments of the present invention, the higher frequency clock may have a time period (th) between timing signals that is in the range 25-100 ms. For example, as discussed above, th may be 50 ms. The lower frequency clock may have a time period (t,) between timing signals that is in the range 0.5-2 seconds. For example, t, may be 1 second.
- 5-
In embodiments of the present invention, the higher frequency clock may have a time period (th) between timing signals and the lower frequency clock may have a time period (t,) between timing signals, where t, /th gives an integer value. This increases the likelihood of each timing signal of the lower frequency clock 5 being aligned with a timing signal of the higher frequency clock.
In embodiments of the present invention, the higher frequency clock may have a lower relative and/or absolute timing signal precision and the lower frequency clock may have a higher relative and/or absolute timing signal precision. The higher precision of the lower frequency clock may help to compensate for any 10 discrepancies (e.g. drift) between the timing signals of the higher and lower frequency clocks. Furthermore, the higher precision of the lower frequency clock (which may, for example, be provided externally to the device that generates the waveform), allows the higher frequency clock (which may, for example, be provided by a component that forms part of the device that generates the waveform) to be 15 provide by a lower cost, lower power or less precise component.
The timing signals of the higher and lower frequency clocks may be provided in any desired and suitable way. In some embodiments, the higher frequency clock may be provided within the device that generates the waveform. For example, the higher frequency clock may be provided by a crystal oscillator for 20 the device (e.g. that forms part of the device), by a synthesised clock source for the device (e.g. that forms part of the device) that synthesises the higher frequency clock from a crystal oscillator, or by an RC oscillator for the device (e.g. that forms part of the device). In some embodiments, the timing signals of the lower frequency clock may be provided externally to the device that generates the waveform. For 25 example, the higher frequency clock may be provided by a radio interval. By powering down the higher frequency clock which forms part of the device, and by relying on a lower frequency clock which does not form part of the device, the device itself may consume less power.
In embodiments of the present invention, a state-change count may be 30 associated with the waveform. The state-change count provides an indication of when to transition between states. For example, when the higher frequency clock is operated, the state-change count may be decremented on each timing signal of the higher frequency clock. When the state-change count reaches a predetermined minimum, the waveform may be made to transition between the first and second 35 states.
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In embodiments of the present invention, the state-change count may be set to a first number (np1) when transitioning the waveform to the first state, where np1 = tp1/th, and where th is the time period between timing signals of the higher frequency clock. For example, if the timing signals of the higher frequency clock are at 50 ms 5 intervals and tp1 is 0.5 seconds, then np1 may be 10. Similarly, the state-change count may be set to a second number (np2) when transitioning the waveform to the second state where np2 = tp2/th. For example, if the timing signals of the higher frequency clock are at 50 ms intervals and tp2 is 1 second, then np1 may be 20.
A power-save count may also be associated with the waveform. The power-10 save count provides an indication of when the next timing signal of the lower frequency clock will occur. For example, when the higher frequency clock is operated, the power-save count may be decremented on each timing signal of the higher frequency clock. However, when the higher frequency clock is powered down, in order for the state-change count to provide an indication of when to 15 transition between states, the state-change count may be reduced by the power-save count.
In embodiments of the present invention, the power-save count may be set to an integer (nps) on each timing signal of the lower frequency clock, where nps = t, / th, or (when nps = t, /th does not give an integer value) nps = floor(t, /th), and where t, 20 is the time period between timing signals of the lower frequency clock. For example, if the timing signals of the higher frequency clock are at 50 ms intervals and the timing signals of the lower frequency clock are at 1 second intervals, then npsmay be 20.
In embodiments of the present invention, whether or not the waveform will 25 transition between the first state and the second state before the next timing signal of the lower frequency clock may be determined from the state change count and the power-save count. For example, if the state-change count is greater than or equal to the power-save count then it may be determined that the waveform will not transition between the first state and the second state before the next timing signal 30 of the lower frequency clock. Similarly, if the state-change count is less than the power-save count then it may be determined that the waveform will transition between the first state and the second state before the next timing signal of the lower frequency clock.
In embodiments of the present invention, the higher frequency clock may be 35 re-synchronised with the lower frequency clock. This re-synchronisation may
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happen, for example, on the next timing signal of the lower frequency clock that occurs once the higher frequency clock is powered down and then is operated again. This can, for example, remove any drift in the higher frequency clock and allow waveform state transitions to occur in synchrony with timing signals of the 5 lower frequency clock.
In embodiments of the present invention, when the waveform is initially generated, the device may be made to wait at least until the next timing signal of the lower frequency clock before being able to power down the high frequency clock. This can, for example, allow the relative temporal positions of the waveform 10 state transitions and lower frequency clock timing signals to be determined before the high frequency clock may be powered down.
In embodiments of the present invention, if the higher frequency clock has previously been powered down and then is operated again, the device may be made to wait at least until the next timing signal of the lower frequency clock before 15 initially generating the waveform. This can, for example, allow the higher and lower frequency clocks and the waveform state transitions to be synchronised when the waveform is initially generated.
As will be appreciated, the present invention has particular application to devices that would benefit from reduced power consumption such as battery or 20 solar powered devices, although the present invention could equally apply to non-battery and non-solar powered devices.
Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying figures in which:
Figure 1 shows a waveform generated in accordance with an embodiment 25 of the present invention;
Figure 2 shows the current drawn by a device that is used to generate the waveform of Figure 1;
Figure 3 shows a waveform generated in accordance with another embodiment of the present invention;
30 Figure 4 shows a waveform generated in accordance with another embodiment of the present invention;
Figure 5 shows a waveform generated in accordance with another embodiment of the present invention;
Figure 6 shows a waveform generated in accordance with another 35 embodiment of the present invention.
- 8-
Figure 1 shows a required waveform generated in accordance with an embodiment of the present invention. In this embodiment, the waveform forms part of a digital voltage signal 10 that is used to power an LED. The waveform has a first "high" state 12 and a second "low" state 14. The required waveform is in the first 5 state 12 for a first time period tp1 and in the second state 14 for a second time period tp2. In this embodiment, the predetermined waveform required has tp1 = 0.5 seconds and tp2= one second. The digital signal 10 causes the LED to flash on for 0.5 seconds and turn off for one second.
Figure 1 also shows a lower frequency clock signal 16 having timing signals 10 16-1 to 16-3. In this embodiment the lower frequency clock signal 16 runs at 1 Hz such that the leading edge of the timing signals 16-1 to 16-3 are spaced apart by one second. The time period between timing signals of the lower frequency clock shall be referred to herein as t|. In this embodiment, the lower frequency clock signal 16 is provided externally to the device that generates the waveform. For 15 example, the lower frequency clock signal 16 may be provided by a host device for the device that generates the waveform or by a radio interval.
Figure 1 also shows a higher frequency clock signal 18 having timing signals 18-1 to 18-11. In this embodiment the higher frequency clock signal 18 runs at 20 Hz such that the leading edge of the timing signals 18-1 to 18-11 are 20 generally spaced apart by 50 ms. However, the leading edges of timing signals 18-5 and 18-6 are spaced apart by slightly less than 50 ms since, as will be discussed in more detail below, timing signal 18-6 is re-synchronised with the timing signals of the lower frequency clock. The time period between timing signals of the higher frequency clock shall be referred to herein as th. In this embodiment, the higher 25 frequency clock signal 20 is provided from within the device that generates the waveform. For example, the higher frequency clock may be provided by a crystal oscillator. In this embodiment, the lower frequency clock has a higher absolute precision than the higher frequency clock.
In embodiments of the present invention, the waveform has associated with 30 it a power-save count which is reset on each timing signal of the lower frequency clock. The power-save count is reset to an integer nps on each timing signal of the lower frequency clock. In this embodiment, nps is given by:
flps = t| / th-
35
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In the present embodiment, nps is:
nps = 1 second / 50 ms = 20.
5 However, as will be appreciated, in embodiments in which t, / thdoes not give an integer value, the power-save count may be set to an integer nps, where:
nps = floor(ti / th).
10 In the present embodiment, the power-save count is decremented by a predetermined amount (in this case one) on each timing signal of the higher frequency clock. The power-save count therefore provides a running indication of when the next timing signal of the lower frequency clock is due to occur. As will be appreciated, in this embodiment, the time until the next timing signal of the lower 15 frequency clock can be taken to be:
power-save count x th.
For example, if the power-save count is currently '20' then the time until the next 20 timing signal of the lower frequency clock is assumed to be:
20 x 50 ms = 1 second.
The waveform also has associated with it a state-change count. As will be 25 discussed in more detail below, the state-change count is either decremented on the higher frequency clock signal by a predetermined amount (in this case one) or reduced on the lower frequency clock signal (when the higher frequency clock is not in operation). When the state-change count reaches a predetermined minimum (in this case zero), the waveform is made to transition between states. The state-30 change count thereby provides a running indication of when to transition between states.
The state-change count is reset each time the waveform changes state. When transitioning to the first state, the state-change count is set to a first number (np1). In this embodiment, np1 is given by:
35
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flpl — tp-l/ th-
In the present embodiment, np1 is:
5 np1 = 0.5 seconds / 50 ms = 10.
Similarly, when transitioning to the second state, the state-change count is set to a second number (np2). In this embodiment, np2 is given by:
10 np2 = tp2/ th.
In the present embodiment, np2 is:
np2 = 1 second / 50 ms = 20.
15
As will be appreciated, in this embodiment, the time until state transition from the first state can be taken to be:
state-change count x th.
20
For example, if the state-change count is currently 5 then the time until state transition is:
5 x 50 ms = 0.25 seconds.
25
By comparing the state-change count to the power-save count, a determination can be made as to whether or not the waveform will transition between the first state 12 and the second state 14 before the next timing signal of the lower frequency clock.
30 In particular, if the state-change count is less than the power-save count,
then the waveform will transition between states before the next timing signal of the lower frequency clock. In this situation, the higher frequency clock will imminently be needed to transition the waveform between states. In this situation, in order for the state-change count to provide an appropriate indication of exactly when to
35 transition between states, the state-change count may be decremented by the
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predetermined amount (in this case one) on each timing signal of the higher frequency clock.
However, if the state-change count is greater than or equal to the power-save count, then the waveform will not transition between states before the next 5 timing signal of the lower frequency clock. In this case, the higher frequency clock is not imminently needed to transition the waveform between states, and can be powered down at least until the next timing signal of the lower frequency clock. By powering down the higher frequency clock, the power consumption of the device that generates the waveform can be reduced.
10 When then the higher frequency clock is powered down, the state-change count is reduced, not by the predetermined amount (e.g. one), but by the power-save count on each timing signal of the lower frequency clock. In this way, the state-change count can still provide an appropriate indication of when to transition between states.
15 In order to give a better understanding of the above features, specific reference will now be made to the embodiment of Figure 1.
Generation of the predetermined waveform begins at t0. At this point in time, the waveform is placed in the first state 12 and the state-change count is 20 accordingly set to '10' for that state in order to give the 0.5 seconds of "high"
required at the beginning of the waveform. The higher frequency clock is operated at this point because there has not yet been a timing signal of the lower frequency clock during generation of the waveform.. The state-change count is then decremented by one on each subsequent timing signal of the higher frequency 25 clock.
At t-i, a timing signal 16-2 of the lower frequency clock is provided and the power-save count is accordingly reset to '20' (i.e. the ratio of the frequencies of the higher frequency and lower frequency clocks). The timing signal 16-2 of the lower frequency clock is also used to re-synchronise the higher and lower frequency 30 clocks by aligning the timing signal 18-6 of the higher frequency clock with the timing signal 16-2 of the lower frequency clock. At this point in time, the state-change count has reached '5'. The higher frequency clock may now be powered down because there has been a timing signal of the lower frequency clock during generation of the waveform. However, the higher frequency clock remains in 35 operation because the state-change count '5' is less than the power-save count '20'.
- 12 -
The state-change count continues to be decremented by one on each timing signal of the higher frequency clock. The power-save count is also now decremented by one on each timing signal of the higher frequency clock.
At t2, the state-change count reaches zero. The device places the waveform 5 in the second state 14 and the state-change count is accordingly set to '20' for that state in order to give the one second of "low" dictated by the required waveform. At this point in time, the power-save count has reached '15'. The higher frequency clock is accordingly powered down because the power-save count '15' is now less than the state-change count '20', i.e. it is determined that the state of the waveform 10 will not transition before the next timing signal of the lower frequency clock and therefore that the higher frequency clock is not imminently needed for a state transition. As there is no higher frequency clock between t2andt3, the change count and power-save count are not decremented between t2andt3.
At t3, a timing signal 16-3 of the lower frequency clock is provided and the 15 current state-change count '20' is reduced by the current power-save count '15' (as will be appreciated, the current power-save count at this point indicates how long the higher frequency clock has been powered down). Reducing the current state-change count '20' by the current power-save count '15' gives a state-change count of '5'. At this point in time, the power-save count is also reset to '20'. The higher 20 frequency clock is also operated again because the state-change count '5' is now less than the power-save count '20', i.e. it is determined that the state of the waveform will transition before the next timing signal of the lower frequency clock and that the higher frequency clock is imminently needed for a state transition. The state-change count and power-save count are then decremented by one on each 25 subsequent timing signal of the higher frequency clock.
At t4, the state-change count reaches zero. The digital signal 10 transitions to the first state 12 and the state-change count is accordingly set to '10' for that state. At this point in time, the power-save count has reached '15'. The higher frequency clock accordingly remains in operation because the state-change count 30 '10' is less than the power-save count '15'. The state-change count and power-save count continue to be decremented by one on each timing signal of the higher frequency clock.
As is shown in Figure 1, the process continues so as to generate a digital signal 10 comprising a pulse train having a number (np) of pulses (in this case 3 35 pulses). In some embodiments (not illustrated by Figure 1), the pulse train may be
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repeated a number (nt) of times to give a set of pulse trains. The start of each pulse train may be separated from the next by a time period (t,).
The above parameters (tp1, tp2, np, n, and/or t,) are predetermined for the digital signal 10. For example, those parameters may be stored in a memory of the 5 device that generates the waveform or may be provided to that device by an external host. Any of all of the above parameters may also be reconfigurable either by the device or by an external host.
Although the above embodiment has been described in the context of a voltage being applied to an LED, it will be appreciated that the waveform could 10 equally be used to drive any other suitable component, such as an audio component (e.g. a buzzer or speaker) or a transmitter that is used to transmit control signals or data (e.g. a wireless transmitter).
Figure 2 shows the digital signal 10, the lower frequency clock signal 16 and the higher frequency clock signal 18 of Figure 1. Figure 2 also shows the voltage 20 15 that is used to operate the device that generates the waveform. Figure 2 also shows the current 22 that is drawn by the device that generates the waveform. As is shown in Figure 2, the current 22 is higher at times when the higher frequency clock is operated (indicated by 24) and is lower at times when the higher frequency clock is powered down (indicated by 26). Accordingly, the power that is consumed by the 20 device that generates the waveform is reduced when the higher frequency clock is not operated. Embodiments of the present invention can therefore reduce the amount of power consumed by the device that generates the waveform.
Figure 3 shows a waveform generated in accordance with another embodiment of the present invention. The waveform of Figure 3 is similar to that of 25 Figures 1 and 2. Thus, the waveform again forms part of a digital signal 30, with the waveform having a first "high" state 32 and a second "low" state 34. However, in this embodiment, tpi is 0.5 seconds and tp2is 0.05 seconds giving a total complete waveform time of 0.55 seconds. Furthermore, in this embodiment, the waveform having the first "high" state 32 and second "low" state 34 are repeated a number 30 (nt) of times, with the start of each occurrence of the waveform being separated from the next by a time period (t,). In this particular embodiment, n, is one second, giving a pulse every one second.
Figure 3 also shows a lower frequency clock signal 36 having 1 Hz timing signals 36-1 to 36-5 and a higher frequency clock signal 38 having 20 Hz timing 35 signals 38-1 to 36-12.
- 14-
The waveform of this embodiment is generated in a similar manner to that of Figures 1 and 2. However, in this embodiment, the initial generation of the waveform is synchronised with a timing signal 36-2 of the lower frequency clock. Furthermore, the higher frequency clock is powered down after the waveform has 5 been completed (after timing signal 38-12) and before the next iteration of the waveform. This allows the higher frequency clock to be powered down in-between iterations of a given waveform.
Figure 4 shows a waveform generated in accordance with another embodiment of the present invention. The waveform of Figure 4 is similar to that of 10 Figures, 1 2 and 3. Thus, the waveform again forms part of a digital signal 40, with the waveform having a first "high" state 42 and a second "low" state 44. However, in this embodiment, tpi is 1 second and tp2 is one second.
Figure 4 also shows a lower frequency clock signal 46 having 1 Hz timing signals 46-1 to 46-3 and a higher frequency clock signal 48 having a timing signal 15 48-1.
The waveform of this embodiment is generated in a similar manner to that of Figures 1, 2 and 3. However, due to the time parameters of the waveform, only one higher frequency clock signal 48-1 is needed for each waveform pulse. This embodiment illustrates the maximum amount of power saving that can be achieved 20 with embodiments of the present invention.
Figure 5 shows a waveform generated in accordance with another embodiment of the present invention. In this embodiment, the waveform comprises a PWM signal 50, with the waveform having a first state 52 in which the PWM signal is active and a second state 54 in which the PWM signal is inactive. The 25 frequency f of the active PWM signal in this particular embodiment, shown in solid black due to the scale of Figure 5, is 5 kHz. As with the previous embodiments, the waveform is in the first state 52 for a first time period tpi and in the second state 54 for a second time period tp2 In this embodiment, tpi is 0.5 seconds and tp2 is 1 second.
30 Figure 5 also shows a lower frequency clock signal 56 having 1 Hz timing signals 56-1 to 56-3 and a higher frequency clock signal 58 having timing signals starting at timing signal 58-1.
The waveform of this embodiment is generated in a similar manner to that of Figures 1 and 2. Thus, whilst the waveform is in the second state 54, the higher 35 frequency clock is powered down if the state-change count is greater than or equal
- 15-
to the power-save count, i.e. if it is determined that the waveform will not transition from the second state 54 to the first state 52 before the next timing signal of the lower frequency count.
However, whilst the waveform is in the first state 52, the higher frequency clock remains in operation even if the state-change count is greater than or equal to the power-save count, i.e. even if it is determined that the waveform will not transition from the first state 52 to the first state 54 before the next timing signal of the lower frequency count. This allows, for example, the higher frequency clock to be used to provide the active PWM signal.
This alternative arrangement for operating the higher frequency clock when in the first state is better illustrated in Figure 6. In this embodiment, the waveform again comprises a PWM signal 60, with the waveform having a first state 62 in which the PWM signal is active and a second state 64 in which the PWM signal is inactive.
Figure 6 also shows a lower frequency clock signal 66 having 1 Hz timing signals 66-1 to 66-3 and a higher frequency clock signal 68 having timing signals starting at timing signal 68-1.
In this embodiment, tp1 is 1 second and tp2is 1 second and the initial generation of the waveform is synchronised with a timing signal 66-2 of the lower frequency clock. The parameters of the waveform in this embodiment are therefore similar to those of the embodiment of Figure 4 described above. However, unlike the embodiment of Figure 4, Figure 6 shows that the higher frequency clock remains in operation whilst the waveform is in the first state 62 so as to provide the active PWM signal.
Although preferred embodiments of the present invention have been described, it will be apparent to the skilled person that various features of those embodiments can be altered, removed or substituted without departing from the scope of the invention as defined by the appended claims.
- 16-
Claims (50)
1. A method of generating a predetermined waveform using a higher frequency clock and a lower frequency clock, the waveform transitioning between 5 first and second states in synchrony with timing signals of the higher frequency clock, the method comprising:
operating the higher frequency clock if the waveform will transition between said states before the next timing signal of the lower frequency clock; and powering down the higher frequency clock if the waveform will not transition 10 between said states before the next timing signal of the lower frequency clock.
2. A method as claimed in claim 1, wherein: the waveform forms part of a digital signal; the first state comprises a first digital level; and 15 the second state comprises a second digital level.
3. A method of generating a predetermined waveform using a higher frequency clock and a lower frequency clock, the waveform transitioning between first and second states in synchrony with timing signals of the higher frequency 20 clock, the method comprising:
operating the higher frequency clock if the waveform is in said first state;
and powering down the higher frequency clock if the waveform will not transition from said second state to said first state before the next timing signal of the lower 25 frequency clock.
4. A method as claimed in claim 3, wherein:
the waveform comprises a pulse width modulation (PWM) signal; the first state comprises the PWM signal being active; and 30 the second state comprises the PWM signal being inactive.
5. A method as claimed in claim 4, wherein:
the PWM signal has a frequency f in the range 490 Hz - 516 kHz.
35
6. A method as claimed in any one of the preceding claims, wherein:
- 17-
the waveform is in the first state for a first time period (tp1), the first time period being defined in the device that generates the waveform by an integer number of timing signals of the higher frequency clock; and/or the waveform is in the second state for a second time period (tp2), the 5 second time period being defined in the device that generates the waveform by an integer number of timing signals of the higher frequency clock.
7. A method as claimed in any one of the preceding claims, wherein:
the waveform is in the first state for a first time period (tpi), the first time 10 period being equal in time to an integer number of timing signals of the lower frequency clock; and/or the waveform is in the second state for a second time period (tp2), the second time period being equal in time to an integer number of timing signals of the lower frequency clock.
15
8. A method as claimed in any one of the preceding claims, wherein:
the waveform is repeated a number (np) of times to generate a pulse train.
9. A method as claimed in claim 8, wherein:
20 the pulse train is repeated a number (nt) of times to generate a series of pulse trains.
10. A method as claimed in claim 9, wherein:
the start of the respective pulse trains are separated by a third time period 25 (tt), the third time period being defined in the device that generates the waveform by an integer number of timing signals of the higher frequency clock.
11. A method as claimed in any one of claims 5-10, wherein:
f, tpi, tp2, np, n, and/or t, are reconfigurable parameters defined in a device 30 that generates the waveform.
12. A method as claimed in any one of the preceding claims, wherein:
the higher frequency clock has a time period (th) between timing signals, wherein th is in the range 25-100 ms, and is preferably 50 ms; and
- 18-
the lower frequency clock has a time period (t,) between timing signals, wherein t, is in the range 0.5-2 seconds, and is preferably 1 second.
13. A method as claimed in any one of the preceding claims, wherein: 5 the higher frequency clock has a lower relative and/or absolute timing signal precision; and the lower frequency clock has a higher relative and/or absolute timing signal precision.
10
14. A method as claimed in any one of the preceding claims, wherein:
the timing signals of the higher frequency clock are provided by a crystal oscillator.
15. A method as claimed in any one of the preceding claims, wherein:
15 the timing signals of the lower frequency clock are provided by a radio interval and/or are provided by a host that is external to a device that generates the waveform.
16. A method as claimed in any one of the preceding claims, wherein:
20 a state-change count is associated with the waveform, the state-change count providing an indication of when to transition between states; and/or a power-save count is associated with the waveform, the power-save count providing an indication of when the next timing signal of the lower frequency clock will occur.
25
17. A method as claimed in claim 16, comprising:
when the higher frequency clock is operated, decrementing the state-change count on each timing signal of the higher frequency clock.
30
18. A method as claimed in claim 16 or 17, comprising:
when the higher frequency clock is operated, decrementing the power-save count on each timing signal of the higher frequency clock.
19. A method as claimed in claim 16, 17 or 18, comprising:
- 19-
when the higher frequency clock is powered down, reducing the state-change count by the power-save count.
20. A method as claimed in any one of claims 16-19, comprising:
5 when the state-change count reaches a predetermined minimum,
transitioning the waveform between the first and second states.
21. A method as claimed in any one of claims 16-20, comprising:
setting the state-change count to a first number (np1) when transitioning the 10 waveform to the first state, where:
npi = tpi / th,
where th is the time period between timing signals of the higher frequency clock and tpi is the time period during which the waveform is in the first state; and/or setting the state-change count to a second number (np2) when transitioning 15 the waveform to the second state, where:
np2 = tp2/ th;
where th is the time period between timing signals of the higher frequency clock and tp2 is the time period during which the waveform is in the second state.
20
22. A method as claimed in any one of claims 16-21, comprising:
setting the power-save count to an integer (nps) on each timing signal of the lower frequency clock, where:
nps = t, / th, and/or nps = floor(ti / th);
25 where th is the time period between timing signals of the higher frequency clock and ti is the time period between timing signals of the lower frequency clock.
23. A method as claimed in any one of claims 16-22, comprising:
determining that the waveform will not transition between the first state and 30 the second state before the next timing signal of the lower frequency clock if the state-change count is greater than or equal to the power-save count; and/or determining that the waveform will transition between the first state and the second state before the next timing signal of the lower frequency clock if the state-change count is less than the power-save count.
35
-20-
24. A method as claimed in any one of the preceding claims, comprising:
if the higher frequency clock has previously been powered down and then is operated again, waiting at least until the next timing signal of the lower frequency clock before initially generating the waveform.
25. A method as claimed in any one of the preceding claims, wherein: the waveform is generated by a battery and/or solar powered device.
26. A device for generating a predetermined waveform using a higher 10 frequency clock and a lower frequency clock, the device being configured to transition the waveform between first and second states in synchrony with timing signals of the higher frequency clock, the device further being configured to:
operate the higher frequency clock if the waveform will transition between said states before the next timing signal of the lower frequency clock; and 15 power down the higher frequency clock if the waveform will not transition between said states before the next timing signal of the lower frequency clock.
27. A device as claimed in claim 26, wherein: the waveform forms part of a digital signal; 20 the first state comprises a first digital level; and the second state comprises a second digital level.
28. A device for generating a predetermined waveform using a higher frequency clock and a lower frequency clock, the device being configured to 25 transition the waveform between first and second states in synchrony with timing signals of the higher frequency clock, the device further being configured to:
operate the higher frequency clock if the waveform is in said first state; and power down the higher frequency clock if the waveform will not transition from said second state to said first state before the next timing signal of the lower 30 frequency clock.
29. A device as claimed in claim 28, wherein:
the waveform comprises a pulse width modulation (PWM) signal; the first state comprises the PWM signal being active; and 35 the second state comprises the PWM signal being inactive.
- 21 -
30. A device as claimed in claim 29, wherein:
the PWM signal has a frequency f in the range 490 Hz - 516 kHz.
5
31. A device as claimed in any one claims 26-30, wherein:
the waveform is in the first state for a first time period (tp1), the first time period being defined in the device by an integer number of timing signals of the higher frequency clock; and/or the waveform is in the second state for a second time period (tp2), the 10 second time period being defined in the device by an integer number of timing signals of the higher frequency clock.
32. A device as claimed in any one of claims 26-31, wherein:
the waveform is in the first state for a first time period (tp1), the first time 15 period being equal in time to an integer number of timing signals of the lower frequency clock; and/or the waveform is in the second state for a second time period (tp2), the second time period being equal in time to an integer number of timing signals of the lower frequency clock.
20
33. A device as claimed in any one of claims 26-32, wherein the device is configured to:
repeat the waveform a number (np) of times to generate a pulse train.
25
34. A device as claimed in claim 33, wherein the device is configured to:
repeat the pulse train a number (nt) of times to generate a series of pulse trains.
35. A device as claimed in claim 34, wherein:
30 the start of the respective pulse trains are separated by a third time period
(tt), the third time period being defined in the device by an integer number of timing signals of the higher frequency clock.
36. A device as claimed in any one of claims 30-35, wherein:
35 f, tpi, tp2, np, n, and/or t, are reconfigurable parameters defined in the device.
- 22 -
37. A device as claimed in any one of claims 26-36, wherein:
the higher frequency clock has a time period (th) between timing signals, wherein th is in the range 25-100 ms, and is preferably 50 ms; and 5 the lower frequency clock has a time period (t,) between timing signals,
wherein t, is in the range 0.5-2 seconds, and is preferably 1 second.
38. A device as claimed in any one of claims 26-37, wherein:
the higher frequency clock has a lower relative and/or absolute timing signal 10 precision; and the lower frequency clock has a higher relative and/or absolute timing signal precision.
39. A device as claimed in any one of claims 26-38, wherein:
15 the timing signals of the higher frequency clock are provided by a crystal oscillator of the device.
40. A device as claimed in any one of claims 26-39, wherein:
the timing signals of the lower frequency clock are provided by a radio 20 interval and/or are provided by a host that is external to the device.
41. A device as claimed in any one of claims 26-40, wherein the device is configured to:
associate a state-change count with the waveform, the state-change count 25 providing an indication of when to transition between states; and/or associate a power-save count with the waveform, the power-save count providing an indication of when the next timing signal of the lower frequency clock will occur.
30
42. A device as claimed in claim 41, wherein the device is configured to:
when the higher frequency clock is operated, decrement the state-change count on each timing signal of the higher frequency clock.
43. A device as claimed in claim 41 or 42, wherein the device is configured to:
-23-
when the higher frequency clock is operated, decrement the power-save count on each timing signal of the higher frequency clock.
44. A device as claimed in claim 41, 42 or 43, wherein the device is configured 5 to:
when the higher frequency clock is powered down, reduce the state-change count by the power-save count.
45. A device as claimed in any one of claims 41 -44, wherein the device is 10 configured to:
when the state-change count reaches a predetermined minimum, transition the waveform between the first and second states.
46. A device as claimed in any one of claims 41 -45, wherein the device is 15 configured to:
set the state-change count to a first number (np1) when transitioning the waveform to the first state, where:
npi = tp-i / th,
where th is the time period between timing signals of the higher frequency 20 clock and tp1 is the time period during which the waveform is in the first state; and/or set the state-change count to a second number (np2) when transitioning the waveform to the second state, where:
np2 = tp2/ th;
where th is the time period between timing signals of the higher frequency 25 clock and tp2 is the time period during which the waveform is in the second state.
47. A device as claimed in any one of claims 41 -46, wherein the device is configured to:
set the power-save count to an integer (nps) on each timing signal of the 30 lower frequency clock, where:
nps = ti / th, and/or nps = floor(ti / th);
where th is the time period between timing signals of the higher frequency clock and t, is the time period between timing signals of the lower frequency clock.
35
- 24-
48. A device as claimed in any one of claims 41 -46, wherein the device is configured to:
determine that the waveform will not transition between the first state and the second state before the next timing signal of the lower frequency clock if the 5 state-change count is greater than or equal to the power-save count; and/or determine that the waveform will transition between the first state and the second state before the next timing signal of the lower frequency clock if the state-change count is less than the power-save count.
10
49. A device as claimed in any one of claims 26-48, wherein the device is configured to:
if the higher frequency clock has previously been powered down and then is operated again, wait at least until the next timing signal of the lower frequency clock before initially generating the waveform.
15
50. A device as claimed in any one of claims 26-49, wherein:
the device is a battery and/or solar powered device.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1203038.3A GB2499615A (en) | 2012-02-22 | 2012-02-22 | Waveform generation |
| TW102104927A TWI608697B (en) | 2012-02-22 | 2013-02-07 | Waveform generation |
| JP2014558207A JP6053830B2 (en) | 2012-02-22 | 2013-02-22 | Waveform generation |
| EP13707205.4A EP2817884A1 (en) | 2012-02-22 | 2013-02-22 | Waveform generation |
| PCT/GB2013/050436 WO2013124667A1 (en) | 2012-02-22 | 2013-02-22 | Waveform generation |
| CN201380009578.7A CN104115401B (en) | 2012-02-22 | 2013-02-22 | Waveform generating |
| KR1020147026304A KR20140127891A (en) | 2012-02-22 | 2013-02-22 | Waveform generation |
| US14/374,864 US9356579B2 (en) | 2012-02-22 | 2013-02-22 | Waveform generation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1203038.3A GB2499615A (en) | 2012-02-22 | 2012-02-22 | Waveform generation |
Publications (2)
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| GB201203038D0 GB201203038D0 (en) | 2012-04-04 |
| GB2499615A true GB2499615A (en) | 2013-08-28 |
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| GB1203038.3A Withdrawn GB2499615A (en) | 2012-02-22 | 2012-02-22 | Waveform generation |
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| EP (1) | EP2817884A1 (en) |
| JP (1) | JP6053830B2 (en) |
| KR (1) | KR20140127891A (en) |
| CN (1) | CN104115401B (en) |
| GB (1) | GB2499615A (en) |
| TW (1) | TWI608697B (en) |
| WO (1) | WO2013124667A1 (en) |
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| US9945926B2 (en) * | 2014-11-26 | 2018-04-17 | Vesperix Corporation | Method of designing bandwidth efficient ranging waveforms |
| GB2545718A (en) * | 2015-12-23 | 2017-06-28 | Nordic Semiconductor Asa | Radio transceivers |
| TWI584191B (en) * | 2016-07-26 | 2017-05-21 | 東元電機股份有限公司 | Method for checking control instruction of driving device by using control instruction waveform |
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| US5815819A (en) * | 1995-06-30 | 1998-09-29 | Nippondenso Co., Ltd. | Intermittent reception control apparatus |
| US6009319A (en) * | 1996-09-06 | 1999-12-28 | Telefonaktiebolaget Lm Ericsson | Method and apparatus for reducing power consumption in a mobile radio communication device |
| US6044282A (en) * | 1997-08-15 | 2000-03-28 | Sharp Laboratories Of America, Inc. | Dual clock power conservation system and method for timing synchronous communications |
| JP2003023369A (en) * | 2001-07-10 | 2003-01-24 | Sharp Corp | Device and method for communication for performing intermittent transmitting/receiving |
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| JP3184265B2 (en) * | 1991-10-17 | 2001-07-09 | 株式会社日立製作所 | Semiconductor integrated circuit device and control method therefor |
| US6433584B1 (en) * | 1998-06-18 | 2002-08-13 | Hitachi, Ltd. | Semiconductor integrated circuit |
| JP2004087602A (en) * | 2002-08-23 | 2004-03-18 | Fujitsu Ltd | Semiconductor integrated circuit device |
| US7113011B2 (en) * | 2004-06-21 | 2006-09-26 | Silicon Laboratories Inc. | Low power PLL for PWM switching digital control power supply |
| GB2425668B (en) * | 2005-01-17 | 2009-02-25 | Wolfson Microelectronics Plc | Pulse width modulator quantisation circuit |
| US20080246650A1 (en) * | 2005-01-28 | 2008-10-09 | Tasuku Teshirogi | Short Range Radar and Method of Controlling the Same |
| GB2441572B (en) * | 2006-09-05 | 2009-01-28 | Stream Technology Ltd M | Switching amplifier |
| US7436233B2 (en) | 2006-11-01 | 2008-10-14 | Sync Power Corp. | Normal mode and green mode pulse width modulation controller |
| CN100553090C (en) * | 2007-03-19 | 2009-10-21 | 立锜科技股份有限公司 | Reduce the method and the circuit of the switching concussion in the switched power supply |
-
2012
- 2012-02-22 GB GB1203038.3A patent/GB2499615A/en not_active Withdrawn
-
2013
- 2013-02-07 TW TW102104927A patent/TWI608697B/en not_active IP Right Cessation
- 2013-02-22 KR KR1020147026304A patent/KR20140127891A/en not_active Application Discontinuation
- 2013-02-22 JP JP2014558207A patent/JP6053830B2/en not_active Expired - Fee Related
- 2013-02-22 WO PCT/GB2013/050436 patent/WO2013124667A1/en active Application Filing
- 2013-02-22 CN CN201380009578.7A patent/CN104115401B/en not_active Expired - Fee Related
- 2013-02-22 EP EP13707205.4A patent/EP2817884A1/en not_active Withdrawn
- 2013-02-22 US US14/374,864 patent/US9356579B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5815819A (en) * | 1995-06-30 | 1998-09-29 | Nippondenso Co., Ltd. | Intermittent reception control apparatus |
| US6009319A (en) * | 1996-09-06 | 1999-12-28 | Telefonaktiebolaget Lm Ericsson | Method and apparatus for reducing power consumption in a mobile radio communication device |
| US6044282A (en) * | 1997-08-15 | 2000-03-28 | Sharp Laboratories Of America, Inc. | Dual clock power conservation system and method for timing synchronous communications |
| JP2003023369A (en) * | 2001-07-10 | 2003-01-24 | Sharp Corp | Device and method for communication for performing intermittent transmitting/receiving |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2817884A1 (en) | 2014-12-31 |
| CN104115401B (en) | 2017-12-08 |
| WO2013124667A1 (en) | 2013-08-29 |
| CN104115401A (en) | 2014-10-22 |
| GB201203038D0 (en) | 2012-04-04 |
| KR20140127891A (en) | 2014-11-04 |
| TW201336223A (en) | 2013-09-01 |
| JP6053830B2 (en) | 2016-12-27 |
| US20150035571A1 (en) | 2015-02-05 |
| US9356579B2 (en) | 2016-05-31 |
| JP2015513256A (en) | 2015-04-30 |
| TWI608697B (en) | 2017-12-11 |
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