GB2498949A - An octal clock phase interpolator - Google Patents
An octal clock phase interpolator Download PDFInfo
- Publication number
- GB2498949A GB2498949A GB1201611.9A GB201201611A GB2498949A GB 2498949 A GB2498949 A GB 2498949A GB 201201611 A GB201201611 A GB 201201611A GB 2498949 A GB2498949 A GB 2498949A
- Authority
- GB
- United Kingdom
- Prior art keywords
- phase
- clock
- clocks
- stage
- interpolator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00208—Layout of the delay element using FET's using differential stages
Abstract
A set of variably rotated octal clocks is generated by rotating each of four quadrature input clocks by the same variable angle and feeding the four rotated clocks to a pair of further similar phase rotators that shift the four rotated clocks by plus and minus 22.5 degrees (pi/8 radians). The use of similar circuit blocks in each stage reduces design time. The octal clocks may be used for data capture in an oversampled clock/data (CDR) recovery system where the sampling frequency is twice that of the frequency of reference clock edges. The complementary rotations effected by the further rotators may optionally be variable.
Description
1
OCTAL CLOCK PHASE INTERPOLATOR ARCHITECTURE FIELD OF THE INVENTION
The present invention relates to phase interpolaters, and more particularly to an octal clock phase interpolator architecture.
BACKGROUND OF THE INVENTION
A known interpolator-based over-sampled clock/data recovery (CDR) scheme is disclosed in the Applicant's prior patent no. GB2415101. In this scheme a set of four quadrature clocks are rotated to generate a set of four aligned clocks with which to capture samples from the serial data stream.
However, there is a need for an octal clock CDR phase interpolator architecture which the known prior scheme does not address.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an apparatus and method of generating a set of 8 clock signals nominally spaced at equal 45° intervals by phase interpolation from a set of 4 quadrature reference clocks. The scheme is useful for clock generation for data capture in an oversampled clock/data recovery (CDR) system where the frequency of data sampling is twice that of the frequency of reference clock edges.
The proposed architecture of the present invention takes advantage of the re-use of just two basic building blocks to minimise design time and support.
According to a first aspect of the invention there is provided a clock phase generating means for generating a set of eight clock phases for a clock/data recovery application,
2
comprising: a rotating first stage interpolator; and a pair of fixed-phase second stage interpolators; wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks.
Preferably, the order of bias signals to one of said second stage interpolators is reversed causing its output clocks to be rotated by 22.5° in the opposite direction to that of said other one of the second stage interpolators, thereby establishing a 45° phase shift between the first and second interpolator clock outputs.
According to a second aspect of the invention there is provided an octal clock phase interpolator comprising the clock phase generating means of the first aspect.
Further embodiments of the invention are as set forth in the accompanying claims.
Examples of the invention will now be described with reference to the accompanying drawings of which:
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows representative waveforms for a typical interpolator-based over-sampled clock/data recovery scheme;
Figure 2 shows representative waveforms for an interpolator-based over-sampled clock/data recovery scheme where the data rate is 2x higher than that shown in Figure 1;
Figure 3 shows a generic structure of a 4-quadrant phase interpolator;
Figure 4 shows an interpolation block using two of the circuits of Figure 3 in parallel which share the same bias controls (VB0...VB3) but with the clock inputs to the second rotated by 90° with respect to the first;
Figure 5 shows the structure and operation of a bias generator; and
3
Figure 6 shows a scheme for generating octal data recovery clocks in accordance with a preferred embodiment of the present invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION
Representative waveforms for a prior interpolator-based over-sampled clock/data recovery scheme as disclosed in the Applicant's patent no. GB2415101 are shown in Figure 1. In this scheme a set of four quadrature clocks are rotated to generate a set of four aligned clocks with which to capture samples from the serial data stream.
However the present invention addresses the case where the data rate is 2x higher than that shown in Figure 1 and consequently demands a higher granularity of data sampling as shown in Figure 2.
The generic structure of a 4-quadrant phase interpolator according to the Applicant's GB patent no. GB2415101 is shown in Figure 3 and consists of a set of 4 differential amplifiers driven by quadrature clocks ClkO & Clkl and their complements Clk2 & Clk3 (i.e. 4 quadrature phases in total) . The four differential amplifiers effectively operate at 90°intervals and each is connected to a current source device whose bias voltage is controlled in order to adjust the phase of the outgoing clock to the desired alignment.
The differential output signals in Figure 3 are each amplified back up to full rail-to-rail swing signals to produce a pair of complementary CMOS clock signals.
By using two of these circuits in parallel which share the same bias controls (VB0...VB3) but with the clock inputs to the second rotated by 90° with respect to the first, a unit block is constructed which takes in 4 quadrature reference clocks and
4
outputs 4 quadrature clocks of the same frequency but whose output phases may all be rotated (relative to the inputs) under control of the applied bias voltages. The symbol for such an interpolation block is shown in Figure 4.
As described above, the phase of the output signal is controlled by the 4 bias voltages applied to each of the 4 differential pairs in the phase interpolator bridge. One such apparatus for achieving this is described in the Applicant's GB patent no. GB 2415100, and consists of an array of differentially switched current sources controlled using a thermometer code (PS<30:0> and complement PSZ<30:0>) to adjust the phase within a quadrant in conjunction with a 2-bit quadrant select code (QS<1:0> and complement QSZ<1:0>) to select the currently active quadrant. One possible embodiment of this bias generator is illustrated in Figure 5.
Octal Clock Generation
The inventors have realised a solution for generating the octal data recovery clocks according to the present invention as shown in Figure 6. The first bias control block is controlled by the CDR loop to rotate the four quadrature input clocks to provide four further quadrature clocks with the required phase. This would only have been an adequate solution for the CDR scheme at half the data rate shown in Figure 1. However, a second pair of phase interpolators is then used to rotate the clocks nominally by 22.5° but crucially the order of bias signals to one of these interpolators is reversed. This causes its output clocks to be rotated by 22.5° in the opposite direction, thus establishing a 45° phase shift between the first and second interpolator clock outputs. The combined outputs from the two second stage interpolator blocks thus provide all 8 clocks required to implement the data capture scheme shown in Figure 2.
5
Although the second stage bias control is nominally fixed, it may be desirable to optionally include some means of adjustment of its phase setting to adjust the timings between the clocks output from the two 2nd stage interpolators. Such adjustment will rotate the interpolators in opposite directions, thereby changing the timing between the two interleaved sets of clock phases.
6
Claims (8)
1. A clock phase generating means for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator; and a pair of fixed-phase second stage interpolators; wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks.
2. A clock phase generating means as according to claim 1, wherein the order of bias signals to one of said second stage interpolators is reversed causing its output clocks to be rotated by 22.5° in the opposite direction to that of said other one of the second stage interpolators, thereby establishing a 45° phase shift between the first and second interpolator clock outputs.
3. A clock phase generating means as according to claim 1 or 2, further comprising phase setting adjustment means for rotating the phase of the second stage interpolators in opposite directions
4. A clock phase generating means as according to claim 1 or 2, further comprising bias control adjustment means for adjustment of the phase setting of said second stage interpolators to adjust the timings between the clocks output from the two second stage interpolators.
5. An octal clock phase interpolator comprising the clock phase generating means according to any one of claims 1 to 4.
7
6. A receiver-side circuit comprising an octal clock phase interpolator according to claim 5.
7. Subject matter of the foregoing description in any novel or inventive combination thereof.
8. The subject matter of the statements of invention characterized by the features recited therein.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1201611.9A GB2498949A (en) | 2012-01-31 | 2012-01-31 | An octal clock phase interpolator |
US13/755,782 US20130285727A1 (en) | 2012-01-31 | 2013-01-31 | Octal clock phase interpolator architecture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1201611.9A GB2498949A (en) | 2012-01-31 | 2012-01-31 | An octal clock phase interpolator |
Publications (2)
Publication Number | Publication Date |
---|---|
GB201201611D0 GB201201611D0 (en) | 2012-03-14 |
GB2498949A true GB2498949A (en) | 2013-08-07 |
Family
ID=45876368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1201611.9A Withdrawn GB2498949A (en) | 2012-01-31 | 2012-01-31 | An octal clock phase interpolator |
Country Status (2)
Country | Link |
---|---|
US (1) | US20130285727A1 (en) |
GB (1) | GB2498949A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115833798B (en) * | 2023-02-15 | 2023-05-02 | 南京沁恒微电子股份有限公司 | High-linearity multi-bit phase interpolator |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7912167B2 (en) * | 2006-02-01 | 2011-03-22 | Renesas Electronics Corporation | Clock and data recovery circuit |
US7961830B2 (en) * | 2005-08-24 | 2011-06-14 | Samsung Electronics Co., Ltd. | Clock and data recovery circuit having wide phase margin |
US7991103B2 (en) * | 2007-09-19 | 2011-08-02 | Intel Corporation | Systems and methods for data recovery in an input circuit receiving digital data at a high rate |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101083674B1 (en) * | 2008-11-11 | 2011-11-16 | 주식회사 하이닉스반도체 | Multi-Phase Clock Generation Circuit |
-
2012
- 2012-01-31 GB GB1201611.9A patent/GB2498949A/en not_active Withdrawn
-
2013
- 2013-01-31 US US13/755,782 patent/US20130285727A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7961830B2 (en) * | 2005-08-24 | 2011-06-14 | Samsung Electronics Co., Ltd. | Clock and data recovery circuit having wide phase margin |
US7912167B2 (en) * | 2006-02-01 | 2011-03-22 | Renesas Electronics Corporation | Clock and data recovery circuit |
US7991103B2 (en) * | 2007-09-19 | 2011-08-02 | Intel Corporation | Systems and methods for data recovery in an input circuit receiving digital data at a high rate |
Also Published As
Publication number | Publication date |
---|---|
US20130285727A1 (en) | 2013-10-31 |
GB201201611D0 (en) | 2012-03-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |