GB2497188A

GB2497188A - Power efficient high speed backplane driver circuit with high voltage swing

Info

Publication number: GB2497188A
Application number: GB201221020A
Authority: GB
Inventors: Dushmantha Rajapaksha; Giuseppe Surace; Peter Hunt
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2011-11-29
Filing date: 2012-11-22
Publication date: 2013-06-05
Also published as: GB201120505D0; GB201201171D0; GB201221020D0; GB2497145A

Abstract

A power efficient transmitter with a high voltage swing capability for sending data along long backplanes is disclosed. The transmitter circuit includes i) a current switching, current mode logic (CML) type driver (transitors M5-M8) connected to the transmitter output terminals TXP & TXN, and ii) a low-voltage differential signal (LVDS) type driver (transistors M1-M4) having an output node connected to the transmitter output TXP & TXN via a terminating load (resistors Rt). In a standard configuration, the LVDS output node would determine the common mode or receiver bias voltage. In the present invention, the LVDS type stage is switched by the driver input signal (INP, INN) in synchronism with the CML type stage to establish at the LVDS output node a voltage that is substantially the same as that which the ac driven leg of a CML type driver would take up, thereby reducing current through, and power loss in, the terminating resistors Rt.

Description

POWER EFFICIENT HIGH SWING LONG REACH TRANSMITTER ARCHITECTURE

The use of lower supply voltages is becoming prevalent for sub micron technologies, however the requirement to send high speed data along long backplanes (having attenuation greater than 26dB) requires large launch amplitudes to be generated at the transmitter. Package losses can amount to -3dB at 12.5Gbps and even higher losses at 17.5Gbps, hence having the capability to generate launch amplitudes in the 1.SVdifferential peak-to-peak (diffpk-pk) to 2Vdiffpk-pk is required.

Pure doubly terminated CML transmitter architectures suffer from high power dissipation since the load seen is effectively 25Ohms for the example a dc path of two 500hm termination resistors appearing in parallel at the receiver (1V differential peak-to-peak requires 2OmA). Voltage drive schemes can have lower power dissipation since the load seen is effectively 2000hm for example a dc path of fout 500hm termination resistors in series between the high and low differential drivers (lVdiffpk-pk, requiring 5mA). However while CML can provide 1.4V diffpk-pk, conventional voltage drive schemes are incapable of providing more than 1.2V diffpk-pk. Voltage drive schemes are ideal in short reach chip to chip applications where low swing is adequate.

Thus there is a need for a power efficient/low power transmitter for sending high speed data along long backplanes.

The present invention mitigates some of the problems and needs by providing a power efficient transmitter with a high voltage swing capability.

A standard configuration of LVDS is shown in Fig.2, which circuit closely follows that described in United States Patent 7,304,494 (Fig.1), and wherein the common mode voltage derived at the coupling point of the transmitter termination resistors (20, 21) will be observed. A similar circuit is shown in United States Patent 7,598,779 which likewise goes on to describes a combined LVDS/CML type transmitter circuit.

The present invention provides apparatus as set forth in the claims.

The proposed power efficient or low power high swing transmitter is described below with reference to the accompanying drawings of which: Figure 1 is a diagram showing a switched load low voltage differential signalling (LVDS) driver transmitter architecture in accordance with the present invention; The basis of the invention is to separate the inputs which in a typical LVDS arrangement would provide the common mode voltage coupling of the prior art and instead switch them in synchronism with the driver signal such that the output nodes acquire the same voltage as the ac driven leg of the CML type driver would take up, or close to it. Now current flow through the transmitter termination resistor is reduced.

The voltage swing at the output is: VREGHI-VREGLO = VSWING/2, which enables the swing to be set to a desired value larger than would be achievable with LVDS alone.

The present invention provides a low power or power efficient transmitter with a high voltage swing capability. Such a transmitter is particularly suited to SerDes transmitters and their architecture. Figure 1 shows a new AC coupled switched load low voltage differential signaling (LVDS) driver proposed for such a transmitter architecture in accordance with the invention, having the capability of supplying 1.5V to >2V differential peak-to-peak (duff pk-pk) with standard VDD input/output (I/O) supply voltages. The transmitter driver consists of an LVDS style driver bridge section comprising the switching devices M5, M6, M7 and M8, which drives the l000hm Rext load (500hm+500hm) to the ac coupling point situated at the receiver. The Transmitter termination 500hm impedance (Rt) is switched synchronously in accordance with the data such that the DC power though the loads approaches zero. The ft termination resistors are terminated to suppiy voltages (VREG_HI) which match the swing required from the transmitter. The VREG_LO regulator is employed to give adequate headroom for M7/M8 and the 12 current source device. The switching of the load effectively reduces the current dissipation by a factor of 2 compared with conventional LVDS drivers and 4 compared with conventional CML drivers.

The architecture of the transmitter lends itself to variable swing operation by modifying 11/12 amplitude and also the VREG_HI and VREG_LO regulated supply voltages. De-emphasis is achieved in the normal manner of having N fingers and switching some in sympathy with and some in anti-phase to the data pattern.

The capacitance on the output node is minimized since the devices M7, M8, M5 and MS can be sized to supply 8mA nominal current at 1 LV diffpk-pk output voltage. This minimizes the size of the devices and hence the output capacitance. The driver uses core devices which offer fastest speed operation and use the core logic supply voltage, O.9V to 1.OV nominal supply.

Claims

<claim-text>CLAIM1. A transmitter for data transfer apparatus including: a current switching CML type driver connected to a transmitter output; and a voltage LVDS type driver connected to the transmitter output via a terminating load at an LVDS node which would, in a standard configuration, determine common mode or receiver bias voltage; the LVDS type stage being switched in synchronism with the CML type stage to establish at that circuit node a voltage that is substantially the same as that as the ac driven leg of the CML type driver would take up, thereby to reduce common mode current through termination resistors compared to said standard configuration.</claim-text> <claim-text>2. A transmitter substantially as herein described with reference to Fig. 1 of the drawings.</claim-text>