GB2487232A - Bit Flipping in LDPC/Turbo Decoding - Google Patents

Abstract

A Low Density Parity Check (LDPC)/Turbo decoder performs a first parity check 101 based on different parts of a parity check matrix and, if the first check fails, inverts the sign ( flips ) bits 104 whose estimated likelihood 103 falls below a threshold (Πi<λi) determined by a gradient descent inversion function, before carrying out a second parity check.  The threshold may be lowered (as in Adaptive Threshold Bit Flipping, ATBF) by a factor θ<1 and the corresponding syndrome (ie. non-zero elements of ith row of fig. 2) updated before this second check. The parity check matrix is divided into D blocks of rows (D=3 in fig. 2), with at most 1 non-zero value in each column within a block, allowing serial (Z=1) or parallel (Z>1) processing of each block.

Description

I

Turbo Decoding Bit Flipping

FIELD

Embodiments described herein generally relate to parity check algorithms. In particular embodiments described herein relate to parity check algorithms including bit flipping techniques.

BACKGROUND

Low Density Parity Check (LDPC) codes have shown error correcting performance approaching channel capacity and thus are desirable in systems requiring robust performance. In addition their comparatively simple decoding structure has led to them being adopted in high throughput systems. One category of LDPC algorithms, referred to as bit flipping, has received considerable attention due to the need for high throughput decoding. The basic strategy in bit flipping is to find unreliable bits in a codeword and flip them until all parity checks involving the bits are satisfied or the maximum number of iterations is reached.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiment of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which: Figure 1 shows a known implementation of an Adaptive Threshold Bit Flipping (ATBF) algorithm; Figure 2 shows a layered LDPC code; Figure 3 shows an implementation of the Turbo-ATBF algorithm; Figure 4 shows the signal to noise dependence of the bit error rate performance of the Turbo-ATBF method using a 336x672 1/2-rate layered LDPC code with Z42; Figure 5 shows the average number of decoding iterations required by the Turbo-ATBF code using a 1/2-rate layered LDPC code; and Figure 6 shows the architecture of an appartus in which the Turbo-ATBF altgorithm can be operated/implemented.

DETAILED DESCRIPTION

According to one embodiment there is provided an LDPC decoding method comprising performing consecutive first and second parity checks on hard decision data. The first and second parity checks are based on different parts of a parity check matrix. Each of the parts of the parity check matrix comprises at most one non-zero value for each data point of the hard decision data. After the first parity check has been performed and before the second parity check is performed a likelihood that the sign of the hard decision bit is incorrect is estimated for each hard decision data bit. Before the second parity check is performed, the sign of one or more hard decision bit for which the estimated likelihood is below a threshold value is inverted. Both the first and the second parity check are performed as part of the same iteration of parity check based on the parity check matrix.

Both first and second parity checks may be based on a row of the parity check matrix that comprise a non-zero entry for the same data point. It will be appreciated that the signs of more than one hard decision values can be inverted following each parity check, rather than merely the sign of a single hard decision value, as is the case in some known algorithms.

Each of the parts of the matrix can comprise more than one row of the matrix. As part of the first and/or the second parity checks; parity checks may, in this case, be performed in parallel for each row of the part. Layered LDPC codes may find particular use in this context.

A gradient descent invention technique may be used for determining the likelihood for each of the hard decision data bits. The gradient descent inversion technique may use the following syndrome in estimating the likelihood referred to above for each row of the parity check matrix involved in the first parity check: JJJ xe{+i,-1} jN(i) N is hereby the set of non-zero values in the i-tb row of the parity check matrix. x are the hard decision values at the non-zero positions of the i-tb row of the parity check matrix. The method may further comprise updating this syndrome before the second parity check is performed.

A decision on whether or not the sign of a hard decision data point is to be inverted is made based on a threshold value. A threshold value for one or more hard decision data points may be reduced if the sign of the hard decision value is not inverted. This reduction may be applied before the second parity check is performed.

According to another aspect of the present invention there is provided an apparatus comprising a memory storing a parity check matrix and a first processor. The first processor is operable to perform, on hard decision data values that are to be checked, a first parity check based on a first row of the parity check matrix, to estimate a likelihood for each hard decision data bit that the sign of the hard decision bit is incorrect, to invert the sign of one or more hard decision bit for which the determined likelihood is below a threshold value and to perform, on the hard decision data values, a second parity check based on a second row of the parity check matrix, only after the estimating and inverting, wherein the second row of the parity check matrix comprises at least one non-zero value for a hard decision bit for which the first row of the parity check matrix also comprises a non-zero value.

According to another aspect there is provided a receiver comprising an apparatus as described above. The receiver may form part of a network, such as part of a WLAN, WPAN or an UWB network.

According to another aspect there is provided a data storage device comprising an apparatus as described above. The apparatus is in this case arranged to check the integrity of the stored data and to correct any errors in the data.

Isrnail, M et al disclose an improved bit flipping algorithm in "Low Latency Low Power Bit Flipping Algorithms For LDPC Decoding", IEEE Intl. Symp. on Personal Indoor and Mobile Radio Communications (PIMRC), September 2010.

This bit flipping algorithm has been named Adaptive Threshold Bit Flipping S (ATBF) algorithm and will be described in the following.

Let y = (y1,y2,.. . ,) be the vector of N received soft decision values, with Yk represent the IdtA element of the received vector, and E {+i,-i}" the corresponding hard decision values x=(,x2,. . .,x) determined according to: x, :=sign(y,) (1) N(i) = e [1, n] = i} is the index of non-zero elements in row and M(j) = [1,m] = i} is an index of non-zero elements in column of the parity check matrix H with j being the -element of the parity check matrix.

N is the set of bits participating in check and is the set of checks participating in the updating of bit3.

The i-th bipolar syndrome of x is defined as: JJ X3{+1,-1} (2) jEN(i) Let Ak,k e {i,. .. ,N} be a negative threshold value associated with each of the received bits.

The ATBF algorithm can be defined as shown in Algorithm 1.

1) Initialise 4k' Ic E ii,nI 2) j c [tn], let X:=sLgTL(y) LetX (Xt,X21...aXn) 3) If the parityequation 1-I Xj = +1 feNCE) holds for all t e (Lm] then output X and stop.

4) ForkE[tn}, + 5 Calculate 490) If 6Y<i. flip bitxk, otherwise, let Ak OAk, where is a scaling factor 5) If the number of iterations has not reached the set limit return to step 3 otherwise output and stop Algorithm 1: Adaptive Threshold Bit Flipping (ATBF) After initialising the threshold values in step (1) of the algorithm and calculating the hard decision values x, in step (2), a parity check is performed in step (3). This parity check uses all of the rows of the parity check matrix. If all the parity equations are satisfied, then there is no need to proceed with further S checks and the algorithm can be terminated. If, however, the parity check indicates a need for correction, then, in step (4), the gradient descent inversion function: (GD) (3 k (X)_XkYk+ Xj IeM(k) jENQ) is used to determine an indication of the confidence with which the bit k should be flipped. If the gradient descent inversion function ar'" (x)for bit k is below the threshold 4for bit k, then bit k is flipped. If the gradient descent inversion function arD) (x) for bit k is above the threshold 1for bit k, then the threshold for bit k is lowered in preparation for the next iteration.

Figure 1 shows a functional representation of the ATBF algorithm as it may be implemented in hardware or software. Block 100 takes the initial hard decision values,X, of the received values Y, and maps the appropriate combination for a particular parity check. Each of the parity check blocks 101 performs an exclusive-OR operation of the hard decision values mapped to it with the relevant row of the parity check matrix. Block 102 provides the correct combination of parity check values for calculating each of the A1 values in blocks 103. The soft values Yj are also provided to blocks 103, so that the values 4 can be calculated in accordance with equation (3). Blocks 104 compare the so calculated values A, with threshold values Aiapplicable to the individual ones of the values A1 If the calculated value of j is below the threshold value the bit Xj is flipped, otherwise the threshold value is scaled by a factor9withO<Oci.

Algorithm I performs all parity checks prior to making a decision on whether or not one or more of the bits should be flipped. Preferred embodiments improve upon this algorithm and will be described in the following.

This algorithm will be referred to at the Turbo-ATBF (TATBF) algorithm.

Let the parity check matrix representing an LDPC code consist of Mrows and N columns. Let R be constructed from a combination of z z permuted identity matrices and all zero matrices. Thus, there areD horizontal bands forming a layered construction of a parity check matrix.

The Turbo-ATBF (TATBF) algorithm can be stated as follows: 1) Initialise Ak, PC [1,n] as a set of negative threshold values 2) j e (tn] let xj:=si,gn(yj) Let 3) If the parity equation [-I jEN(i) holds for all t e ELm) then output and stop.

4) For i = I to D (N.B. This can be in any order) For, Calculate Ar using equation (3) for iç(we [N(q)], q [(i-1)xZ+1,ixZ]) If °° <Ak flip bitxk and update all syndrome check equations (see equation (2) above) Xk involved in, otherwise let & where° is a scaling factor, with 6 >1.

5) If the number of iterations has not reached a set limit return to step 3 otherwise output X and stop Algorithm 2: Turbo Adaptive Threshold Bit Flipping (TATBF) As can be seen from the above, Algorithms I and 2 are the same as far as steps 1 to 3 and 5 are concerned. The two algorithms, however, differ in the fourth step. Each of passes I to D preformed in the fourth step relates to one of the horizontal layers of the parity check matrix. Each horizontal layer is constructed such that it comprises at most one non-zero value in each column.

An example of such a parity check matrix is shown in Figure 2. This enables the parity check in all of the rows of a horizontal layer to be performed in parallel in a conflict free manner. This is indicated in step (4) of Algorithm 2. q indicates the rows of the parity check matrix that are being considered in a particular sub-iteration and w comprises the indexes in which the horizontal layer being considered has non-zero values.

In each pass performed in step (4) of Algorithm 2, at most one value r(x)is calculated for each bit. In contrast to ATBF Algorithm 1 in the TATBF method a bit is flipped if the value ArD) (x) is below the associated threshold 15,before any further parity checks involving bit k are performed. The inventors have realised that this is possible and that by doing so error correction speed can be increased without reduction in bit error rate.

The flipping of a bit also changes the syndromes to which the bit contributes. Consequently the algorithm updates all syndromes upon which the flipped bit has an influence. It is hereby not necessary for the syndrome to be re-calculated. Instead the sign of the previously calculated syndrome can simply be inverted, thereby mirroring the effect the flipping of the bit has on the syndrome. If the value Ar (x) is above the associated threshold, then the threshold, is lowered in Algorithm 2, as is the case in Algorithm 1.

Figure 3 shows a functional representation of the Turbo-ATBF algorithm as it may be implemented in hardware or software. Let c, and r be the maximum column and row weights, respectively. The number of check node processors 101 is equal tozand the syn function in block 104 is an update of all syndromes in which the bit participates.

Figure 3 represents one sub-iteration of the Turbo-ATBF algorithm.

Multiple sub-iterations, covering all rows of the parity check matrix, constitute a full iteration whereby all syndrome and bit values are updated.

Within thez rows, all bit nodes can be updated in parallel, as there is only a single non-zero value within each column across all of the z rows. However, update of a check node where multiple bits have changed sign necessitates recalculation of the syndrome. Alternatively, updates of all bit nodes in a given row may be done in a serial fashion with the corresponding syndrome being updated by a simple sign change when a bit changes sign.

Referring again to Figure 2, the parity check matrix shown in this figure is divided into D = 3 blocks of rows. The columns within each of the blocks have at most one non-zero value. This means that the parity checks within each of the rows of a block of rows cannot interfere with each other, allowing parallel processing of the rows within each block. It will be appreciated that the degree of parallelism achievable changes in accordance with the number of rows in each block of rows. In one extreme z may equal one, so that each row is processed individually. While the gains in processing speed are reduced in this case, the benefits gained from flipping bits before the next parity check involving the bit in question is performed are still attainable.

As discussed above, the known gradient descent inversion function, repeated above as equation (3), may be used to determine the desirability to flip particular bits. The embodiments are, however, not limited to the use of equation (3) and other methods of determining the desirability to flip a bit may be used instead. It will moreover be appreciated that while the above description relates to an embodiment where Z3, other values for Z are also envisaged. This includes embodiments where Z=1, that is embodiments in which he rows of the parity check matrix are operated upon in a fully sequential fashion.

Figure 4 compares the BER performance of the standard ATBF algorithm and the Turbo-ATBF algorithm. Figure 4 shows that the Turbo-ATBF algorithm provides almost identical BER performance with the ATBF algorithm, despite the reduced number of iterations (17% fewer iterations at an SNR of 6 dB) required. The Turbo-ATBF algorithm is useful in very high throughput LDPC decoding (multi-Gb/s) such as in WiGig and IEEE 802.llad standards.

Figure 5 shows the average number of iterations required by the two algorithms when the maximum number of iterations is limited to 100. As can be seen from this figure, for virtually the same error correcting performance the Turbo-ATBF algorithm uses fewer iterations than the ATBF algorithm. The gap between the two widens as the SNR increases.

By faster propagation of information in the decoding process the Turbo-ATBF algorithm uses fewer iterations to deliver the same error correcting performance as the ATBF algorithm when decoding layered LDPC codes.

Alternatively the number of iterations may be fixed for the Turbo-ATBF algorithm to deliver better error correcting performance when decoding layered LDPC codes.

The Turbo-ATBF method disclosed herein may be suitable for reducing the number of iterations required to decode an LDPC channel code using a bit flipping algorithm. Alternatively, the number of iterations may be held constant for an improvement in bit error rate, correcting performance over previously published bit flipping algorithms. The disclosed algorithm may offer further decoding gains when used with layered LDPC codes, i.e. codes constructed from sub-codes in a structured manner.

In the description above equation (3) provides Qne example of a gradient descent inversion function. It will be appreciated that equation (3) is merely an example that does not limit the present invention. Other functions may also find use and Wadayama, T. et al, "Gradient Descent Bit F!ipping Algorithms for Decoding LDPC Codes", Proc. International Symposium on information Theory and Its Applications ISITA 2008may provide guidance in this respect.

Figure 6 illustrates an apparatus 200 that can be used for putting the Turbo-ATPF method into effect. The apparatus 200 comprises a data input 210, a processor 220 and a data output 230. Further provided are a non-volatile memory 240 used for storing a software or firmware code that, when executed, configures the processor 220 to be operable in the above described manner. The memory 240 may further store the parity check matrix. A RAM 250 is provided for temporarily storing data, including newly received data and hard decision values, both as derived from newly received data and as modified by the processor when implementing the above described Turbo-ATBF algorithm.

While certain embodiments have been described, the embodiments have been presented by way of example only, an area not intended to limit the scope of the inventions. Indeed, the novel methods, apparatus and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (11)

1. CLAIMS: 1. An LDPC decoding method comprising performing consecutive first and second parity checks on hard decision data, the first and second parity checks based on different parts of a parity check matrix, wherein each of the parts of the parity check matrix comprises at most one non-zero value for each data point of the hard decision data and wherein the first and second parity checks are performed as part of one path of parity checks based on the parity check matrix; estimating, after having performed the first parity check and before performing the second parity check, a likelihood for each hard decision data bit for which the part of the parity check matrix used for the first parity check has a non-zero value, that the sign of the hard decision bit is incorrect; and inverting, before performing the second parity check, the sign of one or more hard decision bit for which the estimated likelihood is below a threshold value.
2. 2. A method according to Claim 1, wherein one or more of the parts of the matrix comprises more than one row of the matrix, wherein, as part of the first and/or the second parity checks, parity checks are performed in parallel for each row of the part.
3. 3. A method according to Claim 1 or 2, wherein a gradient descent inversion technique is used for determining the said likelihood.
4. 4. A method according to Claim 3, further comprising updating a syndrome: [f xe{+i,-i} JcN(i) used by the gradient descent inversion technique in determining said likelihood for each row of the parity check matrix involved in the first parity check before performing the second parity check, wherein N is the set of non-zero values in row i of the parity check matrix for which he syndrome is calculated, and x1 are the hard decision values at the non-zero positions of said row i of the parity check matrix.
5. 5. A method according to any preceding claims, further comprising, reducing a threshold value for one or more hard decision data points before performing the secondn parity check, wherein a decision on whether or not the sign of the hard decision data point is to be inverted following the second parity check is made based on the threshold value.
6. 6. An apparatus comprising a memory storing a parity check matrix, a first processor operable to, within one pass through a parity check matrix: perform, on hard decision data values data that are to be checked, a first parity check based on a first row of the parity check matrix; estimate a likelihood for each hard decision data bit affected by the first parity check that the sign of the hard decision bit is incorrect; invert the sign of one or more hard decision bit for which the determined likelihood is below a threshold value; and perform, on the hard decision data values, a second parity check based on a second row of the parity check matrix, only after said estimating and inverting, wherein the second row of the parity check matrix comprises at least one non-zero value for a hard decision bit for which the first row of the parity check matrix also comprises a non-zero value.
7. 7. An apparatus according to Claim 6, wherein the parity check matrix can be divided into a number of parts, each part comprising a plurality of rows, wherein each column in a said part comprises at most one non-zero value, the apparatus further comprising one or more further processors, each of said further processors arranged to perform a said first parity check, wherein the first processor and the one or more further processors are arranged to perform at least the said first parity checks substantially in parallel, wherein each processor is operable to use a different row of the part of the parity check matrix.
8. 8. An apparatus according to Claim 6 or 7, wherein the first processor and, if present, the one or more further processors are further operable to determine said likelihood based on a gradient descent inversion technique using a syndrome according to: fl xe{+i,-i} JeNQ) wherein is the set of non-zero values in row i of the parity check matrix for which the syndrome is to be calculated, and x1 are the hard decision values at the non-zerQ..positions of the row i of the parity check matrix; and wherein the first and, if present, the one or more further processors are further operable to update the syndrome before the second parity check is performed, if a hard decision value has been inverted following the first parity check.
9. 9. A receiver comprising an apparatus according to any of claims 6 to 8.
10. 10. A network comprising a receiver according to claim 9.
11. 11. A data storage device comprising an apparatus according to claims 6 to 8.