GB2486739A - Changing the operation of an instruction for a data processor using a prefix instruction - Google Patents
Changing the operation of an instruction for a data processor using a prefix instruction Download PDFInfo
- Publication number
- GB2486739A GB2486739A GB1021990.5A GB201021990A GB2486739A GB 2486739 A GB2486739 A GB 2486739A GB 201021990 A GB201021990 A GB 201021990A GB 2486739 A GB2486739 A GB 2486739A
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- GB
- United Kingdom
- Prior art keywords
- instruction
- operator
- prefix
- integral
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
Abstract
The instruction set for a processor has a prefix instruction, which changes the operation of the following instruction. The prefix instruction may also add a third operand to the two operands specified in the following instruction. The following instruction may be a move/add instruction when not preceded by the prefix and an add/subtract operation when preceded by the prefix. The prefix instruction may be identified by an indicator, such as a predetermined sequence of bits, in the instruction.
Description
t V.' INTELLECTUAL ..* PROPERTY OFFICE Application No. GB 1021990.5 RT1VI Date 4 April 2012 The following terms are registered trademarks and should be read as such wherever they occur in this document:
MIPS
Intellectual Properly Office is an operating name of the Patent Office www.ipo.gov.uk
INSTRUCTION EXECUTION
This disclosure relates generally to instruction set computing. In particular the disclosure relates to a method of executing an instruction set, and an execution processor for executing the instruction set.
Reduced instruction set computing (RISC) processors typically have a fixed bit-width instruction size. Common sizes are 16-bits and 32-bits. 32-bits give flexibility in expressing instructions and operands but at the expense of typically larger code size than the 16-bit instruction sets.
A problem with the short (16-bit) instruction sets is that they have a restricted number of bits for expressing operators. Some processors (for example those operating the reduced instruction set computer architecture MIPS) make use of prefixes. A prefix is an instruction which is associated with another instruction. A prefix contains the same number of bits as the instruction with which it is associated. For example, the MIPS architecture uses short instructions each having 16 bits. Both an MIPS prefix and the MIPS instruction with which it is associated have 16 bits.
Prefixes have been used to signify that a field in an instruction is to be interpreted as having the same meaning but in a different location in the instruction. In a simplified example, figure la illustrates an instruction in which field A is in location 1, field B is in location 2, field C is in location 3, and field D is in location 4 of an instruction. Figure lb illustrates a prefix which precedes the instruction of figure la and indicates that the fields in locations 1 and 3 of the instruction are to be interchanged. Figure lc illustrates the interpretation that the executing processor is left with of the instruction of figure la as a result of the prefix of figure lb. The operands in locations 1 and 3 have been interchanged. Now field C is in location 1, field B in location 2, field A in location 3, and field D in location 4. This example is a simplified illustration. In a real situation the prefix would be used to carry out other functions as well as indicating that the operands in locations 1 and 3 of the instruction are to be interchanged.
The example of figures la, lb and lc illustrates a change in the relative location of operators within the instruction. However, short 16-bit instructions are limited compared to long 32-bit instructions in that the number of operators available for use in the short instructions is significantly reduced compared to the number of operators available for use in the long S instructions due to the length of the instructions. The method illustrated in figures la, lb and lc does not increase the number of operators available for use in a short instruction.
There is therefore a need for a method of executing a reduced instruction set which increases the number of operators available for use in the instruction.
According to a first aspect, there is provided a method of executing an instruction set comprising a first instruction and a second instruction, the method comprising: reading the first instruction; determining whether the first instruction is integral with the second instruction; reading the second instruction; if the first instruction is integral with the second instruction, interpreting a first operator field of the second instruction to represent a first operator; and if the first instruction is not integral with the second instruction, interpreting the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.
Suitably, the method comprises determining that the first instruction is integral with the second instruction by identifying an indicator in the first instruction, Suitably, the indicator in the first instruction is a predetermined sequence of bits.
Optionally, the first operator is an Add/Sub operator, and the second operator is a Mov/Add operator.
Suitably the method further comprises if the first instruction is integral with the second instruction, interpreting the first operator field of the second instruction to require an additional operand. Suitably, the additional operand is not specified in the second instruction.
According to a second aspect, there is provided an execution processor arranged to execute an instruction set comprising a first instruction and a second instruction, the execution processor comprising: an instruction reader arranged to read the first instruction and the second instruction; a determination unit arranged to determine whether the first instruction S is integral with the second instruction; and an interpretation unit arranged to: if the first instruction is integral with the second instruction, interpret a first operator field of the second instruction to represent a first operator; and if the first instruction is not integral with the second instruction, interpret the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.
Suitably, the determination unit is arranged to determine that the first instruction is integral with the second instruction by identifying an indicator in the first instruction.
Suitably, the indicator in the first instruction is a predetermined sequence of bits.
Optionally, the first operator is an Add/Sub operator, and the second operator is a Mov/Add operator.
Suitably, the interpretation unit is further arranged to, if the first instruction is integral with the second instruction, interpret the first operator field of the second instruction to require an additional operand. Suitably, the additional operand is not specified in the second instruction.
The following disclosure will now be described by way of example with reference to the accompanying drawings. In the drawings: figure la illustrates an instruction; figure lb illustrates a prefix; figure lc illustrates the interpretation of the instruction of figure la when preceded by the prefix of figure lb; and figure 2 is a flow diagram illustrating the method by which a processor executes an instruction set according to the protocol described herein.
Known reduced instruction sets use short instructions, generally having 16 bits. These instructions can be grouped into three classes: 1) short instructions which are prefixes; 2) short instructions which are not prefixes but which are associated with one or more short instructions which are prefixes; and 3) short instructions which are isolated full instructions.
From hereon instructions which are not prefixes but which are associated with one or more instructions which are prefixes (group 2 above) will be called main instructions.
Known reduced instruction sets which use prefixes do so to extend an operand or operator of the main instruction with which the prefix is associated. The following discussion describes a reduced instruction set which enables a prefix to increase the number of operators which can be expressed by an instruction. By increasing the set of available operators which can be expressed by an instruction, complex instructions can be expressed in fewer individual instructions. The efficiency of the overall instruction set is thereby increased.
Reduced instruction sets typically have 16-bit long instructions, however it is to be understood that the disclosure extends to instructions having any number of bits.
The flow diagram of figure 2 illustrates a sequence of steps. It is to be understood that not all the steps in this figure are necessarily required, and that some of the steps may be performed in a different order to that depicted. For example, the first instruction may be read by the execution processor prior to the execution processor reading the second instruction. Alternatively, the second instruction may be read by the execution processor prior to the execution processor reading the first instruction, Figure 2 illustrates the method by which a processor executes some instructions in the instruction set. In this example, the instruction set comprises a first instruction and a second instruction. The second instruction is a main instruction. The first instruction is either (i) a prefix associated with the second instruction, or (ii) another instruction unrelated
S
to the second instruction, lithe first instruction is a prefix to the second instruction then the second instruction is interpreted as having one meaning. If the first instruction is not a prefix to the second instruction then the second instruction is interpreted as having a different meaning. In this latter situation, the first instruction is unrelated to the second S instruction, and is processed by the execution processor accordingly.
Referring to figure 2, at step 200 the processor reads the first instruction. At step 202, the processor determines whether the first instruction is a prefix of a second instruction. If the answer to this determination is YES, that the first instruction is a prefix of a second instruction, then the method follows through to step 204 where the second instruction is read. Then, at step 206, the processor interprets a first operator field in the second instruction to represent a first operator. If the answer to the determination of step 202 is NO, that the first instruction is not a prefix of a second instruction, then the method follows through to step 208 where the second instruction is read, Then, at step 210, the processor interprets the first operator field of the second instruction to represent a second operator.
The first operator is different to the second operator. The first instruction is not a prefix of the second instruction. The first instruction is therefore processed by the execution processor as usual, i.e. in accordance with known methods.
Suitably, the processor interprets the remainder of the second instruction independently of the prefix. In other words, the processor interprets the remainder of the second instruction as it would have done had the second instruction not been accompanied by a prefix.
As discussed above, a prefix is an instruction which is associated with another instruction.
Generally, a prefix is integral with another instruction. A prefix may be an instruction which forms a part of another instruction. A prefix may take one of many forms, For example, a prefix may include bits which are to be incorporated into the bits of another instruction. A prefix may include bits which are interpreted by an executing processor as altering the meaning of another instruction.
Suitably, the processor determines if the first instruction is a prefix of the second instruction by searching for an identifier in the first instruction. For example, the prefix may include a sequence of bits which are identifiable by the processor as indicating that the instruction is a prefix. In an example instruction set comprising 16-bit long instructions, the identifier of a prefix constitutes the first 4 bits of the prefix. These first 4 bits are 1111. In a different exam pie instruction set the identifier of a prefix could constitute a different number and/or S different location of bits in the prefix.
Example
Consider a first operator field comprising a bit or a bit sequence in an instruction. In isolation the bit or bit sequence is interpreted by an example execution processor to represent a "Mov/Add" operator. The "Mov/Add" operator selects between the two instructions: RegC = RegA (equation 1) RegC = RegC + RegA (equation 2) Equation 1 is a Mov operation in which the contents of register A are shifted to register C. Equation 2 is an Add operation in which the contents of register A are added to those of register C and the result stored in register C. The presence of a prefix associated with the instruction changes the interpretation held by the execution processor of the first operator field. Instead of interpreting the bit or bit sequence as a "Mov/Add" operator, the execution processor interprets the bit or bit sequence as an "Add/Sub" operator. The "Add/Sub" operator selects between the two instructions: RegC=RegA+RegB (equation 3) RegC=RegA-RegB (equation 4) Equation 3 is an Add operation in which the contents of register A are added to those of register B and the result stored in register C. Equation 4 is a Sub operation in which the contents of register B are subtracted from the contents of register A and stored in register C. In terms of the method described with respect to figure 2, in this example a first instruction is read at step 200, If it is determined at step 202 that this first instruction is not a prefix of a second instruction, then the second instruction is read at step 208. The bit or bit sequence of the first operator field of the second instruction is interpreted by the execution processor in its isolated form, i.e. as a "Mov/Add" operator. Alternatively, if it is determined at step 202 that the first instruction is a prefix of the second instruction, then when the second instruction is read, the bit or bit sequence of the first operator field is interpreted by the execution processor to be an "Add/Sub" operator.
The presence of the prefix (first instruction) changes the execution processor's interpretation of a bit or bit sequence in the main instruction (second instruction) representing an operator.
The presence of a prefix associated with a main instruction may also introduce a further operand into the main instruction. Alternatively, the presence of the prefix associated with a main instruction may introduce a plurality of further operands into the main instruction.
For example, in the described example above the presence of the prefix changes the meaning of an operator field from meaning a "Mov/Add" operator to an "Add/Sub" operator. The "Mov/Add" operator requires two registers: register A and register C. The "Add/Sub" operator requires three registers: register A, register B, and register C. The presence of the prefix has therefore introduced a further operand, the register B, into the main instruction. This further operand may be specified in the main instruction.
Alternatively, this further operand may not be specified in the main instruction.
Suitably, the presence of the prefix associated with the main instruction is interpreted by the execution processor as indicating that each of a plurality of operator fields in the main instruction is to be interpreted as representing a different operator to the operator that that operator field would be interpreted as representing in isolation. In this case, suitably the processor interprets the remainder of the main instruction as it would have done had the main instruction not been accompanied by a prefix.
Optionally, the method of figure 2 may be extended such that the interpretation of the bits of a first operator field in the second instruction is dependent not only on whether the first instruction is a prefix of the second instruction but also on the specific bit sequence of all or part of the prefix. For example, a first bit or sequence of bits in the prefix may be interpreted by the execution processor to mean that the first operator field represents one operator, whereas a second bit or sequence of bits in the prefix may be interpreted by the execution processor to mean that the first operator field represents another operator.
The specific bit sequence of the prefix may be interpreted by the execution processor as specifying which operator field of the second instruction is to be interpreted as representing a different operator to the operator it represents in isolation. For example, a first bit sequence of the prefix may be interpreted as indicating that a first operator field represents operator X (rather than the operator V it represents in isolation); and a second bit sequence of the prefix may be interpreted as indicating that a second operator field represents operator S (rather than the operator T it represents in isolation). Operators X and S may be the same. Operators X and S may be different. Operators V and T may be the same.
Operators V and T may be different.
Optionally, the method of figure 2 may be extended such that the location of a specific bit sequence in the prefix is interpreted by the execution processor as specifying which operator field of the second instruction is to be interpreted as representing a different operator to the operator it represents in isolation. For example, a specific bit sequence located in one position in the prefix may be interpreted as indicating that a first operator field represents operator X (rather than the operator V it represents in isolation); and the specific bit sequence located in a second position in the prefix may be interpreted as indicating that a second operator field represents operator S (rather than the operator T it represents in isolation). Operators X and S may be the same. Operators X and S may be different. Operators V and T may be the same, Operators V and T may be different.
This disclosure also relates to an execution processor which is arranged to execute an instruction set which is formed according to the protocol described herein. The execution processor is arranged to perform the method of figure 2. The execution processor comprises an instruction reader arranged to read instructions, a determination unit arranged to determine whether one instruction is a prefix of a main instruction, and an interpretation unit arranged to interpret the operator fields of the main instruction according to a protocol in which at least one operator field represents a different operator depending on the presence of an associated prefix.
Preferably, the execution processor is implemented in hardware. Optionally, the execution processor is implemented in software.
The methods and apparatus described herein operate according to a protocol in which the bit or bits of an operator field of an instruction is/are to be interpreted by the executing processor as having one significance when that instruction is not accompanied by a prefix and another significance when that instruction is accompanied by a prefix. In particular, an operator field is interpreted as representing one operator when there is no accompanying prefix, and as representing another operator when there is a prefix. For a given operator location in a main instruction, the prefix changes the interpretation of the bits at that location from a first interpretation (which is the interpretation those bits have in isolation) to a second interpretation.
These methods and apparatus are more efficient than the prior art discussed because they increase the number of available operators for use in each instruction. By increasing the set of available operators which can be expressed by an instruction, complex instructions can be expressed in fewer individual instructions. The efficiency of the overall instruction set is thereby increased.
The applicant draws attention to the fact that the present invention may include any feature or combination of features disclosed herein either implicitly or explicitly or any generalisation thereof, without limitation to the scope of any of the present claims. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.
Claims (12)
- CLAI MS1. A method of executing an instruction set comprising a first instruction and a second instruction, the method comprising: reading the first instruction; determining whether the first instruction is integral with the second instruction; reading the second instruction; if the first instruction is integral with the second instruction, interpreting a first operator field of the second instruction to represent a first operator; and if the first instruction is not integral with the second instruction, interpreting the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.
- 2. A method as claimed in claim 1, comprising determining that the first instruction is integral with the second instruction by identifying an indicator in the first instruction.
- 3. A method as claimed in claim 2, wherein the indicator in the first instruction is a predetermined sequence of bits.
- 4. A method as claimed in any preceding claim, wherein the first operator is an Add/Sub operator, and the second operator is a Mov/Add operator.
- 5. A method as claimed in any preceding claim, further comprising if the first instruction is integral with the second instruction, interpreting the first operator field of the second instruction to require an additional operand.
- 6. A method as claimed in claim 5, wherein the additional operand is not specified in the second instruction.
- 7. An execution processor arranged to execute an instruction set comprising a first instruction and a second instruction, the execution processor comprising: an instruction reader arranged to read the first instruction and the second instruction; a determination unit arranged to determine whether the first instruction is integral with the second instruction; and an interpretation unit arranged to: if the first instruction is integral with the second instruction, interpret a first operator field of the second instruction to represent a first operator; and if the first instruction is not integral with the second instruction, interpret the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.
- 8. An execution processor as claimed in claim 7, wherein the determination unit is arranged to determine that the first instruction is integral with the second instruction by identifying an indicator in the first instruction.
- 9. An execution processor as claimed in claim 8, wherein the indicator in the first instruction is a predetermined sequence of bits,
- 10. An execution processor as claimed in any of claims 7 to 9, wherein the first operator is an Add/Sub operator, and the second operator is a Mov/Add operator.
- 11. An execution processor as claimed in any of claims 7 to 10, wherein the interpretation unit is further arranged to, if the first instruction is integral with the second instruction, interpret the first operator field of the second instruction to require an additional operand.
- 12. An execution processor as claimed in claim 11, wherein the additional operand is not specified in the second instruction.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1021990.5A GB2486739B (en) | 2010-12-24 | 2010-12-24 | Instruction execution |
| US13/333,939 US9164768B2 (en) | 2010-12-24 | 2011-12-21 | Executing an instruction set using a prefix to interpret an operator field as either a first or a second operator field |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1021990.5A GB2486739B (en) | 2010-12-24 | 2010-12-24 | Instruction execution |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB201021990D0 GB201021990D0 (en) | 2011-02-02 |
| GB2486739A true GB2486739A (en) | 2012-06-27 |
| GB2486739B GB2486739B (en) | 2018-09-19 |
Family
ID=43599013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1021990.5A Expired - Fee Related GB2486739B (en) | 2010-12-24 | 2010-12-24 | Instruction execution |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9164768B2 (en) |
| GB (1) | GB2486739B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5303358A (en) * | 1990-01-26 | 1994-04-12 | Apple Computer, Inc. | Prefix instruction for modification of a subsequent instruction |
| JP2000284962A (en) * | 1999-03-31 | 2000-10-13 | Seiko Epson Corp | Microcomputer |
| US6970998B1 (en) * | 2002-02-22 | 2005-11-29 | Redback Networks Inc. | Decoding suffix instruction specifying replacement destination for primary instruction |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3657705A (en) * | 1969-11-12 | 1972-04-18 | Honeywell Inc | Instruction translation control with extended address prefix decoding |
| US5845102A (en) * | 1997-03-03 | 1998-12-01 | Advanced Micro Devices, Inc. | Determining microcode entry points and prefix bytes using a parallel logic technique |
| US6185670B1 (en) * | 1998-10-12 | 2001-02-06 | Intel Corporation | System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields |
| US6981132B2 (en) * | 2000-08-09 | 2005-12-27 | Advanced Micro Devices, Inc. | Uniform register addressing using prefix byte |
| US6651160B1 (en) | 2000-09-01 | 2003-11-18 | Mips Technologies, Inc. | Register set extension for compressed instruction set |
| US7529912B2 (en) * | 2002-02-12 | 2009-05-05 | Via Technologies, Inc. | Apparatus and method for instruction-level specification of floating point format |
| US6957321B2 (en) * | 2002-06-19 | 2005-10-18 | Intel Corporation | Instruction set extension using operand bearing NOP instructions |
| EP1387256B1 (en) * | 2002-07-31 | 2018-11-21 | Texas Instruments Incorporated | Program counter adjustment based on the detection of an instruction prefix |
| US20090089564A1 (en) * | 2006-12-06 | 2009-04-02 | Brickell Ernie F | Protecting a Branch Instruction from Side Channel Vulnerabilities |
| JP5193624B2 (en) * | 2008-02-19 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | Data processor |
| JP5481793B2 (en) * | 2008-03-21 | 2014-04-23 | 富士通株式会社 | Arithmetic processing device and method of controlling the same |
| JP5357475B2 (en) * | 2008-09-09 | 2013-12-04 | ルネサスエレクトロニクス株式会社 | Data processor |
-
2010
- 2010-12-24 GB GB1021990.5A patent/GB2486739B/en not_active Expired - Fee Related
-
2011
- 2011-12-21 US US13/333,939 patent/US9164768B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5303358A (en) * | 1990-01-26 | 1994-04-12 | Apple Computer, Inc. | Prefix instruction for modification of a subsequent instruction |
| JP2000284962A (en) * | 1999-03-31 | 2000-10-13 | Seiko Epson Corp | Microcomputer |
| US6970998B1 (en) * | 2002-02-22 | 2005-11-29 | Redback Networks Inc. | Decoding suffix instruction specifying replacement destination for primary instruction |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2486739B (en) | 2018-09-19 |
| US9164768B2 (en) | 2015-10-20 |
| GB201021990D0 (en) | 2011-02-02 |
| US20120331274A1 (en) | 2012-12-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20191224 |