GB2484010A - DC-DC converter circuit using four switches - Google Patents

Abstract

A DC-DC converter circuit comprising a switch network for converting a voltage input terminal, inductor terminal and first and second output terminal wherein the switch network is arranged such that four switches of the network can be operated in use to generate a positive output voltage at the first output terminal and a negative output voltage at the second output terminal. The invention is of particular use in an audio amplifier.

Description

DC-DC CONVERTER CIRCUITS, AND

METHODS AND APPARATUS INCLUDING SUCH CIRCUITS

The invention relates to DC-DC converter circuits, in particular circuits for generating a split rail (dual polarity) supply from a single input voltage supply.

The invention further relates to integrated circuits for use in making such DC-DC converters and methods of operation thereof, and apparatus such as audio amplifiers including such circuits along with functional circuitry.

Modern electronic apparatuses integrate a wider range of functions, such as display, audio, digital and analogue signal processing functions. Each of these functions has its own requirements for voltage supplies, which are met with high efficiency by modern switched mode voltage converters of DC-DC and even AC-DC type. These converters use a combination of inductors, capacitors and networks of switches controlled in a predetermined sequence to translate freely between higher and lower supply voltages.

In modern times, there is a need to generate different supply voltages from those available, to suit different parts of a complex apparatus which may be highly portable, powered either by batteries or through combined signal/power interfaces (USB devices for example). In order to achieve small size and low cost, the power converter functions should be integrated with functional circuitry, and the number and size of external components such as inductors and capacitors should be minimized.

A particular requirement in such applications is for a split rail (bipolar) supply to be generated from a single rail supply. This is easily done with two separate inductors, but to achieve it with one inductor is clearly desirable for reasons of space, cost and pin-out. A DC-DC converter design called a buck-flyback' converter has been proposed which can generate split supply from a single supply using a single inductor. However, in the known design, the voltages experienced by one of the switches are higher than those of other devices in the circuit, so that the known design cannot be integrated with the larger signal processing functions without impacting on process selection, circuit reliability and cost.

The invention aims to enable the provision of multi-output DC-DC conversion functions in a manner which can be integrated more readily with general circuit functions.

The invention in a first aspect provides a DC-DC converter circuit comprising a switch network for connecting a voltage input terminal, inductor terminals and first and second output terminals, wherein said switch network is arranged such that four switches of said network can be operated, in use, to generate a positive output voltage at said first output terminal and a negative output voltage at said second output terminal.

Applications of the DC-DC converter are varied. The invention for example also provides audio apparatus including a DC-DC converter circuit according to the invention set forth above and audio output circuitry connected to be powered by the first and second output voltages of said converter.

The audio apparatus may be portable.

The audio apparatus may be an in-car audio apparatus, a headphone or a stereo headphone apparatus or a communications apparatus such as a mobile phone or PDA.

The audio apparatus may further include an audio output transducer, such as a speaker, connected as a load connected to an output terminal of output amplifier apparatus connected to be powered by said DC-DC converter.

These and other features and advantages of the invention in its various embodiments will be understood from a consideration of the detailed

description which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example only, by reference to the accompanying drawings, in which: Figure Ia and lb show in block schematic form two amplifier circuits in which the DC-DC converters embodying the present invention may be used; Figure 2 shows a known buck-flyback type of DC-DC converter circuit comprising an inductor, two capacitors and a number of switches; Figures 3a -3f illustrate the configuration of the switches in the circuit of Figure 2 during successive phases in the generation of a bipolar voltage supply; Figure 4 shows a novel DC-DC converter circuit according to a first embodiment of the invention; Figures 5a to Sf illustrate the configuration of the switches in the circuit of Figure 4 during successive phases A-F in the generation of a bipolar voltage supply; Figure 6 shows waveforms present in the circuit of Figure 4 in operation; Figures 7a and 7b show in more detail a control circuit suitable for use in the converter of Figure 4; Figure 8 is a state transition diagram implemented by the control circuit of Figure Ta; Figure 9 is a state transition diagram implemented in a second embodiment of the invention, having the same configuration as Figure 4 but a different control circuit; Figure 10 shows in more detail a modified control circuit used in the second embodiment of the invention; Figure 11 shows waveforms present in a third embodiment of the invention, based on further modification of the Figures 9 and 10 embodiment; and Figure 12 shows waveforms present in a fourth embodiment of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Background -DC-DC Converter Applications

Figure Ia represents a typical application wherein dual rail supply voltages V2+ and V2-are generated by a DC-DC converter 10, the converter 10 being supplied from a single rail supply voltage Vi. Labels Vi, V2+ etc. are be used in this description to refer to either the respective terminals or the voltage at that terminal, according to context.

The supply voltage Vi is illustrated as supplying processing circuitry 20. The input signal Si maybe an analogue signal or a digital signal. In the case where Si is an analogue signal then the processing circuitry 20 will be purely analogue type circuitry such as op-amps, multiplexers, gain blocks etc. In the case where Si is a digital signal and the output stage is analogue, then the processing circuitry 20 may be a mixture of digital and analogue circuitry where signal Si is fed, either directly or through some digital signal processing, into a DAC (not illustrated) and the output of the DAC is then fed into the analogue circuitry as mentioned above.

The processing circuitry 20 outputs a processed signal S2 that in this particular embodiment is passed into a level shifter 30 that may be implemented by a DC-blocking capacitor for example. An output amplifier 40 is powered by the dual rail supply voltages V2+ and V2-generated by the DC-DC converter 10. The input signal Si, if analogue, and analogue signals in the processing circuitry 20 will normally be referenced midway between ground potential and VI, whereas the level shifted signal S2' is referenced to ground, as required by the output amplifier operating from the split rail supply V2-'-, V2-.

The level shifted signal S2' is fed into the output amplifier 40 which outputs an amplified output signal S3 which is fed into a ground referenced load in the form of signal transducer 50. In the case where the output amplifier 40 is a switching (class D or PWM) amplifier, or a 1-bit digital (sigma-delta) type output stage, the signals SI, S2 may be digital in form right through to input to output, or may begin in analogue form and be converted to digital form in the processing circuit 20.

Figure lb illustrates a more specific application of the arrangement of Figure Ia; the DC-DC converter 10 and supply connections have been omitted for clarity. The application in this example is a stereo amplifier in which the load is a stereo headphone 51. The signal processing elements of the amplifier are duplicated to process left and right channel signal, as indicated by the suffixes L' and R' on their reference signs. The supplies can be shared by both channels, although independent supplies for different channels would be possible if the application demands it. One area of application is in portable audio apparatus such as MP3 players for example where the split rail supply allows a DC-coupled output, which is desirable to maintain the bass response without having to use large decoupling capacitors.

Other possible application areas where the ability to generate a split rail supplies include (I) voltage supplies for circuits handling analogue composite video signals, where a ground-referenced DC-coupled output signal can avoid black-level droop; and (2) line drivers for data links or modems such as ADSL where a ground-referenced dc coupled output signal can reduce baseline wander effects.

For cost and size reasons, it is important to be able to integrate the functions of an MP3 player, mobile phone or any other application into a small number of integrated circuits. Therefore it is advantageous to integrate the circuitry for supply voltage generation, in this case the DC-DC converter 10, together with the functional circuitry 20, 30, 40 etc.. Generally speaking, the converter 10 includes an inductor which cannot realistically be integrated and has to be located off-chip, with consequences for chip-pin-count and overall circuit size.

Since many circuits require supplies of dual polarity (split rail supplies), this has prompted the development of voltage generation circuits that are capable of generating two (or more) output voltage supplies using a single inductor, rather than an inductor per required output voltage.

Figure 2 shows the structure of a known DC-DC converter circuit, capable of receiving a voltage supply at voltage Vi (relative to ground) and generating positive and negative supplies V2+ and V2-using a single inductor. DC-DC converter topologies are generally classified into types such as buck', boost', buck-boost' and so forth; the circuit shown in Figure 2 has been referred to in the literature as one form of buck-flyback' converter.

The circuit comprises a network of five switches SI to 55 connecting the input and output terminals Vi, V2-'-, V2-and a common ground GND. The circuit includes just one inductor L, with nodes labelled X and Y at either end. As mentioned above, the inductor will be located off-chip, in which case nodes X and Y correspond to pins of the integrated circuit on which the DC-DC converter is made. Each output has a reservoir capacitor, Ci for the positive or high side' output terminal V2+, and C2 for the negative or low side output terminal V2-. The capacitors are generally off-chip too, the outputs V2+, V2-and GND also corresponding to external pins of the chip.

Switch SI when closed connects input terminal Vito node X. Similarly: switch S2 connects node X to ground; switch S3 connects node X to low side output terminal V2-; switch S4 connects node Y to high side output terminal V2+; and switch S5 connects node Y to ground. Each switch Si to S5 is controlled by a respective switch control signal CS1-C55 and these control signals are generated by a controller 60 which activates the switches in predetermined sequences in response to sensing signals together with common signals such as a clock, start-up and shut-down. In an integrated circuit embodiment (or indeed for discrete embodiments) the switches SI to S5 will generally be implemented using MOS transistors. Current-sensing features may be associated with some or all of the switches to provide feedback to the controller. These are all omitted from the drawing for clarity.

The operation of the known Buck-Flyback DC-DC converter 10 of Figure 2 will now be described with reference to Figures 3a to 3f which show the states of the switches in six key phases of operation. The controller cycles the circuit through these phases at a frequency far higher than the audio frequency, so that variations in the output supply voltages are minim ised and noise is outside the band of interest in the audio or other application. More detail of the form and operation of the controller will be given in relation to the novel circuit of Figure 4.

A complete cycle of operation of the converter includes a first type of sub-cycle in which the inductor L supplies current to generate the positive output voltage V2+ and a second type of sub-cycle in which it is used to supply current to generate the negative output voltage V2-. The voltages V2+ and V2-in this example are nominally equal in magnitude and less than Vi. In between these sub-cycles the inductor current returns to zero, as in the "discontinuous mode" of operation of a standard buck type converter.

The first type of sub-cycle includes three phases A to C which correspond to the circuit states shown in Figures 3a to 3c respectively. It should be noted that, for reasons of clarity, the controller 60, all sensing signals and control signals CS1 to CS5 illustrated in Figure 2 have purposely been omitted from Figures3ato3f.

Phase A -(Figure 3a): In the first phase switches Si and S4 are closed.

Initially the inductor current is zero. The inductor L has Vi -(V2+) applied across it so that a current IL through the inductor L builds up and starts to charge up the reservoir capacitor Ci (ICi) despite the demand for load current (ILOAD-'-) demand simultaneously pulling charge out of capacitor Ci and into the high side load (not illustrated) and through the load to ground.

Phase B (Figure 3b): In the next phase, SI is opened and S2 closed, while S4 remains closed. Current IL in the inductor L continues flowing (this is the defining characteristic of an inductor), continuing to charge up capacitor CI, as well as supplying load current ILOAD-'-. However, inductor L now has a voltage of V2+ applied across it which is the opposite polarity to that in Phase A. Thus current IL ramps down, eventually to zero.

Phase C (Figure 3c): In order to avoid pulling charge back out of capacitor Cl and so reducing efficiency, switch S4 is opened when the inductor current IL reaches zero. Switch S2 remains closed. Furthermore, it is preferable to short the nodes X and Y of the inductor L somehow at this point, in order to avoid voltage oscillations due to any residual current in the inductor. This can be done conveniently by closing switch S5 as shown.

With the first sub-cycle finished and the inductor current returned to zero, there can now follow the second type of sub-cycle in which inductor L is used to charge the negative rail capacitor C2.

The second type of sub-cycle comprises three phases D, E and F. The states of switches Si to S5 and the resulting current flow to generate the negative voltage V2-in these three phases are shown in Figures 3d to 3f respectively.

Again, for reasons of clarity, controller 60, various sensing signals and control signals CSI to C55 are omitted from Figures 3d to 3f.

Phase 0 (Figure 3d): Switches SI and S5 are closed, Initially the inductor current is zero, but, now that the inductor L has VI applied across it, current IL builds up, just as it did in Phase A of the first type of sub-cycle (Figure 3a).

Meanwhile the low side load (not shown) draws current ILOAD-to ground, and so simultaneously pulls charge out of the reservoir capacitor C2.

Phase E (Figure 3e): After a time, switch SI is opened and switch S3 closed.

Switch S5 remains closed. Inductor current IL continues flowing, charging up the reservoir capacitor C2, as well as supplying the low side load current ILOAD-. The inductor L has a voltage V2-applied across it, in opposite polarity to the previous phase, and so current IL will ramp down eventually to zero.

Phase F (Figure 3f): When inductor current IL reaches zero, switch S3 is opened in order to avoid pulling charge back out of the capacitor C2, which would reduce efficiency. Switch S5 remains closed. Furthermore, in order to avoid voltage oscillations due to any residual current IL in the inductor L, switch S2 is preferably closed as shown, so as to short the terminals of the inductor L. By cycling through these six phases A to F, as illustrated in Figures 3a to 3f, capacitors Cl and C2 can be recharged alternately, thus generating dual rail, positive and negative, voltages using a single inductor.

Generally the output voltages from V2+N2-will be fed back and compared to respective target voltages. The resulting error signals are used to derive the appropriate duty-cycles, that is the on times, of the two charging phases to provide the current required to minimise these errors. Detail of this control function in the known circuit is not material to the present description. More detail will be provided in relation to control of the novel DC-DC converter circuits described below.

Now, as mentioned above, the switches Si to S5 will be realised in the form of MOS transistors. On an integrated circuit in particular, these transistors will have maximum voltage rating both for long term reliability and to prevent immediate damage. A standard mixed-signal process with 0.i8um minimum feature size may for example have two types of MOS transistors that are rated at 1.8 volts and 5 volts respectively, typical of operating voltage. Allowing 10% tolerance for variations in supply voltage, this would allow for circuitry to operate reliably from a 5.5 v supply voltage.

In such circumstances, it can be difficult, or at any rate costly, to integrate the circuit of Figure 2, because of the peak voltage stress across switch S3.

Specifically, in Phase D of operation of the known circuit (Figure 3d), one side of switch S3 is connected (directly) to the negative output V2-while the other side of S3 is connected to node X which, in Phase D, is at the input supply voltage Vi. Also, in Phase E (Figure 3e), one side of switch Si is connected to VI, whereas the other side of SI is connected to node X which in Phase E is at the low-side output voltage.

The peak voltage stress across S3 or Si is given by: Vi -(V2-) iS Assume that the semiconductor process is a standard mixed signal process for example: 0.i8um with l.8V and 5V transistors and that Vi = 5.5V and V2 = -1.5V. Therefore, the peak stress across S3 or S1 will be: 5.SV-(-i.5V)= 7V For the example process, a peak stress voltage of 7V is significantly above the 5.5v maximum dictated by long term reliability constraints, and indeed uncomfortably close to the minimum potential level of 8v for the breakdown voltage (BVdSS) of the transistors. Immediate transistor breakdown may well be possible when factoring in transient overshoots which will occur when switching the inductor L, or at best the transistor may wear out prematurely due to this extra repetitive stress due to these overshoots. Any such transistor breakdown will normally lead to immediate destruction of the transistors and hence circuit and system failure, which is clearly undesirable.

Semiconductor processes do exist that include additional processing steps that allow the fabrication of transistor structures that are capable of supporting higher breakdown voltages. However, such processes, because of the extra processing steps, are inherently more expensive per wafer. Also, such processes are less widely available than, for example, the above disclosed 1.8V/5V mixed signal process and similar such processes. The electrical characteristics and layout rules of the higher voltage transistors are less standard making it hard to transport circuit designs from one silicon foundry to another. Furthermore, the physical size of the transistors increases with an increase in the breakdown voltages, thus adding to the die area, reducing dice per wafer, increasing packaging requirements and so forth.

Novel DC-DC Converter Figure 4 shows the structure of a novel DC-DC converter circuit 400 for generating bipolar supplies using a single inductor by a topology and phase sequence that overcomes the problem associated with the known buck-flyback converter, namely the stressing of one or more switches.

In the Figure 4 circuit and this description thereof, similar conventions are used as in the description of the known circuit (Figures 2 and 3a-3f) above, and like reference signs are used for ease of reference. As in the known circuit, we see input and output terminals Vi, V2-'-and V2-and a ground terminal (OND), an (off-chip) inductor L coupled to nodes X and Y and capacitors Cl and C2 storing charge for the high side and low side outputs respectively.

The switch network in the novel circuit 400 has four main switches instead of the five of the known circuit. These are labelled SI, S2, S4 and S6, to avoid confusion with switches playing different roles in the known circuits. The network is connected as follows: switch Si when closed connects input terminal Vi to node X; switch S2 connects node X to ground; switch S4 connects node Y to high side output terminal V2+; and switch S6 connects node Y to the low side output terminal V2-. An additional switch may optionally be provided, at either position S7a or 57b, as shown dotted in Figure 4. Each switch is controlled by a respective switch control signal CS1, CS2, CS4, CS6, CS7 and these control signals are generated by a controller 460 which activates the switches in predetermined sequences in response to sensing signals together with common signals such as a clock, start-up and shut-down.

Controller 460 is naturally a modified version of controller 60 in the known circuit, and will be described in more detail after the basic operating sequence of the novel circuit has been described with reference to Figures 5a to Sf.

In an integrated circuit embodiment (or indeed for discrete embodiments) the switches Si etc. may again be implemented using MOS transistors. Current-sensing features are associated with some or all of the switches to provide feedback to the controller. These are all omitted from the drawing for clarity.

With reference to Figures 5a to Sf and Figure 6, operation of this DC-DC iS converter 400 again occurs in two types of sub-cycles, comprising phases A-B-C and D-E-F respectively. As before, the first sub-cycle A-B-C uses inductor L to supply current IL to charge high side output capacitor Cl to generate a positive output voltage V2+ (less than Vi). In contrast, however, the second sub-cycle D-E-F uses inductor L to take charge not from input VI but from high side capacitor Ci, transferring it from there to capacitor C2 to generate a negative output voltage V2-.

Figure 6 shows operational waveforms associated with the phases A to F (Figures 5a to Sf respectively) in the novel converter. The skilled reader will appreciate that the waveforms shown in these diagrams are illustrative only and not intended to show the scale of variations or their detailed form. The cyclic variations shown in the output voltages V2+ and V2-in particular are greatly exaggerated here, for the sake of explanation, compared with what would be expected in a high quality audio application, for example.

In more detail, the first type of sub-cycle includes three phases A to C which correspond to the circuit states shown in Figures 5a to Sc respectively. It should be noted that, for reasons of clarity, the controller 460, all sensing signals and control signals CS1 to 057 illustrated in Figure 4 have purposely been omitted from Figures 5a to Sf. It should be further noted that the "Phases" referred to in Figures 5a -Sf corresponds to the Phases A -F respectively of the respective waveforms illustrated in Figure 6 and described in more detail below.

Phase A (Figure 5a): In the first phase of operation, switches Si and S4 are closed as shown in Figure 5A. Inductor current IL is initially zero but now the inductor L has Vi -(V2+) applied across it so current IL builds up, and increases charge on the high side reservoir capacitor Cl, despite the high side load (not illustrated) simultaneously drawing current ILOAD-'-out of this capacitor Cl and sinking it to ground GND.

Phase B (Figure 5b): After a time, when the inductor current IL has reached the level lmax+ shown in Figure 6, switch Slis opened and switch S2 closed while switch S4 remains closed. The current IL in the inductor L continues flowing, charging up the reservoir capacitor Ci, as well as supplying the high side current ILOAD-'-. As the inductor L has now has a voltage V2+ applied across it, in opposite polarity to the previous phase, current IL will ramp down, eventually to zero.

Phase C (Figure 5c): When the inductor current IL reaches zero, switch S4 is opened to avoid pulling charge back out of the capacitor Cl, which would impair efficiency. Furthermore, in order to avoid voltage oscillations due to any residual current in the inductor L, the additional switch S7a is turned on in series with switch S2 to short the inductor L. Alternatively, a switch 57b may be used to short the inductor terminals X and Y directly.

With the inductor current returned to zero, the controller can bring the circuit into the second sub-cycle which comprises three phases D, E and F. The states of switches SI to Sb and the resulting current flow to generate the negative voltage V2-in these three phases are shown in Figures Sd to Sf respectively. While the operation of the circuit in the first sub-cycle three phases has been substantially identical to that of the known converter, the structure and operating sequence of the second sub-cycle are very different.

Again, for reasons of clarity, controller 60, various sensing signals and control signals 051 to 04, 086, and CS7 are omitted from Figures Sd to Sf.

Phase D (Figure 5d): In the first phase of the second sub-cycle, switches 82 and S4 are closed, while switches Si and S6 are open. Initially the inductor current IL is zero, But inductor L now has voltage V2-'-applied across it so current IL builds up, but in the opposite polarity to the previous sub-cycle.

Consequently, rather than drawing the current from the input supply at Vi, this current IL is drawn from the high side reservoir capacitor Ci. Meanwhile the low side load feeds current ILOAD-into the low side of the reservoir capacitor iS 02, tending to make V2-less negative (this may be understood more easily as the load drawing a current -ILOAD-from the capacitor V2-).

Phase E (Figure 5e): After a time, when the inductor current IL has reached its maximum level (Imax-shown in Figure 6), switch S4 is opened and switch 86 closed, while switch S2 is kept closed. The current IL in the inductor L continues flowing (this is the characteristic behaviour of an inductor) charging up the reservoir capacitor 02, as well as supplying the current ILOAD-to the load. The inductor L now has voltage V2-applied across it, in opposite polarity to the previous phase, so its current will ramp down, eventually to zero.

Phase F (Figure 5f): When the current reaches zero (Phase F), switch 86 is opened to avoid pulling charge back out of the capacitor C. Where a switch 57a or 57b is provided, this is closed in order to avoid voltage oscillations due to any residual current in the inductor L. Switch 87a would be turned on along with S2 remaining on in series with switch 57a, to short the inductor. The alternative switch 57b can short the inductor by itself. An alternative form of Phase F would have switch S2 opened instead of S6 (with S7b in place if desired to short the inductor).

By cycling repeatedly through these six phases (A-F), the capacitors Cl and C2 can be re-charged in turn alternatively, thus generating positive and negative voltage supplies V2-'-and V2-using a single inductor. It should be noted that the current in the inductor reverses between the two types of charging cycle, whereas in known multi-output buck converters the current in the inductor always tends to flow in the same direction.

Importantly, it can now be seen that, in the present example, none of the switches ever sees greater potential more than the voltage at input voltage VI, relative to ground, across its terminals. The voltage at node X switches between V1 and ground, so switches Sl and S2 are never stressed by more than V1. Node Y is switched either to V2-'-by S4 or V2-by S6, so neither of these two switches will see a stress greater than V2+ -(V2-). In other embodiments where the voltages V2-'-and V2-are higher, for example Vl = 5V and V2-'-N2-= -i-I-3V, this peak switch voltage may be greater than Vt but importantly it will be less than the value VI -(V2-) experienced in the known circuit.

Additionally, since the switch S7a or S7b will only have to pass the residual current in the inductor, not any part of the load current, its on resistance' is relatively unimportant which implies that a small MOS switch may be employed.

Accordingly, the novel circuit therefore requires only four principal switches, compared with five required in the known buck-flyback circuit of Figure 2.

These principal switches can be distinguished from auxiliary switches such as switch S7a or S7b by their size and performance characteristics, which are critical to the efficiency of the DC-DC converter as a whole.

Controller 460 Figures 7a and 7b illustrate in more detail an implementation of controller 460 circuitry that may be used to control the operation of the DC-DC Converter 400 just described with reference to Figures 4 to 6. This control circuitry illustrates a simple current-mode control loop for maintaining each of the output voltages V2+ and V2-within a desired range.

The controller 460 of Figure 7a comprises switch control logic or sequencer 462 which conveniently implements a finite state machine according to well-known design principles (the corresponding state transition diagram is shown in Figure 8). Preferably, a square wave clock signal CLK is provided so that the frequency of charging cycles, and hence any resulting artefacts in the output voltages, are well-defined. Sequencer 462 has inputs connected to sensing and pre-processing circuitry to be described, and has outputs carrying the switch control signals CS1, CS2, CS4, CS6 and CS7. Switch pre-drive and level shifting circuitry 464 applies these control signals in the appropriate form to the array 465 of switches 51, S2, S4, S6 and 57a/S7b seen in Figure 4, which in Figure Ta is simply is depicted as a block at the right hand side of the drawing.

The external inductor L and capacitors Cl, C2 can be seen, as can the input and output terminals GND, Vi, V2-'-and V2-.

A potential divider comprising resistors RI a and Ri b is connected across the high side output terminals to produce at terminal V3-i-a scaled down version of the high side output voltage. A high side voltage sensing path comprising a first differential input amplifier (for example a transconductance stage) 466, a high side error filter 468 (typically an RC network) and a first comparator 470 processes the voltage V3+ to feed a logic signal CD-'-to the sequencer 462.

Input amplifier 466 has a reference input connected to the source of a reference voltage Vref. First comparator 470 has its reference input connected to receive a representation IL+ of the inductor current IL sensed in switch Sl by a current sensing circuit 472. Current sensing circuit 472 may operate by buffering the voltage dropped across a sense resistor in series with SI, or may alternatively comprise a current-mirror arrangement including SI. This sensed current is also applied to a second comparator 474 which has a reference input corresponding to zero current, and a logic signal ILZ-'-is fed by this comparator into sequencer 462. The current through S4 might be sensed instead of SI, if preferred.

As shown in broken lines, an additional panic' signal can be input to the sequencer by a third comparator 476 which compares the sensed voltage at V3+ with a panic' reference level VPANIC. (This circuitry is optional and its operation will be described separately, after the main features of operation have been described with reference also to Figure 8.) A second potential divider comprising resistors R2a and R2b is connected across the low side output terminals to produce at terminal V3-a scaled version of the actual low side output voltage. A low side voltage sensing path comprises a level shifter 478 a second differential input amplifier 480, a low side error filter 482, and a fourth comparator 484 processes this sensed voltage to feed a logic signal CD-to the sequencer 462. Comparator 480 has a reference input connected to the source of reference voltage Vref. Comparator 484 has its reference input connected to receive a representation IL-of the inductor current IL sensed in switch S2 (or S6) by a current sensing circuit 486.

This sensed current is also applied to a fifth comparator 488 which has a reference input corresponding to zero current, and a logic signal ILZ-is fed by this comparator into sequencer 462.

Fig 7b shows a possible implementation of level shifter 478. The input voltage is applied to an op-amp configured as a voltage follower, connected to a resistor RLS, which is connected in turn to a current source of defined value Isource. The output voltage is taken from the common node of the current source and the resistor. In operation, the resistor will have a constant l.R drop VLS = lsource.RLS. This will cause the voltage at the output to follow the signal at the op-amp output, but level shifted in a positive direction by the voltage VLS.

In operation, the attenuated positive output voltage V3+ derived from V2+ (for convenience of voltage level) is compared to a reference voltage Vref and the resulting error signal E+ is passed through filter 468 to give a filtered error signal FE+. The current in the inductor is sensed (during Phase A) by sensing the current through switch SI to give sensed-current signal IL+. This signal IL+ is compared with zero, to give a logic signal ILZ+ indicating the polarity of the inductor current: this signal may be used to flag that this current has decayed to zero. IL-'-is also compared with FE-'-to give a signal CD+ denoting whether the sensed inductor current IL+ is less than or greater than the filtered high side error signal FE+. The meaning of this comparison will be made clear later in

the description.

In the low side sensing path, level shifter 478 translates the attenuated negative output voltage V3-to provide a positive voltage for convenient comparison with reference Vref. This allows the control circuitry to operate from a convenient single positive supply such as Vi. In this signal path the inductor current during Phase D is conveniently sensed in switch S2, giving a sensed-current signal 1L-. Signal ILZ-indicates the polarity of the inductor current: this signal may be used to flag when IL-has decayed to zero, while signal CD-indicates that the inductor current IL-exceeds the low side filtered error signal FE-.

Since the sequencer cycles at a frequency much greater than the signal frequency of the powered circuitry (for example audio frequency), it will be expected that demand at any given time will be predominantly on either the high side or the low side, alternating as the audio signal alternates between positive and negative excursions. Many different control strategies and physical implementations are possible.

In the present embodiment, the policy chosen is broadly to alternate sub-cycles of each type at a constant rate, adapting the charge delivered in each sub-cycle according to the demand on each side. This minimises noise in the output supply voltages, maximising smoothness of the output waveform at times of low and moderate demand. The transition between sub-cycles is synchronised with a regular clock pulse, while the individual phase transitions within each sub-cycle are controlled asynchronously. As shown in Figure 6, the clock waveform may be asymmetrical, with a duty ratio designed to maximise efficiency in view of the many asymmetries present in the circuit, the operating voltages, and possibly expected asymmetry in the demand from the load.

Figure 8 is a state transition diagram showing how the sensory inputs generated by the circuitry shown in Figure 7a are used within sequencer 462 to set the switch control signals CSI, CS2, CS4, CS6 and CS7 to control the progression of phases A to F such that the two output voltages are kept close to their desired values as demand varies at each side of the load. The six states labelled A to F on the state diagram correspond to the Phases A to F in the operation of the switch network as already described, and the states of the switch control signals CS1 to CS7 in each phase are defined so as to achieve the switch states shown in the respective drawings Figure 5a to Sf. The arrows on the state transition diagram indicate transitions between states which are triggered by the logical conditions written beside each one. Some of the transitions are indicated with broken lines, and represent refinements to cover special situations that may arise in a practical implementation. Normal operation, indicated by the solid transition lines, will be described first.

Sequencer 462 in normal operation repeatedly cycles through Phases (states) A to F, thereby defining Phases A to F shown in the waveform diagram.

Following a clock transition from 1' to 0', the circuit starts in Phase A (corresponding to Figure 5a) and stays in that state while the sensed inductor current IL-'-is less than the peak inductor current demand signal FE-'-. Once IL+ rises to equal FE+, the circuit is switched into positive output charging Phase B. The circuit then remains in Phase B so long as IL-'-is greater than zero. Once IL+ has ramped down to zero, the circuit is switched into an idle state C It remains in state C until the next transition of clock CLK from 0 to 1, when it is switched into the first phase of the low side charging sub-cycle, namely Phase D, charging up the inductor L from capacitor CI in preparation for supplying capacitor C2. The circuit remains in Phase D until the sensed inductor current IL-has ramped up in magnitude to equal FE-. At that time the circuit is switched into the state shown in Figure 5e and Phase E begins. (Note that IL-and FE-are both negative signals, so the actual condition for this state transition is correctly stated as IL-< FE-.) The circuit then remains in Phase E until the inductor current has decayed to zero, when it is switched into the idle state (Phase F). After completing the low side sub-cycle the circuit is switched back into Phase A when CLK transitions from 1 to 0.

In this way, each of the feedback signal paths (high side and low side) acts similarly to a conventional current-mode control loop. The feedback paths act so that the voltage error modulates FE+ or FE-. FE+ and FE-may thus be regarded as demand signals, and the peak inductor current in each sub-cycle (Imax+ and Imax-) is set in proportion to the respective demand signal by using the output of comparator 470 to trigger the end of Phase A and transition into Phase B. Specifically, by comparing the filtered error signal FE+ with the instantaneous inductor current IL+ as it builds up during Phase A, comparator 470 produces a signal CD-'-which can be used to adjust the point in time at which Phase A ends, allowing more current to build up in the inductor in Phase A if the output voltage V2+ is far below the target value than if it is only slightly below. This allows a greater total charge transfer into capacitor Cl over both phases A and B when demand is high. The filter is necessary to reduce the feedback loop unity gain bandwidth to assure stability. Similarly signal FE-determines the inductor current level at which the end of Phase D will be triggered. Again a filter 482 is necessary to reduce the loop unity gain bandwidth to assure stability.

Deviating from the normal' operation just described, robust control requires some extra transition possibilities, including for example those illustrated by broken lines in Figure 8. As mentioned already, demand in typical applications will often be highly asymmetric, and fault conditions can always arise.

Accordingly, from Phase A, if the current still has not ramped up to FE+ by the time CLK changes from 0 to 1, the circuit is switched into Phase B to ramp the current down again to zero before passing through Phase C to the negative inductor charging Phase D. Depending on the load on the low-side output, there may not need to be a Phase D and E, or there may be enough time remaining for this to occur. If there is not enough time, then these low side phases may similarly spill into the next half clock period, with Phase D terminated when CLK switches from 1' to 0', as shown by the dotted path from Phase D, and transition out of Phase E delayed until IL-decays to zero.

From Phase F, a transitory state F' is defined from which, if FE-'-is less than zero, the circuit is switched directly to Phase C rather than Phase A. This is done so that the circuit will simply miss a high side sub-cycle rather than risk FE+ going high and requesting a burst of current just before the end of the sub-cycle period. Corresponding extra paths and transitory state C' are provided in relation to the low side sub-cycles and the feedback FE-from the negative side of the output supply. Extra control may also be added, for example to limit peak inductor current, by interrupting charging if the sensed inductor current exceeds some predetermined limit. This could be implemented by putting a limiter on the value of FE+ and FE-, instead of additional tests and state transitions.

The additional feedback path using reference VPAN1C is an added feature that can be provided to cope with a fault mode in which the low-side load demands a greater current than the regulator can supply. In this case, both the low-side and the high-side supply voltages will tend to droop. Since the energy that the high-side can supply to the low-side per cycle depends on the voltage across the inductor in the charging phase D, its capacity to charge the low side decreases as the high-side supply droops. There is therefore the danger that, even when the low-side demand returns to its "normal" maximum, the high-side supply will still not be able to supply enough energy per cycle, and the system may lock up, with the high-side supply getting lower and lower. To counter this risk, a "panic" threshold is set, somewhat lower than Vref, below which the high-side demand will be fulfilled by extra logic in sequencer 462, regardless of demand indicated by the low-side feedback path. In this way, at least the high-side may stay at a reasonably normal voltage, ready for a clean recovery once the excessive demand goes away.

Figure 9 is a state diagram for an alternative control loop strategy, using the same switch network. Figure 10 shows a modified feedback arrangement to be used with this state diagram, instead of the arrangement of Figure 7a. The same reference signs are used where the structure and function has elements in common with the circuit of Figure 7a, but prefixed 9' instead of 4' to distinguish the embodiments. Thus the controller 960 replaces controller 460, while modified sequencer is numbered 962 instead of 462, for example. The common elements will not be described further. It will be seen that differences are mainly in the high side path, where the elements 466, 468 and 470 are replaced by a pair of comparators 966 and 968 which generate output logic signals VSI + and VS2+ respectively for use by the sequencer 962. An upper threshold voltage Vhigh is applied to the non-inverting input of comparator 966, while the signal at V3+, representing the high side output voltage V2+, is applied to the inverting input of comparator 966. Conversely, a lower threshold voltage VIow is applied to the inverting input of comparator 968, while the signal at V3+ is applied to the non-inverting input of comparator 968. The panic' path is again provided as an optional feature.

The provision of upper and lower threshold detectors in the positive feedback path enables the high side charging to be controlled in a hysteretic fashion, whereby the attenuated output voltage V3+ is compared instantaneously against upper threshold Vhigh and lower threshold Vlow. Referring also to the state transition diagram of Figure 9, it can be seen that, at the rising edge of the clock, the inductor is charged only if condition V3+ cVlow is satisfied. From there, inductor charging continues until V3+ exceeds Vhigh, when the inductor is discharged until the sensed current has ramped down to zero. This gives a simpler control circuit, but one where careful attention is needed in the design to maintain stability. It will be understood that the thresholds VIow and Vhigh actually applied to the comparator inputs are set in accordance with the scaling factor of the potential divider RI a/Ri b for comparison with V3+, but are scaled up when represented on the waveform diagrams, for comparison with the actual value of V2-'-.

Figure 11 illustrates waveforms depicting a yet further possible mode of operation of the DC-DC converter 400.State transition rules and feedback paths can be generated readily by a designer wishing to implement this mode of operation, based on the principles illustrated in the previous examples. The waveforms of Figure 11 illustrate the result of applying state transition conditions in which the 0-1 transition of signal CLK is ignored and idle state C is omitted, the circuit normally passing from state B directly to state D. This reflects the observation that the switch states in Phases B and D are in fact identical, avoids the need to toggle switch S4 or S7b merely to create an idle state C, and allows more freedom of duty cycle between the positive and negative sub-cycles and their respective charging times. In this diagram, the high side switching is determined by hysteretic thresholds Vhigh and VIow as above. The low-side output V2-is shown in relation to a target value VTARGET-, although its switching may be determined by a signal CD-and ILZ-as described above. A reference signal defining VTARGET-may be derived from Vref via a level shifter and resistor divider.

Many different sets of rules and feedback paths are possible, each with its own advantages and disadvantages in a given application. Further variations are described below.

The modes of operation described so far have assumed charging positive and negative outputs in alternate sub-cycles, albeit with the possibility of an empty sub-cycle in case of no demand. Other schemes are possible in which sub-cycles of the same type can be concatenated in case of high demand from one side or the other. This effectively implements the continuous mode' of operation known in DC-DC converters generally, in which a new sub-cycle can be started without requiring the inductor current to return to zero. This continuous mode operation is possible between sub-cycles of the same type (successive cycles charging the high side, or successive cycles charging the low side). The main constraint is that the continuous mode should be ended and the inductor current returned to zero before a sub-cycle of the opposite type is started.

Figure 12 illustrates waveforms for one such scheme wherein, at each clock transition, the voltage errors for V2-'-and V2-are compared, and the output requiring the greater re-charge is selected. At the first transition illustrated in the example waveforms, V2+ is lower (less positive) than its lower target VIow but V2-is actually below (more negative) than its target VTARGET-so actually needs no re-charge, so Phase A is selected. At the next transition, V2-is slightly positive, but V2+ is still a long way from its target, so Phase A is selected, to boost the inductor current even though it is still not zero. At the third transition, V2+ has overshot positive, while V2-has drooped, so the device does not switch back to Phase A, but continues in Phase B until the current drops to zero and it can drop idle Phase C until the next rising clock edge. The transitions from Phase A to Phase B and Phase D to Phase E are governed by the filtered error signal, FE-in this example. Again, all manner of refinements are possible, for example, to double the speed of the clock or equivalent measures, so that the circuit doesn't have to wait until the "right" sub-cycle to switch which side it is charging.

In many appUcations, the output voltages wanted will be constant. It should be appreciated, however, that the output voltages V2+ and V2-can be controlled to vary over time. This can be done very simply by varying the reference voltages Vref and so forth, that are applied at various points in the feedback control circuits described above. It may be easier alternatively to vary the ratios of the potential dividers Ria/Rib and R2a/R2b instead, to achieve an equivalent effect, or both techniques could be used in combination. The variation may be manually controlled, or controlled automatically according to some desired behaviour.

Many other modifications in the control scheme, the form of the controller 460 and even specifics of the switch network may be varied. The skilled reader will appreciate that the above and other modifications and additions are possible to these circuits, without departing from the spirit and scope of the invention as defined in the appended claims. Accordingly, the above described embodiments are presented to illustrate rather than limit the scope of the invention. For interpreting this specification and claims, the reader should note that the word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, the singular article "a" or "an" does not exclude a plurality, and a single element may fulfil the functions of several elements recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Where a claim recites that elements are "connected" or are "for connecting", this is not to be interpreted as requiring direct connection to the exclusion of any other element, but rather connection sufficient to enable those elements to function as described. The skilled reader will appreciate that a good, practical design might include many auxiliary components not mentioned here, performing, for example, start-up and shutdown functions, sensing functions, fault protection or the like, some of which have been mentioned already, and none of which detract from the basic functions characteristic of the invention in its various embodiments described above in the claims.

In addition to variations and modifications within the DC-DC converter circuit itself, the invention encompasses all manner of apparatuses and systems incorporating the DC-DC converter, besides the headphone amplifier application illustrated in Figure 2. The circuit may be used to power output stages of all manner of apparatus, including communications apparatus, where the output stage may drive an antenna or transmission line, an electro-optical transducer (light emitting device) or electromechanical transducer. In all these fields of application, particularly battery or line-powered devices, the benefits of minimum size and cost which the invention permits are increasingly important.

Claims (8)

1. CLAIMS1. A DC-DC converter circuit comprising a switch network for connecting a voltage input terminal, inductor terminals and first and second output terminals, wherein said switch network is arranged such that four switches of said network can be operated, in use, to generate a positive output voltage at said first output terminal and a negative output voltage at said second output terminal.
2. 2. A DC-DC converter circuit as claimed in claim 1 wherein said four switches comprise: a first switch for connecting the input terminal to the first inductor terminal, a second switch for connecting the first inductor terminal to the common terminal, a third switch for connecting the second inductor terminal to the first output terminal and a fourth switch for connecting the second inductor terminal to the second output terminal.
3. 3. A DC-DC converter circuit as claimed in claim 1 or claim 2 wherein said switch network comprises at least one additional switch to said four switches..
4. 4. A DC-DC converter circuit as claimed in claim 3 wherein said additional switch is for making a connection between said inductor terminals.
5. 5. A DC-DC converter circuit as claimed in claim 3 or claim 4 wherein said additional switch is of smaller physical area than said four switches.
6. 6. A DC-DC converter circuit as claimed in any preceding claim further including functional circuitry connected to be powered by said DC-DC converter circuit.
7. 7. An audio apparatus including a DC-DC converter circuit as claimed in any preceding claim and audio output circuitry connected to be powered from the first and second output terminals of said converter circuit.
8. 8. Audio apparatus as claimed in claim 7 where said audio apparatus is at least one of: portable apparatus; communications apparatus; an in-car audio apparatus; and headphone apparatus.