GB2473179A

GB2473179A - Phase locked loop with leakage current compensation circuit

Info

Publication number: GB2473179A
Application number: GB0912934A
Authority: GB
Inventors: Humberto Andrade Da Fonseca; Peter Hunt; Joaquim Machado; Andrew Pickering
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2009-07-24
Filing date: 2009-07-24
Publication date: 2011-03-09
Also published as: GB0912934D0

Abstract

The present invention provides an improved phase locked loop (PLL) in which deterministic jitter induced by current leakage in the loop filter is virtually eliminated. The PLL includes a phase/frequency detector (PFD) 18 connected to a main charge pump20. The main charge pump 20 is connected to a loop filter 16. The PLL also includes an anti-leakage circuit 14 comprising a second charge pump 26, an integrating capacitor 28 and a controllable current source 30. The second, `anti-leakage' charge pump is connected to the outputs of the PFD 18 in an anti-phase arrangement with respect to the connection of the main charge pump 20. The output of the leakage compensation charge pump 26 is connected to an integrating capacitor 28 and thence to transistor 30. The integration capacitor 28 charges until the transistor 30 passes sufficient current into node 32 of loop filter 16 to compensate for filter and VCO leakage currents.

Description

IMPROVEMENTS IN OR RELATING TO PHASE LOCKED LOOPS

FIELD OF THE INVENTION

The present invention relates to Phase Locked Loops in electronic circuits. More particularly, the present invention relates to an improved phase locked loop and an anti-leakage loop therefor.

BACKGROUND OF THE INVENTION

Conventiona] Phase Locked Loops (PLLs) in deep sub-micron CMOS processes suffer from current leakages in the loop filter and voltage controlled oscillator (VCO) which cause the presence of deterministic jitter at the output of the VCO. The existence of these current leakages creates, after lock, a static phase error at the outputs of the Phase Frequency Detector in the PLL.

This static phase error ensures that the charge lost during one reference cycle is restored regularly (periodically during the next cycle) by the main charge pump. However this, while keeping the PLL locked, creates a ripple in the control voltage that appears as deterministic jitter at the output of the VCO.

Thus there is a need for an improved PLL that suffers from little or no deterministic jitter, and a circuit that can eliminate or compensate for the current leakages in a PLL.

SUMMARY OF THE INVENTION

The present invention provides an improved phase locked loop (PLL) and an anti-leakage ioop therefor, which are able to virtually eliminate the effects of deterministic jitter induced by current leakage. According to a first aspect of the invention there is provided an improved phase locked loop (PLL) circuit as set forth in the appended claims. According to a second aspect of the invention there is provided an anti-leakage loop for eliminating current leakage from a PLL, as set forth in the appended claims Examples of the invention will now be described with reference to the accompanying drawings, of which: Figure 1 shows a PLL circuit with anti-leakage loop according to a preferred embodiment of the present invention; Figure 2 is a graph showing how deterministic jitter present in an improved PLL circuit, in accordance with the present invention, is virtually eliminated during operation of the PLL circuit, wherein the x-axis represents time in seconds and the y-axis represents deterministic Jitter in pico seconds and Figure 3 is a graph showing how various control voltages in the improved PLL vary in time when the PLL is converging towards a locked state, where the x-axis represents time in seconds and the y-axis represents voltage in volts.

DETAILED DESCRIPTION

Figure 1 shows a block diagram of an improved PLL circuit according to a preferred embodiment, comprising a main loop and 12 an anti-leakage loop 14. The main loop 12 comprises a Phase Frequency Detector (PFD) 18 coupled to both a Main Charge Pump 20 and the anti-leakage loop 14, a Loop Filter (LPF) 16 coupled between the main charge pump 20 and a Voltage Controlled Oscillator (VCO) 22, and a Feedback Divider 24 coupled between the VCO 22 and the PFD 18. The anti-leakage loop 14, as well as being coupled to the LPF 16, is also coupled to a loop filter node 32 on the coupling connecting the PFD 18 between the main charge pump and the VCO, and to a power supply.

When designing a PLL circuit in a deep-sub-micron process current leakage in the Loop Filter and VCO is a major concern because of its impact on the amount of deterministic jitter exhibited in the circuit. The preferred embodiment compensates for the current leakage in the LPF regardless of its cause, by the deployment of a second loop, the anti-leakage loop 14, in the PLL.

The anti-leakage loop 14 comprises an anti-leakage charge pump 26, an integration capacitor C3 and a PMOS controlling transistor MAL. The anti-leakage charge pump 26 is coupled to the PFD but is wired in anti-phase with respect to the coupling of the main charge pump to the PFD, as can be seen from Figure 1.

As explained previously, in a conventional charge pump PLL, which has no anti-leakage loop, the existence of leakage in the loop filter 16 creates, after lock, a static phase error at the outputs of the PFD. This static phase error ensures that the charge lost during one reference cycle is restored regularly (periodically during the next cycle) by the main charge pump.

However this, while keeping the PLL locked, creates a ripple in the control voltage that appears as deterministic jitter at the output of the VCO.

The present invention takes the static phase error presented at the output of the PFD, and uses it to control a second charge pump, the anti-leakage charge pump 26, and charge the integration capacitor C3. While there is static phase error at the outputs of the PFD, the integration capacitor C3 keeps charging until the transistor MAL lets through enough current into the main loop 12 at the loop filter node 32 to compensate for the LPF and VCO current leakages. When this occurs the static phase error caused the current leakages reduces to zero.

By utilizing the static phase error presented at the outputs of the PFD, the present invention compensates for the LPF and VCO current leakages in a closed loop manner which makes this technique more robust to temperature and process variations.

So as not to affect the stability of the main loop 12, the anti-leakage loop 14 of a preferred embodiment is designed for a response time 10 times slower than the main loop. However, the inventors have been able to successfully operate the anti-leakage loop 14 and the main loop 12 with response time ratios down to 4 with the PLL 10 still locking.

In Figure 3 the graph shows plots of the control voltages when the improved PLL according to the preferred embodiment is converging towards the locked state. The plot labelled A shows how the gate voltage of the PMOS transistor 30 varies in time during operation. The plot labelled B shows the voltage at the input of the VCO 22 during operation, and the plot labelled C shows the voltage across the integration capacitor 28. For all three plots the x-axis represents time in seconds and the y-axis represents voltage in volts.

Claims

CLAIMS1. An anti-leakage loop for reducing the effect of current leakages in a Phase locked Loop PLL comprising a main loop comprising a Phase Frequency Detector PFD, a main charge pump coupled to the outputs of the PFD, and a loop filter coupled between the output of the main charge pump and an input to a Voltage Controlled Oscillator VCO, said PLL having a loop filter node on the coupling connecting the loop filter between said main charge pump and said VCO, said anti-leakage loop comprising: an anti-leakage charge pump connected to the outputs of the PFD in anti-phase arrangement with respect to the coupling of the main charge pump to the PFD; an integration capacitor coupled between a power supply and an output of the anti-leakage charge pump; and a PMOS transistor the source of which is coupled to the power supply, the drain of said PMOS transistor being coupled to said loop filter node, and the gate of said PMOS transistor being coupled to a node on a coupling between said anti-leakage charge pump and said integration capacitor.
2. An anti-leakage loop as claimed in claim 1 wherein the integration capacitor has a capacitance which enables said anti-leakage loop to operate with a response time greater than or equal to 4 times slower than said main loop of the PLL.
3. An anti-leakage loop as claimed in claim 1 wherein the integration capacitor has a capacitance which enables said anti-leakage loop to operate with a response time 10 times slower than said main loop of the PLL.
4. An improved Phase Locked Loop PLL comprising: a main loop comprising: a Phase Frequency Detector PFD having one input for receiving a reference frequency signal, and having another input and an output, a main charge pump coupled to the outputs of the PFD, a loop filter coupled between the output of the main charge pump and an input to a Voltage Controlled Oscillator VCO, said PLL having a loop filter node on the coupling connecting the loop filter between said main charge pump and said VCO, said VCO having an output, and a feedback divider coupled between the output of the VCO and another input of the PFD; and an anti-leakage loop configured to compensate for current leakage in said main loop.
5. An improved PLL as claimed in claim 4, wherein said anti-leakage loop comprises: an anti-leakage charge pump connected to the output of the PFD in anti-phase arrangement with respect to the coupling of the main charge pump to the output of the PFD; an integration capacitor coupled between a power supply and an output of the anti-leakage charge pump; and a PMOS transistor the source of which is coupled to the power supply, the drain of said PMOS transistor being coupled to said loop filter node, and the gate of said PMOS transistor being coupled to a node on a coupling between said anti-leakage charge pump and said integration capacitor.
6. An anti-leakage loop substantially as hereindescribed with reference to the drawings.
7. The subject matter hereof or any part thereof in any novel, inventive or useful combination.