GB2469450A - Uniaxial Tensile Strain in Semiconductor Devices - Google Patents

Uniaxial Tensile Strain in Semiconductor Devices Download PDF

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Publication number
GB2469450A
GB2469450A GB0906333A GB0906333A GB2469450A GB 2469450 A GB2469450 A GB 2469450A GB 0906333 A GB0906333 A GB 0906333A GB 0906333 A GB0906333 A GB 0906333A GB 2469450 A GB2469450 A GB 2469450A
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semiconductor device
active layer
device structure
strain
tensile strain
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GB0906333D0 (en
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David John Wallis
Richard Jefferies
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Qinetiq Ltd
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Qinetiq Ltd
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Priority to GB0906333A priority Critical patent/GB2469450A/en
Publication of GB0906333D0 publication Critical patent/GB0906333D0/en
Priority to PCT/GB2010/000713 priority patent/WO2010119239A1/en
Priority to CN2010800264777A priority patent/CN102460705A/en
Priority to US13/263,621 priority patent/US20120018704A1/en
Publication of GB2469450A publication Critical patent/GB2469450A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Abstract

A semiconductor device structure for example an n-FET or p-FET comprises an active layer 1 and a buffer layer 2. The active layer for example InSb is a quantum well structure. There is a lattice mismatch between the buffer layer which may be Alxln1-xSb and the active layer 1 which places the active layer under biaxial compressive strain. Uniaxial tensile strain is applied to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction. The tensile strain may be applied by stretching. This favours hole and electron mobility in the first direction and, renders the semiconductor device structure suitable for the formation of both p-channel and n-channel devices. A method of manufacturing a semiconductor device is also disclosed.

Description

UNIAXIAL TENSILE STRAIN IN SEMICONDUCTOR DEVICES
Field of the Invention
The invention relates to uniaxial tensile strain in semiconductor devices. It is particularly relevant to uniaxial tensile strain in semiconductor devices with a quantum well active layer, in particular QWFETs (Quantum Well Field Effect Transistors).
Background to the Invention
In order to produce improvements to logic circuits, it is desirable to produce device structures, particularly field-effect transistors (FETs), that work at higher frequencies and lower powers. The standard architecture for digital circuit design is CMOS. To achieve CMOS circuits, both n-FETs (with electrons as charge carriers) and p-FET5 (with holes as charge carriers) are required.
Conventional CMOS design is largely based on Si semiconductor technology. For n-FETs, very high operational frequencies and low operating powers have been achieved using lnSb as a semiconductor. In this system, a layer of AIln1Sb is grown on a suitable substrate, such as GaAs, and a thin device layer of InSb grown over this. A donor layer to provide electrons is grown over the device layer, separated from it by a small Alln1Sb spacer layer. The device layer is capped by a suitable layer, again Alln1Sb, to confine the charge carriers in the device layer region, which forms a quantum well. For regions with a composition of Alln1Sb, the value of x may vary from region to region. There is a lattice mismatch between the lnSb and the AIIn1Sb, which leads to biaxial strain in the quantum well and can result in increased carrier mobility.
lnSb has a very high electron mobility, and extremely good results have been achieved.
It is desirable to be able to produce p-FETs with comparable performance to these lnSb n-FETs. InSb has relatively high hole mobility, so the same lnSb/ AlIn1Sb system is an appropriate one for producing p-FETs with suitable properties. The strain in the quantum well structure makes a significant contribution to these electrical properties. The quantum well structure is under significant biaxial compressive strain as a result of the lattice mismatch between lnSb and Alln1Sb. It is known that strain can make a significant contribution to carrier mobility. In Si surface channel devices, it is found that tensile strain in the carrier transport direction enhances electron mobilities, whereas compressive strain in the carrier transport direction enhances hole mobilities.
It would be desirable to use the benefits of strain to provide improved device structures.
However, it is necessary to do this in such a way that the devices remain stable, and do not break down or lose desirable electrical properties through the presence of excessive strain.
Summary of the Invention
Accordingly, in a first aspect the invention provides a semiconductor device structure comprising: an active layer comprising a quantum well structure; a butler layer underneath and adjacent to the active layer, wherein there is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain; and means to apply uniaxial tensile strain to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction, the first direction and the second direction lying in a plane of the active layer.
This arrangement enables the high carrier mobility resulting from compressive strain to be exploited in the first direction, without there being such significant strain on the active layer that physical deterioration will result with decline in electrical properties. This may be applied to both p-type and n-type devices.
Advantageously, both p-channel devices such as p-FETs and n-channel devices such as n-FETs will be formed with the p-channel lying in the first direction. This approach thus allows improved fabrication of p-FET and n-FET structures on the same substrate using the same semiconductor device system.
The active part of the device may be unstrained in the second direction, as the uniaxial tensile strain and the biaxial compressive strain are in balance. Alternatively, the uniaxial tensile strain may exceed the biaxial compressive strain, and the semiconductor device structure may be under overall tensile strain in the second direction, leading to greater carrier mobility in the first direction than for the bulk semiconductor.
Desirably, the active layer is formed of lnSb and the buffer layer of Alln1Sb, though alternative semiconductor systems may be employed.
In a further aspect, the invention provides a method of manufacturing a semiconductor device structure, comprising: epitaxially growing a buffer layer on a substrate; epitaxially growing a quantum well active layer on the substrate, wherein there is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain; and applying uniaxial tensile strain to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction, the first direction and the second direction lying in a plane of the active layer.
This uniaxial tensile strain may be applied to the semiconductor device structure as a whole. This may be done by a mechanical approach, such as by bending the semiconductor device structure about an axis lying in the first direction or by stretching the semiconductor device structure in the second direction. This may occur before or after bonding the semiconductor device to a base substrate.
Specific Embodiments of the Invention Specific embodiments of the invention will now be described, by way of example, by reference to the accompanying Figures, of which: Figure 1 shows an FET structure which can be used in embodiments of the invention; Figure 2 illustrates the compressive biaxial strain on the active layer in a strained quantum well device; Figure 3 illustrates the effect of applying uniaxial tensile strain to a strained quantum well device in accordance with embodiments of the invention; and Figure 4 illustrates n-FET and p-FET devices formed from a strained quantum well active layer under uniaxial tensile strain in accordance with embodiments of the invention.
Figure 1 shows a device structure which can be used either for an n-FET device or a p-FET device with appropriate materials and design choices.
The device structure has an InSb quantum well active layer 1 grown on an AllniSb buffer layer 2. It is appreciated that similar structures can be produced for other Ill-V semiconductor systems or indeed other semiconductor systems altogether using a strained quantum well structure. The buffer layer is grown on a substrate 3, which may for example be of GaAs (though Si is a possible alternative). The buffer layer 2 is typically about 3 pm thick, though this thickness may be reduced to as little as 1 pm in appropriate embodiments, and its composition is chosen to provide effective containment of the charge carriers in the active layer 1 -for Alln1Sb, this could involve a value for x of approximately 0.35 for p-FETs and 0.15 for n-FETs (electrons show stronger confinement than holes, so the two device systems optimise differently). The lattice mismatch between lnSb and Alln1Sb places the active layer 1 under compressive strain -this strain is approximately 2% for Al.35ln0.65Sb.
The active layer 1 may differ in thickness for different device types. There may also be different materials choices in the other device layers.
For an n-FET, the active layer 1 may be approximately 2Onm thick -at this thickness quantum states for the carriers are abundant. A spacer layer 12 of Alln1Sb is provided above the active layer, and above that there is a donor sheet 14 (which may, for example, comprise a Te ö-doped sheet doped at approximately lxi 012 cm2) to provide electrons as carriers for the n-channel of the n-FET. This is covered by a confinement layer 16 of Alln1Sb to confine charge carriers in the quantum well structure -this may be 15-45 nm thick.
For a p-FET, a thinner active layer may be used as dislocations resulting from the lattice mismatch would severely limit hole mobility. A quantum well thickness of about 5nm is sufficiently thin that dislocations will not limit hole mobility, but sufficiently thick that there are sufficient low energy quantum states available for carriers. A spacer layer 12 of Alln1Sb is again provided above the active layer with a composition suitable for a p-channel. Above this there is a donor sheet 14 with a dopant appropriate for a p-channel (this may, for example, comprise a Be a-doped sheet) to provide holes as carriers for the p-channel. This is again covered by a confinement layer 16 of Alln1Sb to confine charge carriers in the quantum well structure.
The source 4, the drain 5 and the gate 6 of each FET are formed over the confinement layer 16 in each case by an appropriate metallisation process. This may be a conventional photolithographic or e-beam lithographic process of masking and etching.
It is necessary for the gate 6 to have control over conduction in the channel formed in the active layer 1 between the source 4 and the drain 5 -this requires that it is not separated by too great a thickness of insulator! wider band gap semiconductor from the active layer 1. Figure 1 shows an arrangement in which the confinement layer 16 has been etched back underneath the gate to allow the gate voltage to control the n-channel/p-channel effectively.
Further device structures may be employed in other embodiments of the invention -what is shown in Figure 1 is simply a suitable device structure for use with this materials system. The person skilled in the art will appreciate that other structures may be used for this materials system, or may be appropriate with other materials systems. As indicated above, the n-FET and p-FET structures here are only examples of device structures that may be used in embodiments of the invention, and alternative device structures may similarly be used. One example of such an alternative device structure suitable for p-FETs is a system using a-Sn as semiconductor, rather than lnSb (as is discussed in the applicant's copending British patent application of even date entitled "P-Type Semiconductor Devices", which is incorporated by reference herein to the extent permitted by law. A further example suitable for p-FETs is one in which the thickness of the active layer is increased by compensating for strain in the buffer layer caused by thermal expansion and lattice mismatches between the buffer layer and the substrate -this is described in more detail in the applicant's copending British patent application of even date entitled "Strain Control in Semiconductor Devices", which is incorporated by reference herein to the extent permitted by law.
Figure 2 illustrates the biaxial compressive strain on the active layer. Both lnSb and Alln1Sb adopt the zinc blende crystal structure, but the unit cell of lnSb is significantly larger than that of Alln1Sb, resulting in a lattice mismatch between the two and a compressive strain of almost 2% on the lnSb quantum well structure as it is constrained to the Alln1Sb dimensions with x=0.35. This compressive strain is broadly beneficial for p-type devices, as it promotes hole transport. Holes therefore have a high mobility in this kind of quantum well structure, provided that the quantum well itself is sufficiently thin, as the high compressive strain will result in dislocations if the quantum well exceeds a critical thickness (approximately 7 nm for lnSb on A10351n065Sb, according to the model set out in Matthews and Blakeslee, set out in Journal of Crystal Growth Vol. 29 (1975) pp. 273-280).
This arrangement favours the formation of p-type devices. In suitable materials systems, such as the lnSb system discussed here, it is found also to be advantageous for n-type devices, as it has been found that electron mobility is also favoured by tensile strain in such systems.
If uniaxial strain is applied to the device, a first direction and a second direction will be established -one without strain, and the other with strain. Electron and hole mobility will be favoured in the nominally unstrained direction. If uniaxial compressive strain is applied in the first direction, hole and electron mobility will in principle be further enhanced in this direction. This, however, increases the level of strain to a very high value, as 2% strain is already a significant amount to be accommodated in a crystal structure. Use of such high values of strain would increase the risk of physical breakdown of the material with consequent damage to the electrical properties of the device.
Applying uniaxial tensile strain to the first direction achieves a more effective result, as is shown in plan view in Figure 3 which illustrates an embodiment of the invention in schematic terms. A unit cell of lnSb is shown under different conditions. In bulk (31), the unit cell 30 is unstrained, but in a quantum well structure (32) grown on Al0 351n0 65Sb, it is under 2% compressive strain. As indicated above, when uniaxial compressive strain is applied (33) in the direction of current flow -this may be chosen as the [100] or [110] direction in this semiconductor system -this increases hole and electron mobility in principle, but leads to potential material breakdown. However, when uniaxial tensile strain is applied (34) normal to the channel current flow direction -along the [0101 or [1- 10] direction in this case -the carrier mobility in the channel remains high and will moreover be higher in the current flow direction than in a direction orthogonal to current flow. The level of uniaxial tensile strain may be chosen to make the overall strain in the [010] or [1-10] direction substantially zero, or even sufficient to make the overall strain in the [010] or [1-10] direction tensile rather than compressive.
As shown in Figure 4, this favours the formation on the semiconductor device structure of both p-FET5 41 (and other p-channel devices) and n-FETs 42 (and other n-channel devices) in the same orientation, with the channels lying in the [100] direction. This allows enhanced hole and electron mobility to be achieved together in a single semiconductor system.
There are a variety of different approaches available for applying uniaxial strain to semiconductor devices. These include mechanical approaches, growth of different materials near the device, and use of compliant substrates. Each approach will be briefly described, though it will be appreciated that any approach to applying uniaxial tensile strain which does not damage the fundamental electrical properties of the device may be applied, and that the approaches shown here are by way of example only.
A range of mechanical approaches for producing uniaxial tensile strain to a semiconductor device are discussed in US Patent No. 6455397. All these techniques may be applied to a semiconductor device structure which has already been grown (referred to in US Patent No. 6455397 as a "membrane"), though thinning of the device substrate below a conventional thickness may be required to make the techniques effective. In a first approach, the membrane is mechanically stretched by clamping to a strain bed and applying tensile strain by a screw and micrometer assembly. The strained membrane is then bonded to an additional substrate while under tension. In a second approach, the membrane is mounted and bonded to a curved additional substrate, the curvature being chosen to achieve a particular strain value. In a third approach, an additional substrate is positioned within the curvature of a curved support structure. The membrane is then bonded to this additional substrate -the additional substrate and membrane are then removed from the support structure and the additional substrate is bonded to a substantially flat surface of a further additional substrate. All these approaches allow the application of controlled uniaxial tensile strain to a semiconductor device structure of the type described here. Further details of the straining processes outlined here are not in themselves fundamental to the present invention, but may be found in US Patent No. 6455397.
Use of growth of different materials near a semiconductor device to induce strain in that device is known, but is generally used as a mechanism to introduce compressive strain (by growing a region that presses against the device region to compress it further).
Other approaches involving this type of technique are however discussed in Ghani et al, Technical Digest of the International Electron Devices Meeting 2003, 8 (2003), and the person skilled in the art will appreciate that this approach may also be used to provide uniaxial tensile strain.
Use of compliant substrates to apply uniaxial tensile strain is discussed in Yin et al, Applied Physics Letters 87, 061922 (2005). After growth, semiconductor devices are transferred to a substrate coated with a compliant film (in the case described, a borophosphosilicate glass (BPSG) film formed on a Si substrate), The device structure is patterned into islands, and heating of the assembled structure allows for change in strain as the viscosity of the BPSG film decreases rapidly with temperature. This approach again allows for application of tunable uniaxial tensile strain, and is further described in Yin et al. A method of making such a semiconductor device structure can employ conventional approaches to formation of the basic device structure together with a method of applying tensile uniaxial strain as discussed above. A buffer layer is grown over the substrate using a suitable epitaxial growth method -molecular beam epitaxy (MBE) and metalorganic chemical vapour deposition (MOCVD) are particularly suitable epitaxial growth techniques, but any suitable growth technique may be used (other examples are MOVPE, ALD and MECVD). Growth by MBE or MOCVD at a suitable temperature (effective growth can be achieved at 350°C, but growth can be carried out up to the melting point of lnSb at 520°C) is appropriate for growth of Alln1Sb on GaAs, but as the skilled person will appreciate, other epitaxial growth methods may be used. The lnSb quantum well structure may be grown over this by a similar growth method, as may the other insulator and dopant layers by processes well established in the technical literature. Metallisation to form the source, the drain and the gate of each FET structure (alternative metallisations may be required for other device structures, but the same principles apply) may be made by any appropriate approach, such as photolithographic mask and etch processes. A process for applying uniaxial tensile strain may be employed either after fabrication or during fabrication of the semiconductor device structure, depending on which is appropriate to the strain producing process used. For example, for any of the mechanical processes described in US Patent No. 6455397, the basic semiconductor device structure would be formed before uniaxial tensile strain is applied, the strain subsequently being applied by one of the processes described in US Patent No. 6455397.

Claims (15)

  1. CLAIMS1. A semiconductor device structure comprising: an active layer comprising a quantum well structure; a buffer layer underneath and adjacent to the active layer, wherein there is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain; and means to apply uniaxial tensile strain to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction, the first direction and the second direction lying in a plane of the active layer.
  2. 2. Semiconductor device structure as claimed in claim 1, wherein a p-type device is formed in the semiconductor device structure, the p-type device having a p-channel oriented substantially in the first direction.
  3. 3. Semiconductor device structure as claimed in claim 2, wherein the p-type device is a p-FET.
  4. 4. Semiconductor device structure as claimed in any preceding claim, wherein an n-type device is formed in the semiconductor device structure, the n-type device having an n-channel oriented substantially in the first direction.
  5. 5. Semiconductor device structure as claimed in claim 4, wherein the n-type device is an n-FET.
  6. 6. Semiconductor device structure as claimed in any preceding claim, wherein the active layer is substantially unstrained in the second direction.
  7. 7. Semiconductor device structure as claimed in any preceding claim, wherein the active layer comprises an lnSb quantum well structure.
  8. 8. Semiconductor device structure as claimed in claim 7, wherein the buffer layer is formed of Alln1Sb.
  9. 9. Semiconductor device structure as claimed in any preceding claim, wherein the means to apply uniaxial tensile strain comprises means to bend the semiconductor device structure about an axis lying in the first direction.
  10. 10. Semiconductor device structure as claimed in any preceding claim, wherein the means to apply uniaxial tensile strain comprises means to stretch the semiconductor device structure in the second direction.
  11. 11. Semiconductor device structure as claimed in claim 10 or claim 11, wherein the semiconductor device structure is bonded to a base substrate before or after bending or stretching.
  12. 12. A method of manufacturing a semiconductor device structure, comprising: epitaxially growing a buffer layer on a substrate; epitaxially growing a quantum well active layer on the substrate, wherein there is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain; and applying uniaxial tensile strain to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction, the first direction and the second direction lying in a plane of the active layer.
  13. 13. A method as claimed in claim 12, wherein the step of applying uniaxial tensile strain to the active layer comprises applying uniaxial tensile strain to the semiconductor device structure as a whole.
  14. 14. A method as claimed in claim 13, wherein the step of applying uniaxial tensile strain comprises bending the semiconductor device structure about an axis lying in the first direction before or after bonding the semiconductor device structure to a base substrate.
  15. 15. A method as claimed in claim 13, wherein the step of applying uniaxial tensile strain comprises stretching the semiconductor device structure in the second direction before or after bonding the semiconductor device structure to a base substrate.
GB0906333A 2009-04-14 2009-04-14 Uniaxial Tensile Strain in Semiconductor Devices Withdrawn GB2469450A (en)

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GB0906333A GB2469450A (en) 2009-04-14 2009-04-14 Uniaxial Tensile Strain in Semiconductor Devices
PCT/GB2010/000713 WO2010119239A1 (en) 2009-04-14 2010-04-12 Uniaxial tensile strain in semiconductor devices
CN2010800264777A CN102460705A (en) 2009-04-14 2010-04-12 Uniaxial tensile strain in semiconductor devices
US13/263,621 US20120018704A1 (en) 2009-04-14 2010-04-12 Uniaxial tensile strain in semiconductor devices

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US9368619B2 (en) * 2013-02-08 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for inducing strain in vertical semiconductor columns
US9466668B2 (en) 2013-02-08 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Inducing localized strain in vertical nanowire transistors
US9564493B2 (en) 2015-03-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

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