GB2466218A

GB2466218A - A Cartesian loop RF transmitter with adaptive envelope modulation of the amplifier power supply voltage

Info

Publication number: GB2466218A
Application number: GB0822729A
Authority: GB
Inventors: Moshe Ben Ayun; Ovadia Grossman; Shay Nir; Mark Rozental
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2008-12-12
Filing date: 2008-12-12
Publication date: 2010-06-16
Anticipated expiration: 2028-12-12
Also published as: GB2466218B; GB0822729D0

Abstract

The power supply voltage Vs for the power amplifier 126 in a radio transmitter is reduced until non-linearity is detected, thereby achieving optimal amplifier efficiency. The supply voltage controller 127 provides a reference signal to the regulator 111 which is the product of the RF signal envelope and a scaling factor from the nonlinearity detector 125. The scaling factor is reduced until nonlinearity occurs or the scaling factor reaches a minimum value. The nonlinearity detector 125 (figure 2) is coupled to the outputs of the Cartesian loop filters 116,118 and measures the ratio of power at an offset frequency to on-channel power. Efficiency is not reduced by VSWR changes.

Description

SIMULTANEOUS SUPPLY MODULATION AND CiRCULATOR ELIMThATION WITH MAXIMUM EFFICIENCY

FIELD OF TEE INVENTION

[0011 The present invention relates to a linear RF (radio frequency) transmitter and a method of operation of the transmitter. In particular, the invention relates to a linear RF transmitter including a nonlinearity detector and a control loop to change an operating condition of the transmitter when the detector detects non-linearity in the transmitter.

BACKGROUND

10021 RF communication terminals normally employ an RF transmitter to generate RF signals and a receiver to receive RF signals. Such terminals also normally employ an antenna to send signals produced by the transmitter over the air to another terminal and to receive signals sent over the air from another terminal for delivery to the receiver. The transmitter normally includes an RF power amplifier to amplify the RF signals before they are coupled to the antenna for transmission. As modem RF communication systems operate in narrow frequency bands it is desirable for the transmitter to be linear, i.e. for the RF power amplifier to produce a linear power amplification of the input signal provided to it, in order to prevent distortion of the input signal and to minimize inter-channel interference. A linear RF power amplifier is an electronic circuit whose output is proportional to its input, but capable of delivering more power into a load. Preferably, the circuit does not have to produce an output which is exactly proportional, but can vary within limits, such as by � 10%.

[003J However, it is well known that when RF power amplifiers are operated at high drive levels they may become non-linear. Similar non-linearity may be caused by other operating conditions. For example, an RF power amplifier may be susceptible to an increased antenna impedance that will cause RF energy to be reflected back from the antenna into the transmitter. Changes in the antenna impedance are indicated by a parameter known as VSWR (voltage standing wave ratio). In order to protect an RF power amplifier against changes in load impedance resulting from changes of antenna impedance or VSWR, an isolator is often inserted between the

I

antenna and the power amplifier. The isolator protects the power amplifier by absorbing the reflected energy and preventing it from reaching the power amplifier.

The isolator normally directs the reflected energy to an absorptive load. Although an isolator generally works well, it adds significant cost, size, and weight to the design and construction of the communication terminal.

[004] Linear RF transmitters which do not include an isolator are known in the art.

An example is described in Applicant's GB2403086. In that prior specification the transmitter includes a Cartesian loop to provide linearization of the RF power amplifier of the transmitter. The transmitter also includes an isolator eliminator which operates to detect non-linearity as indicated when excessive adjacent channel power is present. When non-linearity is detected the isolator eliminator applies an increase in attenuation to an input baseband signal to reduce the signal level and thereby reduce the output signal power to restore linearity of the power amplifier.

10051 Due to VSWR changes, the power output capability of the power amplifier can either increase or decrease. If due to VSWR changes, the power output capability of the power amplifier is increased, then power amplifier will work at a degraded, and less than optimum, efficiency. It is therefore desirable to have a linear RF transmitter which operates at optimum efficiency and does not suffer from a degraded efficiency due to VSWR changes.

BRIEF DESCRIPTION OF Tmi DRAWINGS

10061 The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

1007] FIG. 1 depicts a block schematic diagram of a Cartesian loop transmitter, in accordance with one embodiment of the present invention.

[008] FIG. 2 depicts a block schematic diagram showing more detail of part of the transmitter depicted in FIG. 1, in accordance with one embodiment of the present invention.

[009] FIG. 3 depicts a flow chart of a method of operation for the transmitter depicted in FIG. 1, in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

[0010] By actively controlling a parameter of a supply modulation scheme the linear transmitter described operates at optimum efficiency and does not suffer from a degraded efficiency due to VSWR changes. The control of this parameter is based on a decision of a circulator elimination algorithm that is also incorporated into Cartesian loop transmitter.

[00111 FIG. 1 depicts a block schematic diagram of a Cartesian loop linear RF (radio frequency) transmitter 100 in one embodiment. The transmitter 100 includes a forward path 102 and a feedback path 104. A DSP (digital signal processor) 101 generates a baseband input digital signal containing information to provide a modulation signal to be transmitted by the transmitter 100 by RF communication.

The input baseband digital signal comprises an I (in-phase) signal component which is delivered via an I channel 105 and a corresponding Q (quadrature-phase) signal component which is delivered via a Q channel 107.

[0012] The I signal component and the Q signal component are converted to analog form by a D/A (digital to analog) converter 103. The D/A converter 103 delivers an I signal in analog form along the I channel 105 of the forward path 102 and a Q signal in analog form along the Q channel 107 of the forward path 102 in parallel with the I channel 105. The I channel 105 includes, connected to the D/A converter 103 and connected together in turn, an I channel attenuator 108, a differential amplifier 112, an amplifier/filter 116 and an upconverting mixer 120.

[00131 The upconverting mixer 120 is also connected to a local oscillator (carrier frequency synthesizer) 136. The Q channel 107 includes, connected to the D/A converter 103 and connected together in turn, a Q channel attenuator 110, a differential amplifier 114, an amplifier/filter 118 and an upconverting mixer 122. The upconverting mixer 122 is also connected to the local oscillator 136 via a 90 degrees phase shifter 158.

[0014] Output connections from the upconverting mixers 120 and 122 provide inputs to a summing junction 124 having an output connected in turn to a RF power amplifier (radio frequency power amplifier) 126 and an antenna 128.

[0015] In operation, an I signal produced digitally by the DSP 101 and converted to analog form by the D/A converter 103 is delivered to and attenuated by the I channel attenuator 108. The level of attenuation by the I channel attenuator 108 is controlled in a manner to be described later. The attenuated I signal is then delivered to the differential amplifier 112. An error control signal produced in a manner to be described from a downconverting mixer 132 is subtracted from the I signal in the differential amplifier 112. An output corrected I signal produced by the differential amplifier 112 is then amplified and filtered by the amplifier/filter 116. The amplifier/filter 116 comprises a low pass filter which serves as a slew rate limiter.

[0016] The amplified and filtered I signal produced by the amplifier/filter 116 is then mixed with a carrier frequency signal from the local oscillator 136 to upconvert the I signal from baseband to RF (radio frequency). A Q signal produced digitally by the DSP 101 and converted to analog form by the D!A converter 103 is delivered to and attenuated by the Q channel attenuator 110, which is controlled in a manner to be described later. The attenuated Q signal is then delivered to the differential amplifier 114. An error control signal produced in a manner to be described later from a downconverting mixer 134 is subtracted from the Q signal in the differential amplifier 112. An output-corrected Q signal produced by the differential amplifier 114 is then amplified and filtered by the amplifier/filter 118. The amplifier/filter 118 comprises a low pass filter which serves as a slew rate limiter. The amplified and filtered Q signal produced by the amplifier/filter 118 is then mixed by the upconverting mixer 122 with a carrier frequency signal (whose phase has been shifted by ninety degrees compared with the carrier frequency signal delivered to the upconverting mixer 120) delivered from the local oscillator 136 via the phase shifter 158 to upconvert the Q signal from baseband to RF (radio frequency). The RF signals produced as outputs by the upconverting mixer 120 of the I channel 105 and the upconverting mixer 122 of the Q channel 107 are combined at the summing junction 124, and the combined RF signal is amplified by the RF power amplifier 126 to produce an amplified RF output signal.

The amplified RF output signal produced by the RF power amplifier 126 is delivered to the antenna 128 and is sent over the air to a distant terminal (not shown) at which it is received. The antenna 128 may (at times when the transmitter 100 is not in operation) also receive an incoming RF signal sent over the air from a distant terminal (not shown) arid may deliver the received signal for processing to a RF receiver (not shown). The transmitter 100 includes no isolator between the RF power amplifier 126 and the antenna 128.

[0017] A directional coupler 130 is connected between the RF power amplifier 126 and the antenna 128 to sample the amplified RF output signal produced by the RF power amplifier 126. The directional coupler 130 is connected to the feedback path 104 at an attenuator 109. The feedback path 104 leading from the attenuator 109 is branched to include an I channel feedback loop 115 and a Q channel feedback loop 117. The I channel feedback loop 115 includes a downconverting mixer 132 connected to the attenuator 109 and also connected to the local oscillator 136. The downconverting mixer 132 is connected to provide an output signal to the differential amplifier 112. The Q channel feedback loop 117 includes a downconverting mixer 134 which is connected to the attenuator 109 and also is connected to the local oscillator 136 via a 90 degrees phase shifter 160. The downconverting mixer 134 is connected to provide an output signal to the differential amplifier 114.

[00181 In operation, the directional coupler 130 supplies the I channel feedback loop and the Q channel feedback ioop 117 with a feedback signal representing the amplified output signal. The feedback signal is attenuated by the attenuator 109. The attenuated feedback signal is downconverted into I and Q feedback baseband components by the mixers 132 and 134. The resultant baseband components are error control signals which are subtracted respectively in the differential amplifier 112 and the differential amplifier 114 from the I signal and the Q signal delivered to the differential amplifiers 112 and 114 respectively by the attenuators 108 and 110. The feedback loops 115 and 117 provide a known mechanism for maintaining linear operation of the transmitter 100 by forcing the transmitter 100 to produce an RF output which follows the undistorted I signal and Q signal supplied respectively to the differential amplifiers 112 and 114.

[0019] In alternative known forms of the forward path 102 and the feedback path 104, which will be readily apparent to those skilled in the art, the differential amplifiers 112 and 114 may be replaced by summing junctions, and an amplifier and low pass filter may be included in each of the loops 115 and 117 after the downconverting mixers 132 and 134. Such amplifiers and filters may be included instead of or in addition to the amplifier/filters 116 and 118.

[0020] The transmitter 100 includes a supply modulation (SM) control ioop 133 to improve efficiency of operation of the RF power amplifier 126. The SM loop 133 includes an j2 + Q2 calculator 119, a square root approximator 121, a supply voltage controller 127, a D/A converter 129 and a voltage regulator 111 The calculator 119 is connected to the I channel 105 and to the Q channel 107 between the DSP 101 and the D/A converter 103. The calculator 119 thereby samples the output baseb and I and Q signals produced in digital form by the DSP 101. The calculator 119 calculates the value of a parameter x given by: x = 12 + Q2 (Equation 1), where I and Q are the sampled baseband J and Q signals over a given sampling period, e.g. to give for example a sampling rate of 96 ksamples/sec. The square root approximator 121 comprises a digital processor which calculates an approximation of the square root of x for each value of x provided by the calculator 119. The square root approximator 121 uses a polynomial relationship as follows to calculate an approximation of the square root of each value of x: F(x) A2x2 + A1x + A0 (Equation 2), where A2, A and A0 are pre-determined constants. Thus, the expression for F(x) given in Equation 2 gives a polynomial (quadratic) approximation of the square root of x. The approximator 121 is a preferred band limited form of calculator to calculate the square root of x. A more exact square root calculator could be used, but would result a greater signal bandwidth. A narrower band calculator is preferred since for spectral efficiency it is desirable for the spectrum of the transmitted signal to be narrowband and thereby meet adjacent channel emission specifications defined in industry standard operating protocols.

[0021] The result of the calculation by the square root approximator 121 is provided as an output digital signal to the supply voltage controller 127. The supply voltage controller 127 also receives an input digital control signal from a non-linearity detector 125. Such a signal is the output of an algorithm as described in more detail later with reference to FIGS. 2 and 3. When such an input signal is received by the supply voltage controller 127 it causes the controller 127 to multiply an output of the approximator 119 by a multiplication constant a'. Thus, the controller 127 is operable to produce an output digital signal of the form: z = a*y (Equation 3), where: y is a value indicated by an output signal produced by the square root approximator 121; z is a value indicated by an output signal produced by the supply voltage controller 127; a' is the multiplication constant having a value indicated by a signal from the non-linearity detector 125; arid * represents multiplication.

[0022] The supply voltage controller 127 produces in accordance with Equation 3 an output digital control signal, e.g. in the form of a digital control word, which is delivered to a D/A (digital to analog) converter 129 which converts the digital control signal into an analog control signal. The analog control signal produced by the D/A converter 129 is delivered as an analog control signal to the voltage regulator 111.

The regulator 111 receives an input DC voltage from a voltage source 113 such as a battery. The analog control signal received by the regulator 111 from the D/A converter 129 causes the regulator 111 to modulate the voltage from the voltage source 113 in a known manner to produce a modulated supply voltage Vs which is applied to the RF power amplifier 126. The modulation follows the variation of the digital control signal produced by the supply voltage indicator 127. An instantaneous increase in the supply voltage V produced by the modulation causes an increase in the output power of the RF power amplifier 126 and a reduction in the supply voltage V causes a fall in the output power of the RF power amplifier 126. The control SM loop 133 improves efficiency of the RF power amplifier by varying the supply voltage Vs to suit the detected power level of the input signal.

100231 The transmitter 100 includes the non-linearity detector 125 to serve as an isolator eliminator, which is included since the transmitter 100, in accordance with one embodiment, includes no isolator between the RF power amplifier 126 and the antenna 128. However, the transmitter 100, in accordance with another embodiment, may include an isolator. The non-linearity detector 125 is connected to the I channel between the amplifier/filter 116 and the upconverter mixer 120 to sample the baseband filtered output I signal produced by the amplifier/filter 116, and is connected to the Q channel 107 between the amplifier/filter 118 and the upconverter mixer 122 to sample the baseband filtered output Q signal produced by the amplifier/filter 118. The detector 125 is also connected to the I channel attenuator 108 and the Q channel attenuator 110 to control operation of the attenuators 108 and in a manner to be further described with reference to FIG. 2.

100241 As noted earlier, the non-linearity detector 125 is also connected to the supply voltage controller 127 to provide a control signal to the supply voltage controller 127 indicating a value of a multiplication constant a' as in Equation 3. The value of the multiplication constant a' is selected in a manner to be described later with reference to FIG. 3.

10025] FIG. 2 shows in more detail an example of the non-linearity detector 125.

This example is based upon the isolator eliminator of the form described in GB 2403086 but is also adapted in accordance with an embodiment of the invention. The non-linearity detector 125 is connected to an output of the amplifier/filter 116 in the I channel 105 and an output of the amplifier/filter 118 in the Q channel 107. The nonlinearity detector 125 thereby samples in baseband form the I signal and the Q signal in the channels 105 and 107 before these signals reach the upconverting mixers and 122.

[0026] The non-linearity detector 125 detects whether there is non-linearity in operation of the RF power amplifier 126. The non-linearity detector 125 continuously samples from the information provided by the baseband I signal and the baseband Q signal corrected by the error control signals from the feedback loops 115 and 117, an on-channel baseband signal level as well as a noise (off channel signal) level at a predefined frequency offset in relation to a known desired transmission channel frequency. An example of the frequency offset at which the noise level is measured is (+ or -.) 13.5 kHz. The sampled baseband I signal and the sampled baseband Q signal are passed through a low pass filter 138 and a low pass filter 142 respectively to obtain the on-channel signal components. The sampled baseband I signal and the sampled baseband Q signal are passed through a band pass filter 140 and a band pass filter 144, in parallel respectively with the low pass filter 138 and the low pass filter 142, to obtain the noise (or off-channel signal) components. Filtered output signals from the low pass filter 138 and the low pass filter 142 are delivered to a RMS (root mean square) estimator 146. Filtered output signals from the band pass filter 140 and the band pass filter 144 are delivered to a RMS (root mean square) estimator 148.

The RMS estimator 146 comprises a digital processor which calculates the squares respectively of each consecutive incremental sample of the input I signal and the Q signal it receives. The RMS estimator 146 also sums the values of the squares obtained for each sample in a given block of N samples, where N is a pre-determined block size containing a given number of samples, e.g. from one to one hundred samples, and then divides the result by N. This gives for the block of N samples an estimate of the mean square value. Finally, the RMS estimator 146 calculates the square root of the mean square value obtained for the block of N samples giving a root mean square (RMS') value. This is an estimate of the current RMS signal level of the baseband signal having as components the I signal and the Q signal. An output signal representing a digital value of the calculated RMS signal level for each consecutive block of samples is passed from the RMS estimator 146 to a divider 150.

The RMS estimator 148 operates in a manner similar to the RMS estimator 146 to estimate an RMS value of the noise level (off-channel signal level). An output signal representing a digital value of the calculated RMS noise level for each consecutive block of samples is passed from the RMS estimator 148 to the divider 150.

10027] The divider 150 calculates for each block value provided by the RMS estimator 146 and each corresponding block value provided by the RMS estimator 148 a ratio of the value of the RMS on-channel signal to the value of the RMS noise (off channel signal) level. An output signal providing a signal to noise ratio value for each block considered by the divider 150 is provided by the divider 150 to a comparator 152. The comparator 152 provides an output signal having a LOW state if the determined signal to noise ratio indicated by the output signal from the divider is above a predeflned threshold THIR. The comparator 152 provides an output signal having a HIGH state if the determined signal to noise ratio indicated by the output signal from the divider 150 is equal to or below a predefined threshold TER.

[00281 If the comparator 152 produces an output signal having a LOW state it indicates that the transmitter 100 is operating linearly. If the comparator 152 produces an output signal having a HIGH state it indicates non-linearity of the RF power amplifier 126 of the transmitter 100 that needs to be corrected for. The comparator 152 is connected to a microprocessor 154 which receives the output signal produced by the comparator 152 and initiates corrective action when the output signal from the comparator 152 has a HIGH state. In some circumstances to be described in detail with reference to FIG. 3, if the output signal from the comparator 152 has a LOW state, the microprocessor may or may not initiate corrective action. The microprocessor 154 is connected in turn to the I channel attenuator 108 and the Q channel attenuator 110 and also to the supply voltage controller 127. In some circumstances to be described in detail with reference to FIG. 3, if the output signal from the comparator 152 has either a HIGH or LOW state, the microprocessor 154 provides a control signal to the supply voltage controller 127 to produce a change in output signal from the controller 127 leading to an incremental change by the regulator 111 to a level of supply voltage Vs provided to the RF power amplifier 126.

100291 In some circumstances, when the microprocessor 154 applies a control signal to the controller 127, the microprocessor 154 also applies a delay to issue of any further control signal based on a further LOW state output signal from the comparator 152. This delay is applied to allow the transmitter 100 to settle after a step increase in the multiplication constant a' has been applied to the controller 127. The delay is implemented by the microprocessor 154 not reading results of the comparator 152 for pre-deflned period of time. In one embodiment, the delay is comparable to the maximum amount of time it would take for a user to change the antenna impedance, indicated by a parameter known as VSWR change time constant. The VSWR change time constant can be calculated for a given antenna, or device, based upon user testing ajid determining how much time it would take a user to change the antenna impedance of a given device, typically this happens when a user touches or grasps the device. In one embodiment, the delay is between 1 and 1000 milliseconds. The microprocessor 154 stores a value indicating a multiplication constant a' setting in a memory 156 to record the current value of the multiplication constant a' being applied to the controller 127.

[0030] FIG. 3 is a flow chart showing a method 200 used in operation by the transmitter 100. The method 200 is an algorithm which runs in every transmission time slot, e.g. as indicated by a controller (not shown) which controls functional operations of the transmitter 100. The method 200 thus begins at a step 201 which is a start of a transmission time slot. Next, a non-linearity detector algorithm run by the microprocessor 154 begins in a step 203. Next, a multiplication constant a' having a nominal value will be programmed in the supply voltage controller 127 for a given transmitter 100 power control level 207. The power control level 207 is determined by the gain of the feedback path. To keep the Cartesian loop linear RF (radio frequency) transmitter 100 open loop gain constant while changing the output power level of the transmitter 100, the forward and feedback path gains are varied simultaneously when the power control level 207 is varied. For example in a TETRA protocol, the power control level is varied in 5 dB steps.

[0031] In a decision step 209, the microprocessor 154 decides whether or not non-linearity is detected based on the current state of the output signal from the comparator 152. The decision is NO' when the signal received by the microprocessor 154 from the comparator 152 has a LOW state indicating linearity of operation of the transmitter 100, and the decision is YES' when the signal received by the microprocessor 154 from the comparator 152 has a HIGH state indicating non-linearity of operation of the transmitter 100. If the decision taken by the microprocessor 154 in step 209 is YES' the method 200 returns to step 203. If the decision taken by the microprocessor 154 in step 205 is NO', i.e. that linearity is detected, a decision step 211 follows.

[0032] In decision step 211, the microprocessor 154 decides whether the multiplication constant a' (referred to earlier with reference to Equation 3) that is provided by the microprocessor 154 to the supply voltage controller 127 is at a pre-determined minimum value. The pre-determined minimum value of the multiplication constant a' corresponds to a pre-determined minimum value of the supply voltage V. If the decision taken by the microprocessor 154 in step 211 is NO', i.e. the microprocessor 154 determines that a minimum value of the multiplication constant a' has not been reached, a step 213 follows in which the microprocessor 154 issues a control signal to the supply voltage controller 127 with a multiplication constant a' which correspond with a lower value of the supply voltage V, by one incremental step. If the decision taken by the microprocessor 154 in step 211 is YES', i.e. the microprocessor 154 determines that a minimum value of the multiplication constant a' has already been reached, and the method 200 returns to step 209.

[00331 After step 213, once the microprocessor 154 issues a control signal to the supply voltage controller 127, the microprocessor 154 then initiates a delay to issue of any further control signal based on a further LOW state output signal from the comparatoT 152, at step 215. This delay is initiated to allow the transmitter 100 to settle after a step increase in the value of the multiplication constant a' has been applied. The delay is implemented by the microprocessor 154 not reading results of the comparator 152 for pre-defined period of time. The microprocessor 154 stores a value indicating multiplication constant a' setting in memory 156 to record the current value of the multiplication constant a' being applied to the controller 127. In one embodiment, the delay is comparable to a maximum VSWR change time constant delay. The maximum VSWR change time constant is comparable to the amount of time that the VSWIR can change, which is typically on the order of milliseconds and can be determined through testing by determining the average amount of time that it takes a person to touch a phone.

[0034] After step 215, a decision step 217 is applied. In the decision step 217, the microprocessor 154 decides whether or not non-linearity is detected. This is the same as in step 209 but is based on a later result from the comparator 152. If the decision taken by the microprocessor 154 in step 217 is NO', i.e. that linearity is detected, the method 200 returns to step 211. If the decision taken by the microprocessor 154 in step 217 is YES', i.e. that non-linearity is detected, a step 219 follows in which the microprocessor 154 issues a control signal to the supply voltage controller with a multiplication constant a' which correspond with a higher value of the supply voltage V, by one incremental step. After step 219, the method 200 returns to decision step 209.

[0035] In steps 213 arid 219, the value for the multiplication constant is changed to compensate for the lack of an isolator in the transmitter 100. In one embedment, the control signal to the supply voltage controller 127 changes the multiplication constant a' with a value that corresponds with either a lower or higher value for the supply voltage Vs, by one incremental step. However, the multiplication constant a' may be changed by an amount which is not incremental, but rather by an amount which varies in degree from one time to another.

[0036] As an example of applying steps 211, 213, 217, and 219 the multiplication constant a' used by the supply voltage controller 127 may initially be set at a = 1.3 by factory tuning, this is the nominal value for a' for a given power control level. This value of a' is initially applied each time the method 200 runs. Then there may be different gradually increasing or decreasing values of the constant a' applied in turn by the supply voltage controller 127, the values each time being as indicated by a control signal from the microprocessor 154 to the supply voltage controller 127.

[0037] These different values may for example be a' = 1.5; 1.4; 1.3; 1.2; 1.1; and 1.

The last value, 1, may be a minimum allowed value of the multiplication constant a' corresponding to a minimum allowed value of the supply voltage Vs. Thus, each time step 211 produces a NO' result, the value of the multiplication constant a' indicated by the microprocessor 154 to the supply voltage controller 127 will be gradually decreased in an iteration of step 213 until a minimum value for the multiplication constant a' is reached, when step 209 is alternatively applied instead of step 213.

Additionally, each time step 217 produces a YES' result, the value of the multiplication constant a' indicated by the microprocessor 154 to the square root approximator 121 will be increased in an iteration of step 219 until linearity is detected, when step 211 is alternatively applied instead of step 219.

[0038] In a modified form of the transmitter 100, the calculator comprising the square root approximator 121 (and optionally the calculator 119) and the supply voltage controller 127 may be combined in a single processor.

[0039] Thus, by the method 200, when linearity is detected in step 209 the microprocessor 154 issues a control signal to the supply voltage controller 127 which, by causing the regulator 111 to provide an decrease in the supply voltage V5, causes the output power capability of the RF power amplifier 126 to be decreased. This corrective action is taken if it is still possible, i.e. if a minimum value of Vs has not been reached.

[0040] Changes in the supply voltage Vs in the manner described may beneficially be achieved more rapidly than changes which occur in the VSWR as experienced by the RF power amplifier 126. This allows changes in the power level of the RF power amplifier 126 due to changes in the VSWR to be minimized. This improves the efficiency of the RF power amplifier 126, and as a result the working point of the RF power amplifier 126 will be closer to the saturation point of the RF power amplifier 126.

[0041] The tuning of the RF power amplifier 126 may be set initially, e.g. in a factory in which the transmitter 100 is produced and tested, at a level assuming a nominal load termination employed instead of the antenna 128, e.g. a 50 ohm termination.

This sets the initial nominal operating conditions under which the algorithm comprising the method 200 is applied, including an initial level of the multiplication constant a' indicated by the control signal provided by the microprocessor 154 to the supply voltage controller 127.

[0042] The transmitter 100 is suitable for use in an RF communication terminals for use in a number of communication applications, especially those that operate in narrow bandwidths and demand a high level of linearity. Of particular interest is use in a terminal in which the transmitter operates in accordance with pre-defined industry standard operating protocols or procedures such as the TETRA (Terrestrial Trunked Radio) standard protocols as defined by ETSI (European Telecommunication, such as TETRAI, TBTRA2, and North American IE{PD radios.

[0043] In various embodiments of the present invention, the disclosed methods may be implemented as a computer program product for use with a computer system.

Such implementations may include a series of computer instructions fixed either on a tangible medium, such as a computer readable medium (e.g., a diskette, CD-ROM, ROM, or fixed disk) or transmittable to a computer system, via a modem or other interface device, such as a communications adapter connected to a network over a medium. The medium may be either a tangible medium (e.g., optical or analog communications lines) or a medium implemented with wireless techniques (e.g., microwave, infrared or other transmission techniques). The series of computer instructions embodies all or part of the ftinctionality previously described herein with respect to the system. Those skilled in the art should appreciate that such computer instructions can be written in a number of programming languages for use with many computer architectures or operating systems. Furthermore, such instructions may be stored in any memory device, such as semiconductor, magnetic, optical or other memory devices, and may be transmitted using any communications technology, such as optical, infrared, microwave, or other transmission technologies. It is expected that such a computer program product may be distributed as a removable medium with accompanying printed or electronic documentation (e.g., shrink wrapped software), preloaded with a computer system (e.g., on system ROM or fixed disk), or distributed from a server or electronic bulletin board over the network (e.g., the Internet or World Wide Web). Of course, some embodiments of the invention may be implemented as a combination of both software (e.g., a computer program product) and hardware. Still other embodiments of the invention are implemented as entirely hardware, or entirely software (e.g., a computer program product).

[0044] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less thaii all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

[00451 While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that other embodiments and implementations are possible within the scope of the invention. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.

Claims

CLAIMS1. A method of adjusting an output level of a transmitter in a digital radio system, the method comprising: programming a multiplication constant having a nominal value in a supply voltage controller for a given power control level; measuring an on-channel baseband signal level and a noise level of a signal at a predefined frequency offset; calculating a ratio of the noise level to the on-channel baseband signal level to determine if the signal is linear and if the signal is determined to be linear, changing the multiplication constant to decrease the on-channel baseband signal level.
2. The method of claim 1, further comprising if the signal is determined not to be linear, then reprogramming the multiplication constant for the given power control level.
3. The method of claim 1, wherein the transmitter is operable to provide communications in at least one of TETRA, GSM, or IDEN communication systems.
4. The method of claim 1, further comprising if the signal is determined to be linear, determining if the multiplication constant is a minimum value before changing the multiplication constant.
5. The method of claim 1, wherein the multiplication constant is changed to compensate for the lack of an isolator in the transmitter.
6. The method of claim 4, further comprising if the multiplication constant is not the minimum value, changing the multiplication constant to decrease the signal level.
7. The method of claim 6, further comprising: inserting a delay after changing the multiplication constant; re-measuring the on-channel baseband signal level and noise level at the predefined frequency offset; and re-calculating a ratio of the re-measured noise level to the re-measured on-channel baseband signal level to determine if the signal using the changed multiplication constant is linear.
8. A method of adjusting an output level of a transmitter in a digital radio system, the method comprising: determining whether a radio frequency power amplifier of the transmitter produces a linear output signal, wherein if the signal is determined to be linear, then decreasing a voltage supplied to the radio frequency power amplifier if a multiplication constant used in a supply voltage controller that controls the radio frequency power amplifier through the voltage is not at a predetermined minimum value, wherein the voltage supplied to the radio frequency power amplifier is proportional to the multiplication constant.
9. The method of claim 8, further comprising if the voltage supplied to the radio frequency power amplifier is decreased, inserting a delay, and then after the delay, determining again whether the signal produced by the radio frequency power amplifier of the transmitter is linear.
10. The method of claim 9, further comprising after the delay, if the signal is determined to be non-linear, increasing the voltage supplied to the radio frequency power amplifier.
11. The method of claim 8, wherein the multiplication constant is changed to compensate for the lack of an isolator in the transmitter.
12. The method of claim 8, further comprising before determining whether the signal produced by the radio frequency power amplifier of the transmitter is linear, programming a nominal multiplication constant in the supply voltage controller so that the supply voltage controller produces a nominal supply voltage.
13. The method of claim 12, further comprising if the signal is detennined not to be linear, reprogramming the nominal multiplication constant for a given power control level.
14. The method of claim 8, wherein the transmitter is operable to provide communications in at least one of TETRA, GSM, or IDEN communication systems.
15. The method of claim 8, further comprising if the signal using the changed multiplication constant is determined to be non-linear, changing the multiplication constant to increase a signal level of the signal.
16. A method of adjusting an output level of a transmitter in a digital radio system, the method comprising: calculating whether a radio frequency power amplifier of the transmitter produces an output signal that is linear, wherein if the signal is determined to be linear, then: determining if the radio frequency power amplifier is operating with a minimum supply voltage, wherein if the radio frequency power amplifier is not operating with the minimum supply voltage, then: changing a multiplication constant used in a supply voltage controller that controls supply of the supply voltage to the power amplifier so that the supply voltage is reduced.
17. The method of claim 16, further comprising upon reducing the supply voltage, calculating whether the signal produced by the radio frequency power amplifier of the transmitter is linear, wherein if the signal is determined to be non-linear, then changing the multiplication constant used in the supply voltage controller so that the supply voltage is increased.
18. The method of claim 17, further comprising upon increasing the supply voltage, calculating whether the signal produced by the radio frequency power amplifier of the transmitter is linear.
19. The method of claim 16, further comprising before calculating whether the signal produced by the radio frequency power amplifier of the transmitter is linear, programming a nominal multiplication constant in the supply voltage controller so that the supply voltage controller produces a nominal supply voltage.
20. The method of claim 16, wherein the transmitter is operable to provide communications in at least one of TETRA, GSM, or DEN communication systems.