GB2455555A

GB2455555A - A receiver amplifier with adaptive bias for large dynamic range

Info

Publication number: GB2455555A
Application number: GB0724370A
Authority: GB
Inventors: Haim Malka; Moshe Ben-Ayun; Oleg Chermoshniuk; Yaniv Salem
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2007-12-14
Filing date: 2007-12-14
Publication date: 2009-06-17
Anticipated expiration: 2027-12-14
Also published as: GB0724370D0; GB2455555B

Abstract

A strong off channel signal can cause compression in the receiver amplifier of a mobile TETRA terminal, thereby distorting on-channel signals and reducing dynamic range. The signal-to-noise ratio (SNR) and noise figure are reduced because the gain for on-channel signals falls. To counteract these effects the bias current is increased when compression is sensed trough a fall in the bias node voltage VB (figure 2). For example, where the device 101 is an NPN bipolar transistor, a strong RF signal at node 103 leads to a fall in the DC voltage at the base node. The comparator 137, which may have hysteresis, responds to a fall in VB by signalling the current controller 131 to supply more bias current to the amplifying device 101.

Description

TITLE: AMPLIFIER CIRCUIT FOR USE IN A RADIO FREQUENCY

RECEIVER AND A METHOD OF OPERATION

TECHNICAL FIELD

The technical field relates generally to an

amplifier circuit for use in a radio frequency (RF) receiver and a method of operation of the amplifier circuit. In particular, the technical field relates to an amplifier circuit and method for use in a receiver for use in a mobile communication terminal.

BACKGROUND

Mobile communication terminals designed for certain specialist applications require a receiver providing a high performance. Such terminals may operate according to a wireless communication protocol which sets a demanding performance specification for the transmitter and the receiver of the terminal. For example, terminals operating according to the TETRA standard defined by the European Telecommunications Standards Institute (ETSI) handle signals which have a * combination of amplitude and phase modulation, specifically Differential Quadrature Phase Shift Keying (DQPSK), which are in a narrow-band communication channel. Often, the receiver employs at least one low noise amplifier (LNA), especially in a front-end part of its chain of processing components. In some reception situations, a strong off-channel interferer signal may be present as well as a weaker wanted on-channel signal. The off-channel interferer signal may cause operation of the LNA to be driven into an unwanted condition of compression. In such a condition, the LNA has an amplifying characteristic (transfer or small signal gain characteristic) which is changed from a normally linear form to a non-linear form. As a result, the wanted on-channel signal can become distorted.

When operation of the LNA is in compression, the small signal gain is reduced as a function of the amplitude of the off-channel interferer signal. The reduction in small signal gain causes degradation in the signal to noise ratio (SNR) and noise figure of the receiver. The noise figure is a known measure of the degradation of the SNR. The degradation in the SNR and noise figure impacts strongly on performance.

Performance of the receiver is degraded especially where the received signal is amplitude modulated.

Furthermore, the degradation of the SNR and noise figure caused by the off-channel interferer signal may cause phase errors to be introduced in the wanted signal.

Furthermore, when the LNA is in compression the dynamic range of the receiver is also reduced. The dynamic range is the range of input signal powers that the receiver is capable of handling. For example, in a wide dynamic range receiver for use in a TETRA terminal (a terminal operating according to the TETRA standard), the power of the received signal may be in a wide range typically from about -120 dbm to about +10 dBm.

Reduction of the dynamic range when operation of the LNA is in compression is therefore undesirable.

Methods are known to attempt to solve the problem of an amplifier such as an LNA being driven into a condition of compression, especially by a strong off-channel interferer signal as described above.

In one such known method, the amplification characteristic of the RF amplifier is monitored indirectly by monitoring the Received Signal Strength Indication (RSSI) of the input RF signal. From the monitored RSSI it is possible to estimate when the characteristic will go into a condition of compression, at a position on the characteristic known in the art as the compression point'. The compression point is one of the parameters that changes when the RSSI changes.

Thus, when the measured RSSI indicates that the compression point is reached, a change in electrical bias may be applied so that the compression point may be raised in order to maintain linearity of the amplifying characteristic for a higher power signal.

For example, the compression point of an LNA may be raised by increasing a bias current applied to the LNA.

In another such known method, at least one programmable step attenuator is employed in the receiver line-up before the LNA. The output RF power of the signal from the LNA after amplification is monitored and, where the output power becomes excessive, a control signal is fed to the attenuator which in response reduces the amplitude and power of the received input RF signal before it is applied to the LNA.

The known methods do not provide totally satisfactory solutions to the problem described above.

For instance, RSSI measurements do not give a suitably satisfactory indication of the response of the amplifying device to changes in the input signal. Where step attenuators are used in the receiver chain, the attenuators can cause a degradation in the noise figure of the receiver.

Thus, there exists a need for an amplifier circuit and a method of operation, especially for use in an RF receiver for mobile communications, which addresses at least some of the shortcomings of past and present amplifier circuits and methods.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The accompanying drawings, in which like reference numerals refer to identical or functionally similar items throughout the separate views which, together with the detailed description below, are incorporated in and form part of this patent specification and serve to further illustrate various embodiments of concepts that include the claimed invention, and to explain various principles and advantages of those embodiments.

In the accompanying drawings: FIG. 1 is a circuit diagram, partly in block schematic form, of an amplifier circuit.

FIG. 2 is a graph of output RF power and a monitored voltage plotted versus input RF power for the amplifier circuit of FIG. 1.

FIG. 3 is a block circuit diagram of an illustrative hysteresis comparator which may be used in the amplifier circuit of FIG. 1.

FIG. 4 is a graph of output voltage versus input voltage illustrating operation of the hysteresis comparator of FIG. 3.

FIG. 5 is a block circuit diagram of an illustrative circuit useful as a current controller and voltage, source in the amplifier circuit of FIG. 1.

FIG. 6 is a flow chart of a method which summarises operation of the amplifier circuit of FIG. 1.

Skilled artisans will appreciate that items shown in the accompanying drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the items may be exaggerated relative to other items to assist understanding of various embodiments. In

addition, the description and drawings do not

necessarily require the order illustrated. Apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the various embodiments so as not to

obscure the disclosure with details that will be

readily apparent to those of ordinary skill in the art having the benefit of the description herein. Thus, it will be appreciated that for simplicity and clarity of illustration, common and well-understood items that are useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of these various embodiments.

DETAILED DESCRIPTION

Generally speaking, pursuant to the various embodiments to be described, there is provided an improved amplifier circuit for use in an RF receiver, particularly a receiver for use in a mobile communications terminal, and a method of operation of the amplifier circuit. The amplifier circuit includes an amplifying device having: (1) an input terminal for applying an input RF signal to the device; and (ii) an output terminal for delivering an amplified output RF signal from the device, a bias arrangement for applying an electrical bias to the input terminal of the amplifying device to control an amplifying characteristic of the amplifying device, an electrical controller for varying the electrical bias to vary a position of operation on the amplifying characteristic, and a control loop for controlling the electrical controller, the control loop including a comparator for comparing a monitored voltage indicative of the electrical bias with a reference value to produce an output signal which changes when a change in the monitored voltage indicates a condition of compression of the amplifying characteristic, and, operably connected to the comparator, a control input to the electrical controller for applying to the electrical controller the output signal from the comparator to control the electrical bias.

The electrical controller of the improved amplifier circuit may be a current controller. The control input may be operable to control a level of output current delivered by the electrical controller.

The monitored voltage in the improved amplifier circuit may be a DC voltage developed in the bias arrangement, e.g. at an output of the electrical controller. The comparator may be operable to detect a change of the DC voltage developed at the output of the electrical controller relative to an initial value of the voltage and to produce a change in the output signal when the change of the DC voltage reaches a threshold.

The improved amplifier circuit is able to detect accurately a condition of compression in the amplifying characteristic (transfer characteristic) of the amplifying device when a strong input RF signal is applied, particularly an unwanted off-channel interferer signal in a narrow-band receiver. Upon such detection, the control loop automatically changes the electrical bias, e.g. increases bias current, so that operation of the amplifying device is rapidly taken out of compression. The control loop is able to return the electrical bias to an earlier level (prior to detection of compression) when the level of the input RF signal falls.

Thus, the improved amplifier circuit is able to provide accurate detection of a compression point being reached in operation, and automatic adjustment of operation of the amplifying device accordingly, without having to the monitor an amplified RF signal produced by the amplifying device or an input signal applied to the device. This allows a rapid response to changes in the level of the input signal, especially where those changes might themselves occur rapidly, e.g. in a receiver operating according to a time slotted sequence wherein signals are received in individual time slots, such as in a TETRA receiver wherein the signal time slots have a duration of 14.17 milliseconds.

When the amplifier circuit is already in a state in which an electrical bias current applied to the amplifying device current is high, caused by the presence of a strong off-channel interferer signal, and the strength of the interferer signal falls, the current may be reduced in order to avoid wasting energy. Generally, there may be no need for urgency in reducing the current.

Thus, the improved amplifier circuit is beneficial in that can it monitor directly what suitable level is required for the bias current of the amplifying device in order to maintain linearity of operation and can make any required changes to the bias current automatically and, where appropriate, rapidly.

Known solutions, e.g. as described in the Background section earlier, to the problem of increased signal strength leading to compression require additional hardware and software for implementation in an amplifier circuit. In contrast, suitable implementation of the improved amplifier circuit may be obtained essentially by use of additional hardware elements only.

Those skilled in the art will appreciate that these recognized advantages and other advantages described herein are merely illustrative and are not meant to be a complete rendering of all of the advantages of the various embodiments of the invention.

Referring now to the accompanying drawings, and in particular to FIG. 1, there is shown a circuit diagram, partly in block schematic form, of an illustrative amplifier circuit 100 in accordance with an embodiment.

The circuit 101 includes an amplifying device 101. The amplifying device 101 has an input terminal 103, an output terminal 105 and a further terminal 107. The amplifying device 101 may be a solid state, e.g. semiconductor, device such as a transistor having a known construction. The amplifying device 101 may for example be a bipolar junction transistor, which may be a p-n-p or an n-p-n bipolar transistor. In that case, the input terminal 103 is the base electrode, the output terminal is the collector electrode and the further electrode is the emitter electrode of the transistor. Persons skilled in the art will be very familiar with such devices and with the voltage polarities required to operate them.

An input RF signal is applied to the input terminal 103 of the amplifying device 101 through an inductor 109 and a capacitor 111. The inductor 109 and the capacitor 101 provide a suitable input impedance for impedance matching purposes. An amplified output RF signal is delivered from the output terminal 105 of the amplifying device 101 through an output circuit comprising a capacitor 115 and an inductor 117 connected together in series and a capacitor 119 connected between the junction of the capacitor 115 and the inductor 117 and ground. The output circuit provides a suitable impedance for impedance matching purposes.

A voltage source 121 provides a DC supply voltage V2. The voltage source 121 is connected to the output terminal 105 of the amplifying device 101 through a resistor 123 connected in series with an inductor 125.

The further terminal 107 is connected through an inductor 113 to ground. A DC current path runs from the voltage source 121 to ground via the resistor 123, the inductor 125, the amplifying device 101 and the inductor 113. The DC current path includes a controllable current path which runs through the amplifying device 101 between the output terminal 105 and the further terminal 107. For example, where the amplifying device 101 is an n-p-n bipolar junction transistor the current path runs from the collector electrode to the emitter electrode. Current in the controllable path is controlled in a known way by an electrical signal applied to the input terminal 103 of the amplifying device 101. For example, where the amplifying device 101 is an n-p-n bipolar junction transistor, current in the controllable path is controlled by an electrical signal applied to the base electrode of the transistor. The inductors 113 and 125 provide isolation of the output RF signal delivered at the output terminal 105 from components of the DC current path.

A bias arrangement 134 provides a further DC current path from the voltage source 121 to the input terminal 103 of the amplifying device 101. The bias arrangement 134 includes a current controller 131 connected to the voltage source 121, a resistor 133 connected to the current controller 131 and an inductor connected between the resistor 133 and the input terminal 103. The inductor 135 isolates the input RF signal from components of the bias arrangement 134.

Capacitors 127 and 129 are connected in parallel between the voltage source 121 and ground. The capacitors 127 and 129 provide known decoupling and filtering functions.

In operation of the amplifier circuit 100, the input RF signal applied to the input terminal 103 is amplified by the amplifying device 101 to form the amplified output RF signal delivered from the output terminal 105. The amplifying device 101 normally operates in a linear mode in which the device 101 has an amplification characteristic (transfer characteristic or small signal gain) in which the power of the output RF signal is a linear function of the power of the input RF signal. The DC current delivered from the current controller 131 via the resistor 133 and the inductor 135 is a bias current which serves to adjust operation of the amplifying device 101 so that, for an input RF signal applied to the input terminal 103, a suitable amplification characteristic and a suitable operating position on the amplification characteristic is obtained in a known manner. The operating position is selected to be in a linear region of the amplification characteristic below a compression point of the characteristic. As noted earlier, the compression point is in a region of the characteristic where the characteristic becomes non-linear.

A comparator 137 is connected to an output of the current controller 131 to monitor an output voltage V developed in the bias arrangement 134 at the output of the current controller 131. As explained later, particularly with reference to FIG. 2, changes in the monitored voltage yE can be employed give a good direct indication of when operation of the amplifying device 101 is reaching its compression point.

The comparator 137 compares the monitored voltage VB, or a change in the monitored voltage V relative to an initial value of the voltage VB (when the value of the voltage VB is at a maximum), with a threshold voltage. The comparator 137 produces an output control signal which is delivered to a control input 138 of the current controller 131 to provide automatic control of the current controller 131. The threshold voltage used by the comparator 137 is selected to detect and indicate the condition when the operation of the amplifying device 101 reaches the compression point of its amplification characteristic caused by an increase in strength of the input RF signal. When that condition is detected, the output control signal produced by the comparator 137 changes causing the current controller 131 to produce an increased output DC current for delivery as a bias current to the input terminal 103 of the amplifying device 101. The increased bias current so delivered changes the amplification characteristic of the amplifying device 101 and the operating position on the characteristic so that the operating position remains on a linear part of the characteristic.

When the strength of the input RF signal falls, the output control signal produced by the comparator 137 and delivered to the control input 138 changes again causing the current controller 131 to produce an output DC current which is reduced, e.g. to its original level. The reduced current again changes the operation of the amplifying device 101 to its original operation. The operating position remains on a linear part of the characteristic but the characteristic is changed, e.g. to its original, so that less current and less energy is consumed during operation of the amplifying device 101.

The comparator 137 may have a response in which it produces only two possible output signals, one to indicate normal or low' current delivery by the current controller 131 and one to indicate high' current delivery by the current controller 131 when the monitored voltage VE indicates that the device 101 has reached its compression point. However, operation of the comparator 137 is not limited to producing only two possible output signals. The comparator 137 may produce a range of signals each indicating a detected level of the voltage VB. The current controller 131 may in response produce a range of DC currents accordingly.

When the current controller 131 produces an increase in the current it delivers, the monitored voltage VR falls (as illustrated later with reference to FIG. 2) . Conversely, when the current controller 131 produces a reduction in the current it delivers, the monitored voltage VB rises. In order to avoid constant changes of the operating point of the amplifying device 101, the comparator 137 may have a hysteresis response.

By such a response, a change in the output control signal produced by the comparator 137 occurs only when a change in an input signal applied to the comparator 137 (obtained from the monitored voltage V13) is a minimum change. The threshold employed by the comparator 137 may have a value which changes between a first threshold value and a second threshold value when the output signal changes, so that a further change in the output signal requires a further change in the input signal equivalent to the difference between the first and second threshold values. Such operation is illustrated later with reference to FIGS. 3 and 4.

A re-set controller 139 is connected to the comparator 137. The re-set controller 139 may provide a re-set signal to the comparator 137. The re-set signal re-sets the comparator 139 so that it delivers a signal to the current controller 131 which causes the current controller 131 to produce a low output current. The comparator 137 may apply the re-set signal at start-up of amplifier circuit 100, e.g. which occurs upon start-up of a receiver (not shown) in which the amplifier circuit 100 is employed. The comparator 137 may apply the re-set signal periodically during use of the amplifier circuit 100. For example, where the amplifier circuit 101 is used in a receiver operating using a time slotted protocol, e.g. where the receiver is in a TETRA terminal, the re-set signal may be issued by the re-set controller 139 at the end of each time slot in which an RF signal is received.

Use of the monitored voltage VB to provide a detection of the condition of compression of the amplification characteristic in operation of the amplifying device 101 in the manner described above will now be further explained. The monitored voltage V referred to above, here written as VBDC. is given by: VBL)(. = VBI)(.Q -where VBDCQ is a quiescent level of VBDC iith no applied RF signal and AVis the incremental change of VBDC with an RF signal applied. The incremental change AV is a measure of a change in power of an input RF signal having an input level and is given by: = Vtlog[1,,(X)] where X is V1/Vt, and Vt is the thermal voltage which is a known characteristic of the amplifying device 101 which is a constant for a given temperature, e.g. approximately 26 mV at a temperature of 300K, I,1(X) is a coefficient which has a dependence on X in the form of a known modified Bessel function, and log represents a natural logarithm. Thus, AV is a monotonic function of X and therefore a function of the input level Vj of the input signal.

FIG. 2 is a graph 200 illustrating the above analysis. FIG. 2 shows two curves 201 and 203 obtained by simulating the analysis for a given input RF signal applied to the amplifying device 101. Typical operational conditions were used in the simulation to give the curves 201 and 203, namely provision of an initial bias current to the amplifying device 101 of 2.6mA at room temperature (20C) and an input signal frequency of 400 MHz. Other conditions give similar curves. The curve 201 is a plot of the monitored voltage V as referred to earlier with reference to FIG. 1, measured in volts, versus the input RF power of the input RF signal measured in dBm. The scale of the voltage V for the curve 201 is shown on the right side of the graph 200. The curve 203 is a plot of the output RF power of an output RF signal obtained after amplification by the amplifying device 101 versus the input RF power of the same RF signal before amplification measured in dBm. The scale of the output RF power is shown on the left side of the graph 200.

The curve 203 represents the amplification characteristic of the amplifying device 101 for the particular conditions under which the curve 203 was measured. The curve 201 represents the corresponding value of the monitored voltage V as a function of the RF power of the input RF signal for the same conditions. Inspection of FIG. 2 shows that the curve 203 is linear for values of the input RF power below (smaller than) about -15 dEm. When the value of the input RF power is above (greater than) about -15 dbm, the curve 203 is seen to be non-linear. Thus, when the value of the input power reaches about -15 dBm, a compression point of the curve 203 may be considered to be reached. The curve 201 is approximately horizontal, i.e. shows little change in output RF power as a function of input RF power, for values of the input power below about -15 dBm. When the value of the input power is above about -15 dBm, the curve 201 is seen to fall rapidly. Thus, the curve 201 has a change in shape at about -15 dB which corresponds directly to the compression point of the curve 203. Thus, yE is relatively constant whilst the amplification stage comprising the amplifying device 101 is in the linear region of its amplification characteristic, curve 203.

When the input signal starts to drive the amplification stage into compression, the voltage VB correspondingly starts to fall in a monotonic manner as in the curve 201. Thus, detection of a change in the shape of the curve 201 from horizontal to falling gives a good direct indication of reaching the compression point of the curve 203.

The threshold voltage employed in the comparator 137 can be selected so that it represents a particular point on the curve 201 which is considered to correspond to a compression point of the curve 203. For example, the threshold voltage may be selected to indicate that a minimum fall in the monitored voltage VE has been detected.

FIG. 3 is a block circuit diagram of an illustrative comparator 300 which may be used as the comparator 137 in the amplifier circuit 100 of FIG. 1.

The comparator 300 is one of various comparators which will be familiar to those skilled in the art and which may be employed as the comparator 137 (FIG. 1). The comparator 300 is a hysteresis comparator which includes a differential amplifier 301 having a bias current in a path between a terminal 303 (e.g. connected to the voltage source 121 shown in FIG. 1) at which the voltage V is applied and ground. The differential amplifier 301 has inputs 305 and 307 and an output 309. An input voltage yIN being monitored (related to the voltage VB indicated in FIG. 1) is applied from a terminal 313 to the input 305 via a resistor 311. The input 307 is connected through a resistor 317 to the terminal 303 providing the supply voltage V and through a resistor 319 to ground. A reference voltage VREF having a value between V and ground potential is thereby developed at the input 307.

The input 305 is connected to the output 309 via a resistor 321. The output 309 is connected to an output terminal 325 via a resistor 323. An output voltage VOUT is obtained at the output terminal 325.

FIG.4 is a graph 400 which illustrates operation of the comparator 300. The graph 400 shows the output voltage VOUT obtained as a function of the input voltage VIN for the comparator 300. In this case, VIN may be considered to indicate the amount which the monitored voltage V has fallen from its initial value; thus an increase in the value of VIN is equivalent to a fall in the value of V. Operation of the comparator 400 follows a plot 401. When operation first begins, the input voltage VIN is below a value of a lower threshold VTL and also below a second, higher threshold VTH. The output voltage VOIJT is at a (relatively) low level VOL.

When the input voltage yIN becomes greater than VTL but is still less than V*1.1 the plot 401 remains on a lower horizontal portion 403, and the output voltage V(u1' remains at the low level V11. When the input voltage VIN becomes equal to or greater than VTH, the plot 401 jumps upward along a vertical portion 405, and the output voltage VOUT is switched to a (relatively) high level Vc)H. The output voltage VOUT remains at the high level VOH whilst the input voltage remains not less than V1.1. When the input voltage VIN becomes less than V1.11 but is still greater than VTJ,, the plot 401 remains on an upper horizontal portion 407, and the output voltage remains at the high level VOH. When the input voltage VIN falls further to become equal to or less than VTL, the plot 401 jumps downward along a vertical portion 409, and the output voltage is switched back to the low level VOL. Thus, the horizontal portions 403 and 407 of the plot 401 represent an applied hysteresis in the changing of the output voltage VOUT relative to the input voltage VIN.

It is to be noted that the values of V011, VOL, VTL and VTH for the comparator 300 are given by the following relationships: VTH = [ (R3u + R21) X VREF -(R31 X VOL) I /R321 VTL = [ (R311 + R371) x VREF -(R311 x VOH) I /R321 where R311 is the resistance of the resistor 311 and R321 is the resistance of the resistor 321. Suitable values of V011, VOL, VTT, and VTH may therefore be obtained by selection of the values of the resistances R311 and R371 and of the reference voltage VRII,.

The reference voltage VREF is given by: VREF = X R1 / (R31q + R311) where R.17 is the resistance of the resistor 317 and R31q is the resistance of the resistor 319. A suitable value of VREF may therefore be obtained by selection of the values of the resistances R317 and R.q.

Any of the resistors shown in FIG. 3 may have a resistance value which is adjustable for additional flexibility of design of the comparator 300.

Re-set of the comparator 300 by the reset controller 139 (FIG. 1) may be achieved by switching the supply voltage V off and on again. This action effectively ensures that the bias current to the amplifying device 101 is always re-set to give the correct initial mode of operation with respect to the input signal level.

FIG. 5 is a block circuit diagram of a circuit 500 which may used as an illustrative implementation of the current controller 131 and the voltage source 121 (FIG.

1) . The circuit 500 includes transistors 501, 503 and 505, which for illustration purposes are shown in FIG. as bipolar junction p-n-p transistors. However, it will be readily apparent to those skilled in the art that bipolar junction n-p-n transistors or field effect transistors could be used instead with a suitable selection of voltage polarities. A battery 507 serving as the voltage source 121 (FIG. 1) has a negative terminal which is connected to ground and a positive terminal at the supply voltage V::. The battery 507 15 connected at its positive terminal via a resistor 509 to the transistor 501 at its emitter electrode and is connected via a resistor 511 to the transistors 503 and 505 at their respective emitter electrodes. The respective base electrodes of the transistors 501 and 503 are connected together and are connected to the respective collector electrodes of the transistors 503 and 505. The collector electrodes of the transistors 503 and 505 are also connected via a resistor 513 to ground. The collector electrode of the transistor 501 is connected via a capacitor 515 and a resistor 517 to ground.

In operation of the circuit 500, the transistor 501 delivers an output current via the resistor 133 (and the inductor 135) of the bias arrangement 134 to the input terminal 103 of the amplifying device 101 (FIG.1). The output current is controlled to be either low in a low current mode or high in a high current mode, depending on the output control signal produced by the comparator 137 (FIG. 1). The output control signal produced by the comparator 137 is in this case an output voltage VOUT which is applied to the base electrode of the transistor 505. The base electrode of the transistor 505 thus serves as the control input 138 shown in FIG. 1.

When the input RF signal has a power which is below a level which drives operation of the amplifying device 101 into compression, the circuit 500 operates in its low current mode, i.e. the output current produced by transistor 501 at its collector electrode is relatively low. The voltage VOUT which is applied to the base electrode of transistor 505 in this mode causes the transistor 505 to be in a cut-off or non-conducting state so that it has no effect on the transistor 503. The transistors 501 and 503 are both in a conducting state. The transistors 501 and 503 are also in a current sourcing mirror configuration. The output current produced by the transistor 501 is controlled to mirror that in the load provided by the resistor 513. The voltage at the collector electrode of the transistor 501 is the monitored voltage VE referred to earlier.

When a condition is obtained in which the input RF signal has a power which reaches or exceeds a level which drives operation of the amplifying device 101 into the condition of compression, the condition is detected by the comparator 137 (FIG. 1) from the corresponding fall in the monitored voltage yE in the manner described earlier. The output voltage Vou produced by the comparator 137 is thereby changed to cause the circuit 500 to be changed to its high current mode. In the high current mode, the output voltage V0p produced by the comparator 137 causes the transistor 505 to be switched to a highly conducting or saturated state. In this state of the transistor 505, the transistor 503 is switched in turn to be in a cut-off or non-conducting state in which it has no effect on the transistor 501. The transistor 501 remains in a conducting state, although the current delivered by the collector electrode of the transistor 501 is increased to high in the high current mode.

The output current required to be delivered as a bias current by the circuit 500 respectively in the low current and high current modes will depend on the properties of the amplifying device 101 and the way in which its compression point changes with bias current.

The circuit 500 can be designed to give suitable output currents in the different modes.

The connection to ground which includes the capacitor 515 and the resistor 517 is an optional connection which serves in connection with the current mirror configuration of the transistors 501 and 503 as a noise filter in a known manner.

FIG. 6 is a flow chart of a method 600 which summarises operation of the amplifier circuit 100 of FIG. 1. In a step 601, an RF signal is applied to the input terminal 103 of the amplifying device 101. In a step 603, the monitored voltage yE at the output of the current controller 131 is detected by the comparator 131. In a step 605, which is applied continuously, the comparator 131 compares the monitored voltage V8 (or a change in the monitored voltage V8) with a reference voltage.

If a change in the monitored voltage V8 (from its initial value) is found in step 605 to be less than a threshold, e.g. equivalent to the threshold value VTFI indicated in FIG. 4, a step 607 follows in which the output voltage VOUT produced by the comparator 137, which serves as a control signal, is set to operate the current controller 131 via its control input 138 in a low current mode, which is one of at least two modes of operation of the current controller 131. In response to receiving the particular level of the output voltage VOUT produced in step 609, the current controller 131 is operated in the low current mode. In response, the amplifying device 101 receives a low current at the input terminal 103 and operates in a linear part of its amplification characteristic. The low current is one of at least two different currents that the amplifying device 101 may receive from the current controller 131 in its different modes.

If the change in the monitored voltage yE is found in step 605 to be at or above the threshold, e.g. the threshold VTH indicated in FIG. 4, a step 613 follows in which the output voltage VOUT produced by the comparator 137 is set at a level to control the current controller 131 via the control input 138 to operate in a high current mode, which is another of the modes pf the current controller 131. In response to receiving the particular level of the voltage VOUT produced in step 613, the current controller 131 is operated in the high current mode. In response, the amplifying device 101 receives a high bias current at the input terminal 103 and continues to operate in a linear part of its transfer characteristic, even though the input RF signal is stronger.

If the change in the monitored voltage VB (from its initial value) is found in step 605 following application of steps 613 to 617 to be once more at or below a threshold, steps 607 to 611 follow once more.

However in this case, the relevant threshold may be below that previously applied to trigger steps 613 to 617, e.g. it may be equivalent to the lower threshold value V11, indicated in FIG. 4. Similarly, if the change (from its initial value) of the monitored voltage yR is found in step 605 following application of steps 607 to 611 to be once more at or above a threshold, steps 613 to 617 follow once more. However in this case, the relevant threshold may again be the higher threshold value VTH indicated in FIG. 4.

The amplifier circuit 100 may be used as a low noise amplifier (LNA), e.g. in known applications of such amplifiers. In particular, the amplifier circuit 100 is suitable for use in one or more stages of a receiver of a mobile communication terminal, especially a terminal in which high performance operation as described earlier is required to give minimal distortion and maximal dynamic range, e.g. a TETRA terminal.

In the foregoing specification, specific

embodiments have been described. However, one of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the scope of the invention as set forth in the accompanying claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this patent application and all equivalents of those claims as issued.

Moreover in this document, relational terms such as first' and second', top' and bottom', and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The terms comprises', comprising', has', having', includes', including', contains', containing' or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes or contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by comprises...a', has a', includes...a', or contains...a' does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms a' and an' are defined as one or more unless explicitly stated otherwise herein. The terms substantially', essentially', approximately', about' or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%, of a stated value. The term coupled' as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is configured' in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose

of streamlining the disclosure. This method of

disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim.

Rather, as the following claims reflect, inventive subject matter may lie in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter. TITLE: AMPLIFIER CIRCUIT FOR USE IN A RADIO FREQUENCY

RECEIVER AND A METHOD OF OPERATION

TECHNICAL FIELD

The technical field relates generally to an

BACKGROUND

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

addition, the description and drawings do not

obscure the disclosure with details that will be

DETAILED DESCRIPTION

In the foregoing specification, specific

of streamlining the disclosure. This method of

Rather, as the following claims reflect, inventive subject matter may lie in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

Claims

CLAIMS 1. An amplifier circuit for use in a radio frequency (RF) receiver, the amplifier circuit including an amplifying device having: (i) an input terminal for applying an input RF signal to the device; and (ii) an output terminal for delivering an amplified output RF signal from the device, a bias arrangement for applying an electrical bias to the input terminal of the amplifying device to control an amplifying characteristic of the amplifying device, an electrical controller for varying the electrical bias to vary a position of operation on the amplifying characteristic, and a control loop for controlling the electrical controller, the control loop including a comparator for comparing a monitored voltage indicative of the electrical bias with a reference value to produce an output signal which changes when a change in the monitored voltage indicates a condition of compression of the amplifying characteristic, and, operably connected to the comparator, a control input to the electrical controller for applying to the electrical controller the output signal from the comparator to control the electrical bias. 2. An amplifier circuit according to claim 1 wherein the electrical controller is a current controller and the control input is operable to control a level of output current delivered by the electrical controller. 3. An amplifier circuit according to claim 2 wherein the current controller is operable in at least two modes to deliver different levels of output current in the different modes, and the control input is operable to apply different input signals to the current controller to select the different modes. 4. An amplifier circuit according to claim 3 wherein the control input is operable to deliver from the comparator to the control input of the current controller different input signals which are different voltages. 5. An amplifier circuit according to any one of claims 2 to 4 wherein the current controller comprises a first transistor and a second transistor in a current sourcing mirror configuration operable to deliver an output current from the first transistor, and a third transistor operable to switch the second transistor between a conducting state and a non-conducting state, the control input being connected to control the third transistor to provide the third transistor with a first state in which the third transistor is non-conducting and has no effect on the second transistor and a second state in which the third transistor is conducting and switches the second transistor to a non-conducting state. 6. An amplifier circuit according to any one of the preceding claims wherein the monitored voltage is a DC voltage developed in the bias arrangement between the electrical controller and the input terminal. 7. An amplifier circuit according to claim 6 wherein the monitored voltage is a DC voltage developed at an output of the electrical controller. 8. An amplifier circuit according to claim 7 wherein the comparator is operable to detect a change of the DC voltage developed at the output of the electrical controller relative to an initial value of the voltage and to produce a change in the output signal when the change of the DC voltage reaches a threshold. 9. An amplifier circuit according to any one of the preceding claims wherein the comparator comprises a hysteresis comparator which produces an output signal which changes when an input signal reaches a threshold, wherein the threshold changes between a first threshold value and a second threshold value when the output signal changes so that a further change in the output signal requires a further change in the input signal equivalent to the difference between the first threshold value and the second threshold value. 10. An amplifier circuit according to any one of the preceding claims including a re-set controller operable to re-set the comparator. 11. An amplifier circuit according to claim 10 wherein the re-set controller is operable to re-set the comparator at start-up of the amplifier circuit. 12. An amplifier circuit according to claim 10 or claim 11 wherein the re-set controller is operable to re-set the comparator at the end of every time slot of a time slotted sequence in which an RF input signal is applied to the amplifier circuit. 13. An amplifier circuit according to any one of the preceding claims wherein the amplifying device is a solid state device. 14. An amplifying circuit according to claim 13 wherein the amplifying device is a bipolar junction transistor, the input terminal comprises a base electrode of the transistor and the output terminal comprises a collector electrode of the transistor. 15. An amplifying circuit according to any one of the preceding claims and substantially as herein described with reference to any one or more of the accompanying drawings. 16. A method of operation of the amplifier circuit according to any one of the preceding claims including applying an input RF signal to the amplifying device; delivering an amplified output RF signal from the amplifying device, applying from the electrical controller via the electrical bias arrangement to the input terminal of the amplifying device an electrical bias to control an amplifying characteristic of the amplifying device, varying the electrical bias to vary a position of operation on the amplifying characteristic, and controlling the electrical controller by a control loop including a comparator and a control input to the electrical controller, the comparator comparing a monitored voltage indicative of the electrical bias with a reference value to produce an output signal which changes when the monitored parameter reaches a threshold value indicating a condition of compression of the amplifying characteristic, and the control input applying to the electrical controller the output signal from the comparator to control the electrical bias. 17. An amplifying circuit according to any one of the preceding claims 1 to 15 and substantially as herein described with reference to any one or more of the accompanying drawings. 18. A method of operation according to claim 16 and substantially as herein described with reference to any one or more of the accompanying drawings. Amendments to the claims have been filed as follows 1. An amplifier circuit for use in a radio frequency (RF) receiver, the amplifier circuit including an amplifying device having: (i) an input terminal for applying an input RF signal to the device; and (ii) an output terminal for delivering an amplified output RF signal from the device, a bias arrangement for applying an electrical bias to the input terminal of the amplifying device to control an amplifying * characteristic of the amplifying device, an electrical *S. controller for varying the electrical bias to vary a position of operation on the amplifying characteristic, and a control loop for controlling the electrical controller, the control loop including a comparator for comparing a monitored voltage, which is a DC voltage developed in the bias arrangement between the electrical controller and the input terminal, with a reference value to produce an output signal which changes when a change in the monitored voltage indicates a condition of compression of the amplifying characteristic and, operably connected to the comparator, a control input to the electrical controller for applying to the electrical controller the output signal from the comparator to control the electrical bias. 2. An amplifier circuit according to claim 1 wherein the electrical controller is a current controller and the control input is operable to control a level of output current delivered by the electrical controller. 3. An amplifier circuit according to claim 2 wherein the current controller is operable in at least two modes to deliver different levels of output current in the different modes, and the control input is operable to apply different input signals to the current controller to select the different modes. 4. An amplifier circuit according to claim 3 wherein s.., the control input is operable to deliver from the * 5. comparator to the control input of the current controller different input signals which are different voltages. 5. An amplifier circuit according to any one of claims 2 to 4 wherein the current controller comprises a first transistor and a second transistor in a current sourcing mirror configuration operable to deliver an output current from the first transistor, and a third transistor operable to switch the second transistor between a conducting state and a non-conducting state, the control input being connected to control the third transistor to provide the third transistor with a first state in which the third transistor is non-conducting and has no effect on the second transistor and a second state in which the third transistor is conducting and switches the second transistor to a non-conducting state. 6. An amplifier circuit according to any one of the preceding claims wherein the monitored voltage is a DC voltage developed at an output of the electrical controller. 7. An amplifier circuit according to claim 6 wherein the comparator is operable to detect a change of the DC voltage developed at the output of the electrical controller relative to an initial value of the voltage and to produqe a change in the output signal when the change of the DC voltage reaches a threshold. 8. An amplifier circuit according to any one of the * ** preceding claims wherein the comparator comprises a **S. hysteresis comparator which produces an output signal *: which changes when an input signal reaches a threshold, *15 wherein the threshold changes between a first threshold value and a second threshold value when the output *:*::* signal changes so that a further change in the output signal requires a further change in the input signal equivalent to the difference between the first threshold value and the second threshold value. 9. An amplifier circuit according to any one of the preceding claims including a re-set controller operable to re-set the comparator. 10. An amplifier circuit according to claim 9 wherein the re-set controller is operable to re-set the comparator at start-up of the amplifier circuit. 11. An amplifier circuit according to claim 9 or claim wherein the re-set controller is operable to re-set the comparator at the end of every time slot of a time slotted sequence in which an RE' input signal is applied to the amplifier circuit. 12. An amplifier circuit according to any one of the preceding claims wherein the amplifying device is a solid state device. 13. A amplifying circuit according to claim 12 wherein the amplifying device is a bipolar junction transistor, the input terminal comprises a base electrode of the transistor and the output terminal comprises a collector electrode of the transistor. 14. An amplifying circuit according to any one of the * .. preceding claims and substantially as herein described S... with reference to any one or more of the accompanying drawings. 15. A method of operation of the amplifier circuit according to any one of the preceding claims including applying an input RE' signal to the amplifying device; * delivering an amplified output RE' signal from the amplifying device, applying from the electrical controller via the electrical bias arrangement to the input terminal of the amplifying device an electrical bias to.control an amplifying characteristic of the amplifying device, varying the electrical bias to vary a position of operation on the amplifying characteristic, and controlling the electrical controller by a control loop including a comparator and a control input to the electrical controller, the comparator comparing with a reference voltage a monitored voltage indicative of the electrical bias, 3C\ the monitored voltage being a DC voltage developed in the bias arrangement between the electrical controller and the input terminal, the comparator producing an output signal which changes when the monitored parameter reaches a threshold value indicating a condition of compression of the amplifying characteristic, and the control input applying to the electrical controller the output signal from the * ** comparator to control the electrical bias. 16. An amplifying circuit according to any one of the preceding claims 1 to 14 and substantially as herein described with reference to any one or more of the U... accompanying drawings. 17. A method of operation according to claim 15 and substantially as herein described with reference to any one or more of the accompanying drawings. U CLAIMS

1. An amplifier circuit for use in a radio frequency (RF) receiver, the amplifier circuit including an amplifying device having: (i) an input terminal for applying an input RF signal to the device; and (ii) an output terminal for delivering an amplified output RF signal from the device, a bias arrangement for applying an electrical bias to the input terminal of the amplifying device to control an amplifying characteristic of the amplifying device, an electrical controller for varying the electrical bias to vary a position of operation on the amplifying characteristic, and a control loop for controlling the electrical controller, the control loop including a comparator for comparing a monitored voltage indicative of the electrical bias with a reference value to produce an output signal which changes when a change in the monitored voltage indicates a condition of compression of the amplifying characteristic, and, operably connected to the comparator, a control input to the electrical controller for applying to the electrical controller the output signal from the comparator to control the electrical bias.

2. An amplifier circuit according to claim 1 wherein the electrical controller is a current controller and the control input is operable to control a level of output current delivered by the electrical controller.

3. An amplifier circuit according to claim 2 wherein the current controller is operable in at least two modes to deliver different levels of output current in the different modes, and the control input is operable to apply different input signals to the current controller to select the different modes.

4. An amplifier circuit according to claim 3 wherein the control input is operable to deliver from the comparator to the control input of the current controller different input signals which are different voltages.

5. An amplifier circuit according to any one of claims 2 to 4 wherein the current controller comprises a first transistor and a second transistor in a current sourcing mirror configuration operable to deliver an output current from the first transistor, and a third transistor operable to switch the second transistor between a conducting state and a non-conducting state, the control input being connected to control the third transistor to provide the third transistor with a first state in which the third transistor is non-conducting and has no effect on the second transistor and a second state in which the third transistor is conducting and switches the second transistor to a non-conducting state.

6. An amplifier circuit according to any one of the preceding claims wherein the monitored voltage is a DC voltage developed in the bias arrangement between the electrical controller and the input terminal.

7. An amplifier circuit according to claim 6 wherein the monitored voltage is a DC voltage developed at an output of the electrical controller.

8. An amplifier circuit according to claim 7 wherein the comparator is operable to detect a change of the DC voltage developed at the output of the electrical controller relative to an initial value of the voltage and to produce a change in the output signal when the change of the DC voltage reaches a threshold.

9. An amplifier circuit according to any one of the preceding claims wherein the comparator comprises a hysteresis comparator which produces an output signal which changes when an input signal reaches a threshold, wherein the threshold changes between a first threshold value and a second threshold value when the output signal changes so that a further change in the output signal requires a further change in the input signal equivalent to the difference between the first threshold value and the second threshold value.

10. An amplifier circuit according to any one of the preceding claims including a re-set controller operable to re-set the comparator.

11. An amplifier circuit according to claim 10 wherein the re-set controller is operable to re-set the comparator at start-up of the amplifier circuit.

12. An amplifier circuit according to claim 10 or claim 11 wherein the re-set controller is operable to re-set the comparator at the end of every time slot of a time slotted sequence in which an RF input signal is applied to the amplifier circuit.

13. An amplifier circuit according to any one of the preceding claims wherein the amplifying device is a solid state device.

14. An amplifying circuit according to claim 13 wherein the amplifying device is a bipolar junction transistor, the input terminal comprises a base electrode of the transistor and the output terminal comprises a collector electrode of the transistor.

15. An amplifying circuit according to any one of the preceding claims and substantially as herein described with reference to any one or more of the accompanying drawings.

16. A method of operation of the amplifier circuit according to any one of the preceding claims including applying an input RF signal to the amplifying device; delivering an amplified output RF signal from the amplifying device, applying from the electrical controller via the electrical bias arrangement to the input terminal of the amplifying device an electrical bias to control an amplifying characteristic of the amplifying device, varying the electrical bias to vary a position of operation on the amplifying characteristic, and controlling the electrical controller by a control loop including a comparator and a control input to the electrical controller, the comparator comparing a monitored voltage indicative of the electrical bias with a reference value to produce an output signal which changes when the monitored parameter reaches a threshold value indicating a condition of compression of the amplifying characteristic, and the control input applying to the electrical controller the output signal from the comparator to control the electrical bias.

17. A method of operation according to claim 15 and substantially as herein described with reference to any one or more of the accompanying drawings.

U

17. An amplifying circuit according to any one of the preceding claims 1 to 15 and substantially as herein described with reference to any one or more of the accompanying drawings.

18. A method of operation according to claim 16 and substantially as herein described with reference to any one or more of the accompanying drawings.

Amendments to the claims have been filed as follows 1. An amplifier circuit for use in a radio frequency (RF) receiver, the amplifier circuit including an amplifying device having: (i) an input terminal for applying an input RF signal to the device; and (ii) an output terminal for delivering an amplified output RF signal from the device, a bias arrangement for applying an electrical bias to the input terminal of the amplifying device to control an amplifying * characteristic of the amplifying device, an electrical *S.

controller for varying the electrical bias to vary a position of operation on the amplifying characteristic, and a control loop for controlling the electrical controller, the control loop including a comparator for comparing a monitored voltage, which is a DC voltage developed in the bias arrangement between the electrical controller and the input terminal, with a reference value to produce an output signal which changes when a change in the monitored voltage indicates a condition of compression of the amplifying characteristic and, operably connected to the comparator, a control input to the electrical controller for applying to the electrical controller the output signal from the comparator to control the electrical bias.

4. An amplifier circuit according to claim 3 wherein s.., the control input is operable to deliver from the * 5.

comparator to the control input of the current controller different input signals which are different voltages.

6. An amplifier circuit according to any one of the preceding claims wherein the monitored voltage is a DC voltage developed at an output of the electrical controller.

7. An amplifier circuit according to claim 6 wherein the comparator is operable to detect a change of the DC voltage developed at the output of the electrical controller relative to an initial value of the voltage and to produqe a change in the output signal when the change of the DC voltage reaches a threshold.

8. An amplifier circuit according to any one of the * ** preceding claims wherein the comparator comprises a **S.

hysteresis comparator which produces an output signal *: which changes when an input signal reaches a threshold, *15 wherein the threshold changes between a first threshold value and a second threshold value when the output *:*::* signal changes so that a further change in the output signal requires a further change in the input signal equivalent to the difference between the first threshold value and the second threshold value.

9. An amplifier circuit according to any one of the preceding claims including a re-set controller operable to re-set the comparator.

10. An amplifier circuit according to claim 9 wherein the re-set controller is operable to re-set the comparator at start-up of the amplifier circuit.

11. An amplifier circuit according to claim 9 or claim wherein the re-set controller is operable to re-set the comparator at the end of every time slot of a time slotted sequence in which an RE' input signal is applied to the amplifier circuit.

12. An amplifier circuit according to any one of the preceding claims wherein the amplifying device is a solid state device.

13. A amplifying circuit according to claim 12 wherein the amplifying device is a bipolar junction transistor, the input terminal comprises a base electrode of the transistor and the output terminal comprises a collector electrode of the transistor.

14. An amplifying circuit according to any one of the * ..

preceding claims and substantially as herein described S...

with reference to any one or more of the accompanying drawings.

15. A method of operation of the amplifier circuit according to any one of the preceding claims including applying an input RE' signal to the amplifying device; * delivering an amplified output RE' signal from the amplifying device, applying from the electrical controller via the electrical bias arrangement to the input terminal of the amplifying device an electrical bias to.control an amplifying characteristic of the amplifying device, varying the electrical bias to vary a position of operation on the amplifying characteristic, and controlling the electrical controller by a control loop including a comparator and a control input to the electrical controller, the comparator comparing with a reference voltage a monitored voltage indicative of the electrical bias, 3C\ the monitored voltage being a DC voltage developed in the bias arrangement between the electrical controller and the input terminal, the comparator producing an output signal which changes when the monitored parameter reaches a threshold value indicating a condition of compression of the amplifying characteristic, and the control input applying to the electrical controller the output signal from the * ** comparator to control the electrical bias.

16. An amplifying circuit according to any one of the preceding claims 1 to 14 and substantially as herein described with reference to any one or more of the U...

accompanying drawings.