GB2443376A - Semiconductor memory device having bit registering layer and method of driving the same - Google Patents

Semiconductor memory device having bit registering layer and method of driving the same Download PDF

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Publication number
GB2443376A
GB2443376A GB0804034A GB0804034A GB2443376A GB 2443376 A GB2443376 A GB 2443376A GB 0804034 A GB0804034 A GB 0804034A GB 0804034 A GB0804034 A GB 0804034A GB 2443376 A GB2443376 A GB 2443376A
Authority
GB
United Kingdom
Prior art keywords
memory
memory device
layer
semiconductor memory
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0804034A
Other versions
GB0804034D0 (en
GB2443376B (en
GB2443376A8 (en
Inventor
Hong Sik Yoon
In Seok Yeo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050086689A external-priority patent/KR100655078B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB0804034D0 publication Critical patent/GB0804034D0/en
Publication of GB2443376A publication Critical patent/GB2443376A/en
Publication of GB2443376A8 publication Critical patent/GB2443376A8/en
Application granted granted Critical
Publication of GB2443376B publication Critical patent/GB2443376B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/883—Masking faults in memories by using spares or by reconfiguring with partially good memories using a single defective memory device with reduced capacity, e.g. half capacity
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/16—Memory cell being a nanotube, e.g. suspended nanotube
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a carbon nanotube memory, an atomic memory, a single electron memory, or a memory fabricated by a chemical bottom-up method, etc.
GB0804034A 2005-09-16 2006-05-09 Semiconductor memory device having bit registering layer and method of driving the same Active GB2443376B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020050086689A KR100655078B1 (en) 2005-09-16 2005-09-16 Semiconductor memory device having bit registering layer and method for driving thereof
US11/365,585 US7535778B2 (en) 2005-09-16 2006-03-02 Semiconductor memory device with memory cells, each having bit registering layer in addition to a memory layer and method of driving the same
PCT/KR2006/001727 WO2007032588A1 (en) 2005-09-16 2006-05-09 Semiconductor memory device having bit registering layer and method of driving the same

Publications (4)

Publication Number Publication Date
GB0804034D0 GB0804034D0 (en) 2008-04-09
GB2443376A true GB2443376A (en) 2008-04-30
GB2443376A8 GB2443376A8 (en) 2008-05-19
GB2443376B GB2443376B (en) 2011-03-23

Family

ID=37865147

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0804034A Active GB2443376B (en) 2005-09-16 2006-05-09 Semiconductor memory device having bit registering layer and method of driving the same

Country Status (3)

Country Link
DE (1) DE112006002421B4 (en)
GB (1) GB2443376B (en)
WO (1) WO2007032588A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359559A (en) * 1991-05-21 1994-10-25 Texas Instruments Incorporated Semiconductor memory device having redundant memory cells
US6205065B1 (en) * 1999-01-26 2001-03-20 Nec Corporation Semiconductor memory device having redundancy memory circuit
US6246617B1 (en) * 1999-03-11 2001-06-12 Kabushiki Kaisha Toshiba Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device
US6807101B2 (en) * 2002-03-06 2004-10-19 Renesas Technology Corp. Semiconductor memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5532966A (en) 1995-06-13 1996-07-02 Alliance Semiconductor Corporation Random access memory redundancy circuit employing fusible links
US6683783B1 (en) 1997-03-07 2004-01-27 William Marsh Rice University Carbon fibers formed from single-wall carbon nanotubes
US6472705B1 (en) 1998-11-18 2002-10-29 International Business Machines Corporation Molecular memory & logic
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
US6549457B1 (en) * 2002-02-15 2003-04-15 Intel Corporation Using multiple status bits per cell for handling power failures during write operations
JP2003346496A (en) * 2002-05-22 2003-12-05 Mitsubishi Electric Corp Defective information storage, defective information storage processor provided with the same, defective information storage method, semiconductor device testing apparatus provided with defective information storage, and semiconductor device provided with defective information storage
US7006392B2 (en) * 2004-01-26 2006-02-28 Micron Technology, Inc. Memory redundancy programming
EP1624463A1 (en) * 2004-07-14 2006-02-08 STMicroelectronics S.r.l. A Programmable memory device with an improved redundancy structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359559A (en) * 1991-05-21 1994-10-25 Texas Instruments Incorporated Semiconductor memory device having redundant memory cells
US6205065B1 (en) * 1999-01-26 2001-03-20 Nec Corporation Semiconductor memory device having redundancy memory circuit
US6246617B1 (en) * 1999-03-11 2001-06-12 Kabushiki Kaisha Toshiba Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device
US6807101B2 (en) * 2002-03-06 2004-10-19 Renesas Technology Corp. Semiconductor memory device

Also Published As

Publication number Publication date
GB0804034D0 (en) 2008-04-09
GB2443376B (en) 2011-03-23
GB2443376A8 (en) 2008-05-19
DE112006002421B4 (en) 2018-11-29
WO2007032588A1 (en) 2007-03-22
DE112006002421T5 (en) 2008-07-24

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