GB2412044A

GB2412044A - Analogue decoding before conversion in UWB IR receivers

Info

Publication number: GB2412044A
Application number: GB0405318A
Authority: GB
Inventors: Paul Strauch; Douglas John Gargin
Original assignee: Toshiba Research Europe Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 2004-03-09
Filing date: 2004-03-09
Publication date: 2005-09-14
Anticipated expiration: 2024-03-09
Also published as: GB2412044B; GB0405318D0

Abstract

An ultra wide band (UWB) impulse radio (IR) receiver employs an analogue decoder 12 prior to analogue to digital (A/D) conversion 13 in order to reduce computationally and energy intensive digital processing. Several analogue sample-and-hold circuits 11 receive temporally spaced samples of an encoded analogue signal from a correlator 5 after correlation with a pulse template 6. These soft decision values are supplied in parallel to an analogue decoder 12 which outputs hard decision values to the A/D convertor 13. The analogue signal may be encoded using BPSK or MBOK modulation and Turbo, LDPC or convolutional coding, and the correlator 5 may be replaced by multiple correlators (15, fig. 3) supplied by different analogue signals from a rake receiver.

Description

24 1 2044 Communications Receiver The present invention relates to a

communications receiver, and more particularly but not exclusively to an ultra wide band (UWB) communications receiver.

In many applications an analogue transmitter transmits a signal which is received by an analogue receiver. A device including the analogue receiver may process digital (as opposed to analogue) signals, and it is therefore common to sample the received analogue signal at a predetermined sampling rate, and input sampled values of the analogue signal to an analogue to digital convertor to generate a bit-stream which can then be processed by the device as digital data.

In many applications the received analogue signal may have been generated from a digital signal, which has been encoded using a Forward Error Correction (FEC) code.

Such coding allows data to be accurately received even when some parts of the signal are inaccurately received due to, for example, noise. Typically used FEC codes include convolutional codes, Turbo codes, and low-density parity check (LDPC) codes. When such coding is employed, the receiver uses a decoder such as a Viterbi decoder operating on digital signals to decode the bit-stream output from the analogue to digital convertor. The decoder can be implemented using any appropriate architecture such as a digital signal processor (DSP), application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Such decoding is usually carried out after the process of equalization, which is also carried out in the digital domain.

Iterative decoding of FEC codes is a computationally demanding process. Recently, analogue decoding of error correcting codes has been proposed. Performing decoding in the analogue domain seeks to exploit the nonlinear characteristics of transistors. One -) such analogue decoder is described in Winstead, C; Dai, J.; Yu, S; Harrison, R; Meyers, C; and Schlegel, C: "Analog decoding of Product Codes", ITW 2001.

Although analogue decoding has advantages, such decoding has proved unattractive for use in communications receivers such as that described above, given that decoding is carried out after other digital domain processes. This means that the digital signal must be converted back to an analogue signal using digital to analogue converters, and returned to an analogue signal at the output of the decoder using analogue to digital convertors. These conversions usually out weigh any benefits which may be achieved through use of an analogue decoder.

It is an object of the present invention to provide a communications receiver which obviates or mitigates one or more of the disadvantages outlined above.

According to the present invention, there is provided a communications receiver comprising an antenna for receiving an encoded analogue signal, sampling means for sampling said encoded analogue signal to obtain a plurality of temporally spaced analogue sample values of said encoded analogue signal, analogue decoder means for receiving said analogue sample values and generating an analogue decoded signal from said analogue sample values, and an analogue to digital convertor configured to convert said decoded signal to a digital signal.

Surprisingly, the inventors of the present invention have discovered that by reordering processes within a communications receiver, decoding can be carried out before any analogue to digital conversion. This allows analogue decoders to be efficiently used within a communications receiver. Thus the invention allows the benefits of analogue decoding to be employed without the overhead of digital to analogue and analogue to digital conversion outlined above.

Embodiments of the present invention provide a number of benefits. For example, the invention can be applied to Ultra wide band (UWB) impulse radio (IR). UWB IR aims to be a low cost, low power communications technology. High-speed digital circuits included in UWB IR devices are power hungry and occupy relatively large areas of silicon space, thus hampering the aim of low power consumption. UWB IR devices therefore comprise triggered analogue correlators rather than a digital solution to reduce power consumption. However, much digital processing is still required, thereby retaining the problems of power consumption and relatively large surface area described above. Embodiments of the present invention allow decoding to be carried out in the analogue domain, thereby reducing power consumption. Thus analogue to digital conversion need not be carried out until after decoding has taken place, and the analogue to digital convertors need only be single bit convertors, each of which can be realized by means of a simple comparator.

A communications receiver in accordance with embodiments of the invention may further comprise correlator means for receiving said encoded analogue signal and outputting a signal suitable for input to said sampling means. The correlator means may comprise a rake receiver configured to receive a plurality of components of a transmitted signal, each of which has travelled by a different path, and configured to combine the components to form a single signal. Using a rake receiver in this way improves the signal to noise ratio (SNR) of the received signal.

The communications receiver may further comprise integration means taking input samples from said sampling means and performing integration on said samples, the result of said integration being input to said analogue decoder means. Using an integrator in this way is particularly beneficial where a single bit of data is transmitted a plurality of times, and said integration is used to improve the accuracy with which data is received.

The analogue signal may be modulated using a variety modulation schemes, including binary phase shift keying (BPSK) modulation, and a M-ary biorthogonal shift keying (MBOK) modulation.

The modulated signal may comprise a plurality of pulses, and each pulse may represent a plurality of bits of data. The correlator means may comprise a plurality of multipliers and a plurality of integrators, one multiplier and one integrator being provided for each bit of said plurality of bits of data The correlator means may further comprise a plurality \ of adders configured to sum outputs from said plurality of integrators, one adder being provided for each bit of said plurality of bits of data. The adders may be configured such that each adder produces an output indicative of the value of one bit of said plurality of bits of data.

The encoded analogue signal may encoded using turbo coding, LDPC coding or convolutional coding.

The invention further provides a method for receiving and processing a signal comprising receiving an encoded analogue signal, sampling said encoded analogue signal to obtain a plurality of temporally spaced analogue sample values of said encoded analogue signal, receiving said analogue sample values at a decoder and generating an analogue decoded signal from said analogue sample values, and converting said decoded signal to a digital signal.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure I is a schematic illustration of a prior art communications receiver; Figure 1A is an illustration of a signal received by the antenna of Figure 1; Figure I B is an illustration of the signal output by the correlator of Figure 1; Figure 2 is a schematic illustration of a communications receiver in accordance with an embodiment of the present invention; Figure 3 is a schematic illustration of a communications receiver in accordance with a further embodiment of the present invention incorporating a rake receiver; Figure 4 is a table showing encoding of two-bit values using M-ary Bi-orthogonal Shift Keying (MBOK) modulation; \: Figure 5 is a schematic illustration of a communications receiver in accordance with an embodiment of the present invention configured to receive signals modulated using MBOK modulation; Figures SA and SB are illustrations of pulses generated by template generators in the communications receiver of Figure 5; and Figure 6 is a table showing how a correlation circuit of the communications receiver of Figure 5 decodes MBOK modulated data.

Referring first to Figure 1, a known communications receiver is described. The illustrated receiver is configured for use in ultra wide band (UWB) impulse radio (IR).

Although the receiver is described in outline below, a fuller description can be found in Win, M.Z; and Scholtz, R.A: "Impulse Radio: How it works", IEEE Communications Letters, Vol. 2, No 2, February 1998, the contents of which are herein incorporated by reference.

A signal 1 is received by an antenna 2. The signal 1 has been encoded to reduce errors using convolutional coding, and modulated using Binary Phase Shift Keying (BPSK).

When using BPSK modulation, the polarity of the pulse is modulated in accordance with data to be transmitted. For example, a pulse with positive polarity is generated to represent a '1', and a pulse with negative polarity is generated to represent a '0'. In UWB IR a plurality of pulses may be transmitted to represent a single bit of data, so as to improve the signal to noise ratio (SNR).

The received signal I is illustrated in Figure IA. The signal is amplified by an amplifier 3 and filtered by a filter 4 to remove noise. The filtered signal is input to a correlator 5 comprising a multiplier 5a and an integrator 5b. The correlator is configured to correlate the signal by performing a "multiply and integrate" operation. In order to facilitate the "multiply and integrate" correlation operation a second waveform is input to the multiplier 5a, and the multiplier 5a multiplies the second waveform and the filter end signal.. The second waveform, is internally generated in the receiver, using a template generator 6, and a trigger circuit 7. The second waveform is generated so as to be as close as possible to that which was generated by the transmitter, by identifying the probable sequence of pulses responsible for the received signal. This facilitates correct pulse correlation for every pulse entering the receiver. Figure 1B shows the signal output by the correlator 5 in response to receipt of the signal illustrated in Figure 1 A. The correlator is conventional in nature and is not therefore described in further detail here, a full description can be found in Burke, B.E.; Smythe, D.L.; 'A CCD time- integrating correlator', Solid-State Circuits, IEEE Journal of, Volume: 18 Issue: 6, Dec 1983.

The sequence of pulses output from the correlator 5 is input to a sample and hold circuit 8, the purpose of which is to generate samples. An increase in performance can be obtained by using soft bit decision data for input to a decoder. In Figure 1, this is achieved by using an N-bit analogue to digital convertor 9. It should be noted that performance can be improved further by encoding each data symbol (bit in this case) using multiple pulses at the transmitter. In some embodiments of the invention, the contribution of the plurality of pulses can be exploited at the receiver by using a further integrator block (not shown), which takes input the sample and hold circuit 8. The use of such an integrator block will be well known to one skilled in the art, and is therefore not described in further detail. The N-bits of digital data output from the analogue to digital convertor 9 are then input to a Viterbi decoder 10 which outputs a bit-stream representative of that which was transmitted to the receiver.

Figure 2 illustrates a communications receiver in accordance with an embodiment of the present invention. The antenna 2, the amplifier 3, the filter 4 and the correlator 5 correspond to equivalent components of the communications receiver of Figure 1.

However in the communications receiver of Figure 2, data output from the correlator 5 is input to one of M multiple sample and hold circuits 11. When M separate samples have been captured, one in each sample and hold circuit 11, these are then fed to an analogue decoder 12, which accepts M samples in parallel as input. The data output from the correlator 5 is a series of analogue pulses which are such that the polarity of each pulse represents a value, i.e. '1' or 'O' and the magnitude of each pulse represents a certainty in that value (i.e. the larger the magnitude the greater the certainty in the value). Thus the outputs are so-called "soft decision values". The analogue decoder 12 will output a plurality of analogue values which are "hard decision values" generated from the soft decision values using a decoding algorithm that will be well known to one skilled in the art. These hard decision values are such that the polarity will represent a value ('1' or 'O') with no indication of certainty. The hard decision values output from the analogue decoder 12 are converted to digital values by means of a bank of 1-bit analogue to digital convertors 13, each of which converts a single analogue value into a single digital bit. Each of these analogue to digital convertors 13 can be implemented using a simple comparator.

From the preceding description, it can be seen that embodiments of the present invention can be particularly conveniently implemented where signals are modulated using BPSK modulation, given that after conventional correlation, the signals can be directly used as soft decision values for input to the analogue decoder 12.

The digital outputs from the analogue to digital convertors 13 are input to a parallel to serial interface 14 which outputs a serial stream of bits which can be processed as necessary. It will be appreciated that in some embodiments of the invention processing may be carried out on parallel digital data, and in such embodiments, the parallel to serial interface 14 is not required.

Figure 3 shows an alternative embodiment of the present invention in which the correlator includes a rake receiver. The use of a rake receiver is well known in UWB communications devices. When a signal is transmitted from a transmitter to a receiver, the signal will travel by a plurality of different paths. Part of the received signal will be received by direct propagation from the transmitter to the receiver, and other parts of the signal will be received by reflection from objects within the environment. Thus transmittal of a single signal will result in receipt of a plurality of temporally spaced signals. A rake receiver is a known apparatus for combining these plurality of signals so as to generate a single signal with an improved signal to noise ratio.

Referring to Figure 3, the antenna 2, amplifier 3 and filter 4 operate in the manner described with reference to Figure 2. However in the embodiment of Figure 3 the single correlator 5 of Figure 2 is replaced with a plurality of correlators 1 5a to 1 be, each correlator being configured to receive one of the plurality of signals described above.

Each correlator has an associated template generator 16a to 16e, and a trigger circuit 17 is also provided. Each of the received signals is correlated independently, and the correlator outputs are input to a rake combination device 18 which outputs a single signal which represents the combination of all correlations. The output of the combination device 18 is then input to one of the sample and hold circuits 11, and the remainder of the receiver operates as described with reference to Figure 2.

It has been described above that the invention can be conveniently implemented using BPSK modulation. It was explained that such modulation is convenient because the outputs of the correlator 5 (Figure 2) or the rake combination device 18 (Figure 3) are soft decision values which form suitable inputs for the analogue decoder 12. However, it will be appreciated that some embodiments of the invention can make use of other modulation schemes, one of which is now described with reference to Figures 4 and 5.

Figure 4 is a table showing how two bits of binary data are encoded using M-ary bi- Orthogonal Shift Keying (MBOK) modulation. A value of 00 is represented by a negative pulse, a value of 01 is represented by a pulse having a first positive component and a second negative component, a value of 10 is represented by a pulse having a first negative component and a second positive component, and a value of 11 is represented by a positive pulse. In the example of Figure 4, two orthogonal pulse shapes are used to generate a four symbol MBOK code.

Referring now to Figure 5, there is illustrated a communications device in accordance with an embodiment of the present invention which is configured to receive MBOK modulated data. The receiver again comprises an antenna 2, an amplifier 3 and a filter 4 as described above. The output of the filter 4 is input to a correlation circuit 19. The correlation circuit 19 comprises a first multiplier 20 and a second multiplier 21. The first multiplier 20 has an associated first template generator 22 which generates a signal comprising pulses as illustrated in Figure 5A. The second multiplier 21 has an associated second template generator 23 which generates a signal comprising pulses as illustrated in Figure 5B. Both the first template generator 22 and the second template o generator 23 are connected to a common trigger circuit 24. It should be noted that in the described embodiment, each pulse generator produces a different pulse shape and the pulse shapes are orthogonal. The output of the first multiplier 20 is input to a first integrator 25 and the output of the second multiplier 21 is input to a second integrator 26. The output of the first integrator 25 is added to that of the second integrator 26 by an adder 27. The output of the second integrator 26 is subtracted from that of the first integrator 25 by an adder 28.

Operation of the correlation circuit 19 is now described, where it is assumed that the filter 4 has successfully removed all out-of band noise from the signal output from the amplifier 3. If a pulse representing a value of '00' is input to the correlation circuit 19, the first multiplier 20 will output a negative pulse, representing the multiplication of the 00' pulse with the pulse of Figure 5A, and the second multiplier 21 will output a waveform which has an integral of zero which represents a multiplication of the pulse of Figure 5B, and the '00' pulse. The output of the first integrator 25 will therefore be negative, and the output of the second integrator 26 will be zero, due to the orthogonality of the two pulses. In this case the first adder 27 will output a negative value, and the output of the second adder 28 will also be negative.

If a pulse representing a value of '01' is received, the output of the first multiplier 20 will be a pulse having a zero valued integral, and the output of the second multiplier 21 will be a pulse having two negative components. Thus, the output of the first integrator will be zero, and the output of the second integrator 26 will be negative. The first adder 27 will perform addition of zero plus a negative number to generate a negative output, and the second adder 28 will perform subtraction of a negative number from zero to provide a positive output.

If a pulse representing '10' is received, the first multiplier 20 will generate a pulse having a zero valued integral, and the second multiplier 21 will generate a pulse having a positive component. The output of the first integrator 25 will therefore be zero, and the output of the second integrator 26 will be positive. The output of the first adder 27 will therefore be positive, and the output of second adder 28 will therefore be negative.

If a pulse representing '11' is received, the first multiplier 20 will generate a pulse having a positive component, and the second multiplier 21 will generate a pulse having a zero valued integral. Therefore, the output of the first integrator 25 will be positive, and the output of the second integrator 26 will be negative. The first adder 27 and the second adder 28 will therefore both produce positive outputs.

The outputs of the integrators 25, 26 and the adders 27, 28 described above are summarised in a table in Figure 6. The first adder 27 output is used to represent the most significant bit of the value of Figure 4, and the second adder 28 is used to represent the least significant bit of the value of Figure 4. It can be seen that for each different pulse type, a pair of values having a unique polarity combination are output from the adders 27, 28. It can also be seen that each '0' bit value is represented by negative output from the appropriate adder, and each '1' bit value is represented by a positive output from the appropriate adder. The magnitudes of these outputs will be dependent upon signal strength. It can therefore be seen that data received which is modulated using MBOK modulation can be processed by the correlation circuit 19 to generate an analogue output for each bit value represented by the received pulse, and that these analogue outputs are suitable soft decision values for input to an analogue decoder without the need for digital processing.

Referring back to Figure S. the illustrated communications receiver further comprises two sample and hold circuits 29, 30, one for each bit represented by the received pulse.

These sample and hold circuits function in a similar manner to that described with reference to Figure 2. The outputs of the sample and hold circuits 29, 30 are then input to the analogue decoder 12, from where processing continues as described with reference to Figure 3.

It will be appreciated that embodiments of the invention such as those described above have a wide range of potential applications including, for example, wireless personal area networks, machine to machine wireless communication, smart home connectivity systems, vehicular technology and ad-hoc wireless networks.

Although preferred embodiments of the present invention have been described above, it will be appreciated that modifications can be made without departing from the scope and spirit of the invention as defined by the appended claims. For example, the sample and hold circuits illustrated in Figures 2, 3 and 5, are simply one convenient way of inputting data to an analogue decoder. It will be appreciated that other interfaces can be provided. It will also be appreciated that the invention can be applied to communications receivers operating on signals using modulation schemes other than BPSK and MBOK as described above. For example, the embodiment of the invention described above with reference to MBOK modulation operates on pulses each representing two bits of data. It will be appreciated that the invention can be applied in situations where each pulse represents more than two bits of data.

Claims

CLAIMS: 1. A communications receiver comprising: an antenna for receiving

an encoded analogue signal; sampling means for sampling said encoded analogue signal to obtain a plurality of temporally spaced analogue sample values of said encoded analogue signal; analogue decoder means for receiving said analogue sample values and generating an analogue decoded signal from said analogue sample values; and an analogue to digital convertor configured to convert said decoded signal into a digital signal.
2. A communications receiver according to claim 2, further comprising: correlator means for receiving said encoded analogue signal and outputting a signal suitable for input to said sampling means.
3. A communications receiver according to claim 2, wherein the correlator means comprises a rake receiver.
4. A communications receiver according to claim 1, 2 or 3, wherein the receiver is configured to receive the analogue signal as a binary phase shift keying (BPSK) modulated signal.
5. A communications receiver according to claim 2 or 3, wherein the receiver is configured to receive the analogue signal as a MBOK modulated signal.
6. A communications receiver according to claim 5, wherein said modulated signal comprises a plurality of pulses, and each pulse represents a plurality of bits of data.
7. A communications receiver according to claim 6, wherein said correlator means comprises a plurality of multipliers and a plurality of integrators, one multiplier and one integrator being provided for each bit of said plurality of bits of data.
8. A communications receiver according to claim 7, wherein said correlator means further comprises a plurality of adders configured to sum outputs from said plurality of integrators, one adder being provided for each bit of said plurality of bits of data.
9. A communications receiver according to claim 8, wherein said adders are configured such that each adder produces an output indicative of the value of one bit of said plurality of bits of data.
10. A communications receiver according to claim 9, wherein the sign of each output indicates the value of one bit of said plurality of bits of data.
11. A communications receiver according to claim 8, 9 or 10, wherein each output indicates confidence in the output value.
12. A communications receiver according to claim 11, wherein confidence in each value is indicated by the magnitude of each respective output, said magnitude indicating signal strength of the received analogue signal.
13. A communications receiver according to any preceding claim, further comprising filtering means to filter said encoded analogue signal.
14. A communications receiver according to any preceding claim, further comprising an integrator taking as input samples from said sampling means, and performing integration on said samples, the result of said integration being input to said analogue decoder means.
15. A communications receiver according to any preceding claim, wherein said encoded analogue signal is encoded using turbo coding, LDPC coding or convolutional coding.

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16. A communications receiver according to any preceding claim, wherein said analogue decoder has a plurality of inputs, and is configured to receive a plurality of analogue samples in parallel.
17. A communications receiver according to claim 16, wherein the communications receiver further comprises a sample and hold circuit for each input of the analogue decoder.
18. A method for receiving and processing a signal comprising: receiving an encoded analogue signal; sampling said encoded analogue signal to obtain a plurality of temporally spaced analogue sample values of said encoded analogue signal; receiving said analogue sample values at a decoder and generating an analogue decoded signal from said analogue sample values; and converting said decoded signal to a digital signal.
19. A method according to claim 18, further comprising: correlating said encoded analogue signal to generate a signal suitable for input to said sampling means.
20. A method according to claim 18 or 19, wherein the receiver is configured to receive the analogue signal as a binary phase shift keying (BPSK) modulated signal.
21. A method according to claim 19, wherein the receiver is configured to receive the analogue signal as a MBOK modulated signal.
22. A method according to claim 21, wherein said modulated signal comprises a plurality of pulses, and each pulse represents a plurality of bits of data.
23. A method according to claim 22, wherein said correlating generates a plurality of values, and the sign of each output indicates the value of one bit of said plurality of bits of data.

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24. A method according to claim 23, wherein the magnitude of each output indicates signal strength of the received analogue signal and confidence in the bit value governed by its sign.
25. A method according to any one of claims 18 to 24, further comprising filtering said encoded analogue signal.
26. A method according to any one of claims 18 to 24, further comprising: integrating a signal output from said sampling; and passing a result of said integration to said analogue decoder means.
27. A method according to any one of claims 17 to 25, wherein said encoded analogue signal is encoded using turbo coding, LDPC coding or convolutional coding.
28. A method for receiving and processing a signal substantially as hereinbefore described, with reference to Figures 2 to 6 of the accompanying drawings.
29. A communications receiver substantially as hereinbefore described, with reference to Figures 2 to 6 of the accompanying drawings.