GB2411981B - Clock setting arrangement and method for computer motherboard - Google Patents

Clock setting arrangement and method for computer motherboard

Info

Publication number
GB2411981B
GB2411981B GB0405519A GB0405519A GB2411981B GB 2411981 B GB2411981 B GB 2411981B GB 0405519 A GB0405519 A GB 0405519A GB 0405519 A GB0405519 A GB 0405519A GB 2411981 B GB2411981 B GB 2411981B
Authority
GB
United Kingdom
Prior art keywords
computer motherboard
clock setting
setting arrangement
arrangement
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0405519A
Other versions
GB2411981A (en
GB0405519D0 (en
Inventor
Yen Sheng Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giga Byte Technology Co Ltd
Original Assignee
Giga Byte Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giga Byte Technology Co Ltd filed Critical Giga Byte Technology Co Ltd
Priority to GB0405519A priority Critical patent/GB2411981B/en
Publication of GB0405519D0 publication Critical patent/GB0405519D0/en
Publication of GB2411981A publication Critical patent/GB2411981A/en
Application granted granted Critical
Publication of GB2411981B publication Critical patent/GB2411981B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
GB0405519A 2004-03-11 2004-03-11 Clock setting arrangement and method for computer motherboard Expired - Fee Related GB2411981B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0405519A GB2411981B (en) 2004-03-11 2004-03-11 Clock setting arrangement and method for computer motherboard

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0405519A GB2411981B (en) 2004-03-11 2004-03-11 Clock setting arrangement and method for computer motherboard

Publications (3)

Publication Number Publication Date
GB0405519D0 GB0405519D0 (en) 2004-04-21
GB2411981A GB2411981A (en) 2005-09-14
GB2411981B true GB2411981B (en) 2006-08-23

Family

ID=32117492

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0405519A Expired - Fee Related GB2411981B (en) 2004-03-11 2004-03-11 Clock setting arrangement and method for computer motherboard

Country Status (1)

Country Link
GB (1) GB2411981B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2133593A (en) * 1982-11-29 1984-07-25 Tektronix Inc A restart circuit for a digital processor
US5560017A (en) * 1990-11-09 1996-09-24 Wang Laboratories, Inc. System with clock frequency controller responsive to interrupt independent of software routine and software loop repeatedly executing instruction to slow down system clock
US5586309A (en) * 1992-06-11 1996-12-17 Sierra Semiconductor Corporation Universal programming interface for clock generators operable in a parallel programming mode and a serial programming mode
US6457137B1 (en) * 1999-05-28 2002-09-24 3Com Corporation Method for configuring clock ratios in a microprocessor
US20030065966A1 (en) * 1999-09-29 2003-04-03 Poisner David I. Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2133593A (en) * 1982-11-29 1984-07-25 Tektronix Inc A restart circuit for a digital processor
US5560017A (en) * 1990-11-09 1996-09-24 Wang Laboratories, Inc. System with clock frequency controller responsive to interrupt independent of software routine and software loop repeatedly executing instruction to slow down system clock
US5586309A (en) * 1992-06-11 1996-12-17 Sierra Semiconductor Corporation Universal programming interface for clock generators operable in a parallel programming mode and a serial programming mode
US6457137B1 (en) * 1999-05-28 2002-09-24 3Com Corporation Method for configuring clock ratios in a microprocessor
US20030065966A1 (en) * 1999-09-29 2003-04-03 Poisner David I. Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate

Also Published As

Publication number Publication date
GB2411981A (en) 2005-09-14
GB0405519D0 (en) 2004-04-21

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20190311