GB2392261A - Method and device for computing an absolute differece - Google Patents
Method and device for computing an absolute differece Download PDFInfo
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- GB2392261A GB2392261A GB0219199A GB0219199A GB2392261A GB 2392261 A GB2392261 A GB 2392261A GB 0219199 A GB0219199 A GB 0219199A GB 0219199 A GB0219199 A GB 0219199A GB 2392261 A GB2392261 A GB 2392261A
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- 238000012544 monitoring process Methods 0.000 claims 5
- 238000007792 addition Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
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- 230000004075 alteration Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/544—Indexing scheme relating to group G06F7/544
- G06F2207/5442—Absolute difference
Abstract
Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders (24) . The second value is subtracted from the first value using the propagate terms to yield a subtraction difference. It is determined at one or more correctors (26) whether the subtraction difference is negative. If the subtraction difference is negative, the subtraction difference is modified according to the propagate terms to compute an absolute difference between the first value and the second value. Otherwise, the subtraction difference is reported as the absolute difference between the first value and the second value.
Description
- 1 r39226 1 METHOD AND DEVICE FOR COMPUTING AN ABSOLUTE DIFFERENCE
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of arithmetic
and logic units and, more specifically, to a method and device for computing an absolute difference.
BACKGROUND OF THE INVENTION
Calculating an absolute difference between two values using an arithmetic and logic unit involves determining the positive.
À À. difference between the two values Merely subtracting one value from the other value does not necessarily yield the absolute difference, since the subtraction may yield a negative difference. Typically, other calculations are performed to determine whether a difference is negative and to change a negative difference to a positive difference. Consequently, efficiently calculating an absolute difference has posed challenges SUMMARY OF THE INVENTION
In accordance with the present invention, disadvantages and problems associated with previous techniques for calculating an absolute difference may be reduced or eliminated.
According to one embodiment of the present invention, computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders The second value is subtracted from the first value using the propagate terms to yield a subtraction difference. It is determined at one or more correctors whether the subtraction difference is negative. If the subtraction difference is negative, the subtraction difference is modified according to the propagate terms to compute an absolute difference between the first value and the second value Otherwise, the subtraction
- 2 difference is reported as the absolute difference between the first value and the second value.
Certain embodiments of the invention may provide one or more technical advantages. A technical advantage of one embodiment may be that a subtraction difference between two values is calculated and corrected if needed in order to determine the absolute difference between the two values The embodiment may require fewer computations than techniques that, for example, perform multiple subtractions to determine one absolute difference. Another technical advantage of one embodiment may be that a propagate term computed during the calculation of the subtraction difference is used to correct the subtraction difference Using the already computed propagate term reduces the need to perform additional calculations to correct the subtraction difference. Accordingly, the embodiment may provide for a more efficient manner of calculating an absolute difference.: Certain embodiments of the invention may include none, some, or all of the above technical advantages. One or more other technical advantages may be readily apparent to one skilled in the art from the figures, descriptions, and claims
included herein BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and its features and advantages, reference is now made to the following description, taken in conjunction with the
accompanying drawings, in which: FIGURE 1 is a diagram illustrating one embodiment of an absolute difference device for calculating an absolute difference between two values; FIGURE is diagram illustrating one embodiment of one-bit absolute difference unit; and
- 3 -:
FIGURE 3 is a flowchart illustrating one embodiment of a method for calculating an absolute difference between two values. DETAILED DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention and its advantages may be understood by referring to FIGURES 1 through 3 of the drawings, like numerals being used for like and corresponding parts of the various drawings.
FIGURE 1 is a diagram illustrating one embodiment of an..
absolute difference device 10 for calculating an absolute....
difference between two values. Given two values A and B. either A - B or B - A yields the absolute difference |A-B|=|B-A|..
Basically, if A > B. then A - B yields the absolute difference; if A < B. then B - A yields the absolute difference; and if A = B. then either A - B or B - A yields the absolute difference.
According to the embodiment, absolute difference device 10 calculates propagate terms in order to subtract one value from another value to determine a subtraction difference. The subtraction difference is checked to determine whether the subtraction difference is positive or negative. If the subtraction difference is negative, absolute difference device 10 uses the propagate terms to modify the subtraction difference to generate the absolute difference.
Absolute difference device 10 comprises p one-bit absolute difference units 20, where p indicates the number of bits of input values A and B that may be processed by absolute difference device 10. The bits of A may be represented by A[n], where A = A [ p-l],..., A[n],..., A[0], and p-1 indicates the most significant bit. The bits for B may be written in a .. slmllar manner.
A one-bit absolute difference unit 20 comprises an inverter 22, an adder 24, and a corrector 26. To subtract B from A, the
- 4 - negative of B. represented by -B. is calculated and added to A. -B is calculated by inverting bits B[n] using inverter 22 and adding one to the inverted bits. Adder 24 adds A[n3 and -B[n] to calculate a subtraction difference term S[n] that is used to generate subtraction difference S = S[p-l],..., S[n],..., S[0].
Adder 24 receives a carry in term Cln [I] and outputs a carry out term COut[n], where Ci=[n+1] = COut[n]. Carry in term Cin[n] is used to calculate S[n], and carry out term COut[nJ is used to calculate S[n+l]. Adder 24 calculates a propagate term P[n] in order to add A[n] and -B[n]. Adder 24 may add A[n] and -B[n}..
according to the values listed in TABLE 1. Adder 24 is..
described in more detail in reference to FIGURE 2.
TABLE 1 À
A[n] B[n] Cin Cout S[n].... À-. O O 1 O 1 À.
O 1 O O 1
1 O O.. _ 1
1 _ o- 1 O 1 O
1 1 1 1
Corrector 26 receives subtraction difference term S[n] from adder 24 and determines whether subtraction difference term S[n] needs to be modified to generate an absolute difference. If needed, corrector 26 modifies subtraction difference term S[n] using propagate term P[n] to generate an absolute difference term ABS[n] that is used to form absolute difference ABS = ABS[p-l],..., ABS[n],..., ABS[ O]. Corrector 26 receives carry in term Con] and outputs carry out term COut[n]. Corrector 26 is described in more detail with reference to FIGURE 2.
- 5 FIGURE 2 is diagram illustrating one embodiment of one-bit absolute difference unit 20. One-bit absolute difference unit 20 includes adder 24 and corrector 26.
Adder 24 comprises an addition gate 30, a not-OR (NOR) gate 32, AND gates 34 and 36, an OR gate 38, and an addition gate 39.
Addition gate 30 generates propagate term P[n] from inputs A[n] and B[n]. Propagate term P[n] is used to indicate that if A [n] = 1 and B[n] = 0, or if A [n] = 0 and B[n] = 1, then carry in term Cln [n] equals carry out term COu[n]. NOR gate 32 is used to generate kill term K[n], which is used to indicate that if A[n] = B[n] = 0, then carry out term COUL[n] = 0. AND gate 34 is Àe.e used to calculate generate term G[n], which is used to indicate that if A[n] = B[n] = 1, then carry out term Cout = 1.
AND gate 36 and OR gate 38 generate carry out term COut[n] from input carry in term Cin [n] according to the rules specified by generate term G[n], kill term K[n], and propagate term P[n].
In this example, AND gate 36 and OR gate 38 generate carry out term COu[n] according to propagate term P[n] even though propagate term P[n] is not used as an input. Addition unit 39 generates subtraction difference term S[n] from carry in term Cin[n] and propagate term P[n].
Corrector 26 comprises an inverter 40, a multiplexer (MUX) 42, an addition gate 44, and an AND gate 46. Inverter 40 inverts carry in term Cin[n] to generate Cin'[n]. Multiplexer 42 determines whether the subtraction difference S is positive or negative. If the subtraction difference S is negative, multiplexer 42 determines whether subtraction difference term S[n] needs to be inverted, and signals addition unit 44 to invert the subtraction difference term S[n] if needed.
Multiplexer 42 may check the most significant bit of the subtraction difference S[p-l] to determine if the subtraction difference is positive or negative. If S[p-1] = 0, then the subtraction difference is positive, and if S[p-l] = 1, then the subtraction difference is negative. If the subtraction
difference is positive, multiplexer 42 transmits a value of zero to addition unit 44. If the subtraction difference is negative, multiplexer 42 checks CiT,' [I] to determine whether subtraction difference term S[n] needs to be inverted. If Ci, [n] = 0, then multiplexer 42 signals addition unit 44 to not invert subtraction difference term S[n]. If Cin'[n] = 1, then multiplexer 42 signals addition unit 44 to invert subtraction difference term S[n]. AND gate 46 receives carry in term Cin[] and propagate term P[n] to generate carry out term Coup [n].
FIGURE 3 is a flowchart illustrating one embodiment of a method for calculating an absolute difference between two values. According to the embodiment, propagate terms are calculated in order to subtract one value from another value tonne yield a subtraction difference. The subtraction difference is checked to determine whether the subtraction difference is positive or negative. If the subtraction difference is negative, the subtraction difference is modified using the propagate terms to generate the absolute difference.
The method begins at step 100, where A and B are received at absolute difference device 10. To illustrate the method, the absolute difference is calculated for two pairs of values, pair Al and Bl and pair A2 and B2, where Al = B2, and A2 = B1. In practice, however, the absolute difference for only one pair of values is typically calculated. According to one embodiment, the method performs one subtraction A - B in order to determine the absolute difference |A - B|. In contrast, other techniques require calculating both A - B and B - A and selecting the correct result in order to determine the absolute difference |A - B|. In the illustrated example, Al = B2 = 01101111 in the base 2 number system, which equals 111 in the base 10 number system, and B1 = A2 = 00100111 in base 2, which equals 39 in base 10.
For values Al and B1, Al - B1= 010010002, which equals 72lo' yields the absolute difference because Al > B1. The difference A2 - B2=
- 7 1Ol110002, which is equal to -72lo, does not yield the absolute difference because A2 < B2.
To subtract B from A, the negative of B. represented by -B.
is formed at step 102. -B may be formed by inverting each B[n] at inverters 22 and setting Cin [0] = 1. As used in this document, "each" refers to each member of a set or each member of a subset of a set. In the illustrated example, the negative of B: is -Bl = ll0ll000, and the negative of B2 is -B2 = l00l0000.
Propagate terms for A and -B are determined at step 104. The propagate terms P[n] may be determined at addition units 30., according to Equation (l):.
P[n] = A[n] XOR B[n] ( 1) À À ' In the illustrated example, the propagate terms P[n] may be described by Equations (2):....
A,-B,01101111 A,
+11011000 B.
10110111 Pl[n] (2) A2-B200100111 A2
+ lOQl B2 10110111 P2[n] The carry terms for A and -B are determined at step 106.
In the illustrated example, the carry terms Cin[n] = Coup [n-l] = C[n-l] may be determined at AND gate 36 and OR gate 38 according to Equation (3) : Con] = A[n] AND B[n] + BEn] AND Cin[n] + A[n] AND Cln[n] (3) The carry terms C[n-l] may be described by Equations (4);
- 8 Al-Bi 01101111 Al +11011000 Be 10110111 [in] 111111111 C'[n-l] (4) A2 - B2 0010011 1 A2
+10010000 B2
10110111 P2[n] 000001111 C2[-1]
Subtraction difference S is calculated at step 108. The subtraction difference terms S[n] may be determined at addition gate 39 according to Equation (5):..
S[n] = P[n] FOR C[n -1] ( 5) À In the illustrated example, the subtraction difference terms S[n] may be described by Equations (6): À A- B,01101111 A,
+ 11011000 B.
10110111 [in]...... 111111111 Cl[n-l].. 01001000 5 [n]....
(6) A2-B2 00100111 A2
10010000 B2
10110111 P2[n] 0 01111 C2[n-1] 0011 1000 S2[n] The subtraction difference is checked at multiplexer 42 to determine whether subtraction difference A - B is positive or zero at step llO. The most significant bit of the subtraction difference, or the most significant subtraction difference term, indicates whether the subtraction difference is positive or zero. For example, S[p-1] = 0 indicates that the subtraction difference is positive or zero, and S[p-l] = l indicates that the subtraction difference is negative. In the illustrated example, Sl[7] = 0, indicating that the subtraction difference Al- Al is positive or zero. In contrast, S2[7] = 0, indicating that the subtraction difference A2 - B2 is negative. If the subtraction difference is positive or zero at step 112, the method proceeds to step 114, where the absolute difference |A
I. - 9 -
B| is reported. In the illustrated example, subtraction difference Al - B1 is reported as the absolute difference |A1 -
B1l After reporting the absolute difference |A - B|, the method terminates If the subtraction difference is negative at step 112, the method proceeds to step 116, where group propagate terms are determined The group propagate terms are determined from the propagate terms and are used to invert incorrect bits of the subtraction difference in order to generate the absolute difference. Propagate terms include a first false propagates À À. term P[k], which indicates that subtraction difference termite.
Àe S[k+l] immediately following requires inversion Group propagate terms GP[n] may be calculated at multiplexer 42..
according to Equation (7):....
À - - À GP[n] = P[n] AND P[n -1] AND P[n - 2] AND... ( 7).
: Accordingly, if P[n] = 0, then GP[j] = 0 for j = n,..., p. In the illustrated example, group propagate terms GP[n] for A2 - B2 may be described by Equation (8): A2 - B2 0010011 1 A2
10010000 B2
10110111 p2[n] 000001111 C2[n-1] (8) 10111000 S2[n] 00000111 GP2[n] Group propagate terms indicate which bits of the subtraction difference need to be inverted to generate an absolute difference. The subtraction difference is modified according to the group propagate terms to generate the absolute difference |A -
B| at step 118 The subtraction difference may be modified by inverting bits of the subtraction difference according to the
1' as_ - 10 group propagate terms at addition unit 44. According to one embodiment, the subtraction difference terms may be inverted by modifying corresponding propagate terms. This inversion may be performed according to the relationship described by Equations (I): P[n] XOR C[n -1] = S[IZ] ( 9) P[n] XOR C[n-] = S[n] A modified propagate term PM[n] may be defined by Equation (10):..
PM [n] = P[n] XNOR GP[n - 1] (10) Accordingly, a modified propagate term PM[n] = P[n] if GP[n-l] =.
1, and PM[n] = P[n] if GP[n-l]. The absolute difference |A - B| is reported at step 122. After reporting the absolute..
difference |A - B|, the method terminates. À.
Certain embodiments of the invention may provide one or more technical advantages. A technical advantage of one embodiment may be that a subtraction difference between two values is calculated and corrected if needed in order to determine the absolute difference between two values. The embodiment may require fewer computations than techniques that, for example, perform multiple subtractions to determine one absolute difference. Another technical advantage of one embodiment may be that a propagate term computed during the calculation of the subtraction difference is used to correct the subtraction difference. Using the already computed propagate term reduces the need to perform additional calculations to correct the subtraction difference. Accordingly, the embodiment may provide for a more efficient manner of calculating are absolute difference.
Although an embodiment of the invention and its advantages are described in detail, a person skilled in the art could make
- 11 -
various alterations, additions, and omissions without departing from the spirit and scope of the present invention as defined by the appended claims.
À. À À À Àe Àe À À À. À. À.. À - À- À À-e. À À À À À-
Claims (20)
1. A method for computing an absolute difference, comprising: receiving a first value and a second value; determining a plurality of propagate terms according to the first value and the second value at one or more adders; subtracting the second value from the first value using the propagate terms to yield a subtraction difference; determining at one or more correctors whether thee..
À À- subtraction difference is negative; À.
Àe modifying the subtraction difference according to the propagate terms to compute an absolute difference between the:.
. first value and the second value, if the subtraction differences,.
is negative; and....
À reporting the subtraction difference as the absolute .. difference between the first value and the second value.
otherwise.
2. The method of Claim 1, wherein determining the
propagate terms according to the first value and the second value at the adders comprises applying an exclusive-or operation to each bit of a first sequence of bits corresponding to the first value and to each bit of a second sequence of bits corresponding to the second value.
3 The method of Claim 1 or Claim 2, wherein determining at the correctors whether the subtraction difference is negative comprises: selecting a most significant subtraction difference bit of the subtraction difference; and determining whether the subtraction difference is negative according to the most significant subtraction difference bit
r-_, - 13
4 The method of Claim 1, Claim 2 or Claim 3, wherein modifying the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value comprises: determining a false propagate term, the propagate terms comprising the false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; and modifying the subtraction difference according to the false propagate term. I..
5 The method of Claim 1, Claim 2 or Claim 3, wherein modifying the subtraction difference according to the propagate..
terms to compute the absolute difference between the first value...
and the second value comprises:....
determining a false propagate term, the propagate terms comprising the false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; and inverting one or more bits of the subtraction difference according to the false propagate term to modify the subtraction difference, the one or more bits comprising a bit corresponding to the false propagate term and a most significant subtraction difference bit
6 The method of Claim 1, Claim 2 or Claim 3, wherein modifying the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value comprises: determining a false propagate term, the propagate terms comprising the false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; and
changing one or more of the propagate terms according to the false propagate term to modify the subtraction difference.
7. The method of Claim 1, wherein modifying the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value comprises: generating a plurality of group propagate terms according to the propagate terms, the propagate terms comprising the false propagate term, the false propagate term corresponding to aid..
incorrect bit of the subtraction difference; I. monitoring the group propagate terms to detect the false propagate term; and '..
modifying the subtraction difference according to the false.
propagate term.
À
8. The method of Claim 1, Claim 2 or Claim 3, wherein modifying the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value comprises: generating a plurality of carry terms according to the propagate terms; and modifying the subtraction difference according to the carry terms.
9. The method of Claim 1, Claim 2 or Claim 3, wherein modifying the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value comprises: generating a plurality of carry terms according to the propagate terms, the propagate terms comprising a false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference;
À 15 monitoring the carry terms to detect the false propagate term; and modifying the subtraction difference according to the carry terms.
10. A device for computing an absolute difference, comprising: one or more adders operable to: receive a first value and a second value; determine a plurality of propagate terms according to.',.
the first value and the second value; and.' subtract the second value from the first value using the propagate terms to yield a subtraction difference;, one or more correctors, each corrector coupled to an adder ' I.,.
and operable to: -e'..a determine at one or more correctors whether the subtraction difference is negative; modify the subtraction difference according to the propagate terms to compute an absolute difference between the first value and the second value, if the subtraction difference is negative; and report the subtraction difference as the absolute difference between the first value and the second value, otherwise.
11. The device of Claim 10, wherein the correctors are operable to determine the propagate terms according to the first value and the second value at the adders by applying an exclusive-or operation to each bit of a first sequence of bits corresponding to the first value and to each bit of a second sequence of bits corresponding to the second value.
12 The device of Claim 10 or Claim 11, wherein the correctors are operable to determine whether the subtraction difference is negative by: selecting a most significant subtraction difference bit of the subtraction difference; and determining whether the subtraction difference is negative according to the most significant subtraction difference bit
13 The device of Claim 10, Claim 11 or Claim 12, wherein the correctors are operable to modify the subtraction differences..
according to the propagate terms to compute the absolute difference between the first value and the second value by determining a false propagate term, the propagate terms À. comprising the false propagate term, the false propagate Her corresponding to an incorrect bit of the subtraction difference;..,.
À and.. * À À modifying the subtraction difference according to the false* propagate term
14 The device of Claim 10, Claim 11 or Claim 12, wherein the correctors are operable to modify the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value by: determining a false propagate term, the propagate terms comprising the false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; and inverting one or more bits of the subtraction difference according to the false propagate term to modify the subtraction difference, the one or more bits comprising a bit corresponding to the false propagate term and a most significant subtraction difference bit
- - - 17
15 The device of Claim 10, Claim 11 or Claim 12, wherein the correctors are operable to modify the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value by: determining a false propagate term, the propagate terms comprising the false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; and changing one or more of the propagate terms according to the false propagate term to modify the subtraction difference
16 The device of Claim 10, Claim 11 or Claim 12, wherein the correctors are operable to modify the subtraction difference according to the propagate terms to compute the absolute I difference between the first value and the second value by: A..
generating a plurality of group propagate terms according..
À. to the propagate terms, the propagate terms comprising the false propagate term, the false propagate term corresponding to an..
incorrect bit of the subtraction difference; À....
monitoring the group propagate terms to detect the false....
propagate term; and modifying the subtraction difference according to the false.
propagate term.
17 The device of Claim 10, Claim 11 or Claim 12, wherein the correctors are operable to modify the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value by: generating a plurality of carry terms according to the propagate terms; and modifying the subtraction difference according to the carry terms
-
18 18. The device of Claim 10, Claim 11 or Claim 12, wherein the correctors are operable to modify the subtraction difference according to the propagate terms to compute the absolute difference between the first value and the second value by: generating a plurality of carry terms according to the propagate terms, the propagate terms comprising a false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; monitoring the carry terms to detect the false propagate term; and modifying the subtraction difference according to the carry terms.
19. A device for computing an absolute difference, I comprising: A..
means for receiving a first value and a second value;..
À. means for determining a plurality of propagate terms according to the first value and the second value at one or more À. - adders; À.. means for subtracting the second value from the first value....
using the propagate terms to yield a subtraction difference;.
À À means for determining at one or more correctors whether the subtraction difference is negative; means for modifying the subtraction difference according to the propagate terms to compute an absolute difference between the first value and the second value, if the subtraction difference is negative; and means for reporting the subtraction difference as the absolute difference between the first value and the second value, otherwise.
20. A method for computing an absolute difference, comprising: receiving a first value and a second value;
- 19 determining a plurality of propagate terms according to the first value and the second value at one or more adders by applying an exclusiveor operation to each bit of a first sequence of bits corresponding to the first value and to each bit of a second sequence of bits corresponding to the second value; subtracting the second value from the first value using the propagate terms to yield a subtraction difference; determining at one or more correctors whether the subtraction difference is negative by selecting a most significant subtraction difference bit of the subtraction difference, and determining whether the subtraction difference is negative according to the most significant subtraction difference bit; modifying the subtraction difference according to that propagate terms to compute an absolute difference between the first value and the second value, if the subtraction difference is negative, by: generating a plurality of group propagate terms according to the propagate terms, the propagate terms comprising the false propagate term, the false propagate term corresponding to an incorrect bit of the subtraction difference; monitoring the group propagate terms to detect the false propagate term; and inverting one or more bits of the subtraction difference according to the false propagate term to modify the subtraction difference, the one or more bits comprising a bit corresponding to the false propagate term and a most significant subtraction difference bit; and reporting the subtraction difference as the absolute difference between the first value and the second value, otherwise
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0219199A GB2392261B (en) | 2002-08-19 | 2002-08-19 | Device for computing an absolute difference |
| US10/640,453 US7191199B2 (en) | 2002-08-19 | 2003-08-13 | Method and device for computing an absolute difference |
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| GB0219199A GB2392261B (en) | 2002-08-19 | 2002-08-19 | Device for computing an absolute difference |
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| KR20050053135A (en) * | 2003-12-02 | 2005-06-08 | 삼성전자주식회사 | Apparatus for calculating absolute difference value, and motion prediction apparatus and motion picture encoding apparatus utilizing the calculated absolute difference value |
| US7386580B2 (en) * | 2004-03-18 | 2008-06-10 | Arm Limited | Data processing apparatus and method for computing an absolute difference between first and second data elements |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4218751A (en) * | 1979-03-07 | 1980-08-19 | International Business Machines Corporation | Absolute difference generator for use in display systems |
| JPS58132861A (en) * | 1982-02-03 | 1983-08-08 | Toshiba Corp | Arithmetic circuitry |
| EP0295788A2 (en) * | 1987-05-15 | 1988-12-21 | Digital Equipment Corporation | Apparatus and method for an extended arithmetic logic unit for expediting selected operations |
| US4982352A (en) * | 1988-06-17 | 1991-01-01 | Bipolar Integrated Technology, Inc. | Methods and apparatus for determining the absolute value of the difference between binary operands |
| US5251164A (en) * | 1992-05-22 | 1993-10-05 | S-Mos Systems, Inc. | Low-power area-efficient absolute value arithmetic unit |
| US5610850A (en) * | 1992-06-01 | 1997-03-11 | Sharp Kabushiki Kaisha | Absolute difference accumulator circuit |
| US5835389A (en) * | 1996-04-22 | 1998-11-10 | Samsung Electronics Company, Ltd. | Calculating the absolute difference of two integer numbers in a single instruction cycle |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5813286A (en) | 1981-07-15 | 1983-01-25 | 中日クリ−ナ−工業株式会社 | Method of discarding and treating pipe |
| JPH0776911B2 (en) * | 1988-03-23 | 1995-08-16 | 松下電器産業株式会社 | Floating point arithmetic unit |
| KR0146065B1 (en) * | 1994-10-18 | 1998-09-15 | 문정환 | Absolute value calculating circuit |
-
2002
- 2002-08-19 GB GB0219199A patent/GB2392261B/en not_active Expired - Fee Related
-
2003
- 2003-08-13 US US10/640,453 patent/US7191199B2/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4218751A (en) * | 1979-03-07 | 1980-08-19 | International Business Machines Corporation | Absolute difference generator for use in display systems |
| JPS58132861A (en) * | 1982-02-03 | 1983-08-08 | Toshiba Corp | Arithmetic circuitry |
| EP0295788A2 (en) * | 1987-05-15 | 1988-12-21 | Digital Equipment Corporation | Apparatus and method for an extended arithmetic logic unit for expediting selected operations |
| US4982352A (en) * | 1988-06-17 | 1991-01-01 | Bipolar Integrated Technology, Inc. | Methods and apparatus for determining the absolute value of the difference between binary operands |
| US5251164A (en) * | 1992-05-22 | 1993-10-05 | S-Mos Systems, Inc. | Low-power area-efficient absolute value arithmetic unit |
| US5610850A (en) * | 1992-06-01 | 1997-03-11 | Sharp Kabushiki Kaisha | Absolute difference accumulator circuit |
| US5835389A (en) * | 1996-04-22 | 1998-11-10 | Samsung Electronics Company, Ltd. | Calculating the absolute difference of two integer numbers in a single instruction cycle |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2392261B (en) | 2005-08-03 |
| US20040034680A1 (en) | 2004-02-19 |
| GB0219199D0 (en) | 2002-09-25 |
| US7191199B2 (en) | 2007-03-13 |
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| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20180819 |