GB2386443A

GB2386443A - Predicting configurations in programmable devices

Info

Publication number: GB2386443A
Application number: GB0205820A
Authority: GB
Inventors: Jonathan David Lewis
Original assignee: Toshiba Research Europe Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 2002-03-12
Filing date: 2002-03-12
Publication date: 2003-09-17
Anticipated expiration: 2022-03-12
Also published as: GB0205820D0; GB2386443B

Abstract

A signal processing system comprising a processor, one or more reconfigurable devices (eg an FPGA) associated with the processor, a memory unit providing instructions to the processor relating to the functional configuration of the device and a control unit for controlling configuration of the device during processing. The system may use a variety of methods for controlling the configurations including checking whether a current configuration is suitable, looking ahead at future configuration requirements, predicting future requirements, matching current requirements with known/subsequent configurations and storing lists of past sequences and comparing with current sequences. Preferably, the signal processing system is for use in a mobile terminal such as a mobile phone or base station.

Description

M&C Folio: GBP84582 2386443 Controller for Hardware Accelerators The

present invention relates to systems and methods in the field of signal and data

processing, particularly controllers of signal processing hardware in a mobile telecommunications device and associated methods of control. In particular, the invention relates to third generation (3G) mobile telecommunications systems.

Traditionally, an algorithm is coded in software and implemented on a general purpose microprocessor. While this approach has a high degree of flexibility and may be achieved at a relatively low cost, it is generally a low performance option.

Alternatively, custom hardware may be designed and built to implement the given algorithm. This approach generally achieves a higher level of performance, but is a relatively expensive and inflexible approach. Therefore, overall the relative advantages of creating a custom hardware solution to a problem as opposed to a software-based solution have traditionally been based on cost and performance versus flexibility.

Various Digital Signal Processor (DSP) architectures have been devised to address performance/flexibility issues, such as parallel execution via deep pipelining and multiple execution units. One approach for exploiting instruction-level parallelism is the very long instruction word (VLIW) architecture. The VLIWs are created at compile time by grouping a number of basic instructions which are executable in parallel.

VLIW processors, which contain multiple functional units, fetch, from an instruction cache, a VLIW which contains several basic instructions, and dispatch the entire VLIW for parallel execution. Therefore VLIW processors have relatively simple control logic because they do not perform any dynamic scheduling nor reordering of operations, as is the case in most contemporary superscalar processors. Since the operational complexity has been moved from the hardware to the compiler, simpler and faster processors are achievable.

The Carmel_ DSP core provided by Infineon is a low power DSP core with a plurality of parallel execution units. This DSP uses a configurable long instruction word (CLIW) architecture, which allows combinations of execution units to be selected in order to achieve an optimal performance for specific computation steps, particularly for time-

critical algorithms. The CLIW has greater flexibility than the VLIW, as it allows the parallel use of a number of instructions that utilise several processing elements within the core. For example, the parallel use of a move instruction, Multiply-Accumulate Unit (MAC) instruction and an Arithmetic Logic Unit (ALU) instruction may be defined in a single C:LIW. The CLIWs are effectively reusable routines that remove the need to define an opcode specifically for the combination of instructions. Hence, in the main body of the code, these CLIW instructions can be called without having to use the complete definition of the combination, as would be done with VLIWs. Instead, a referral to the CLIW instruction is made. The advantage of this is that the number of opcodes can be reduced and/or the instruction word size can be reduced compared to a more standard VLIVV architecture.

Infineon also provide Power Plug_ modules for use with the Carmel DSP core. In operation CLIW instructions are defined so as to pass register/memory values to the Power Pinged module. This module then pefolllls user defined hardware operations on the operands and passes the result back to the register/memory in the core. Each module decodes its own instruction set, controls its own registers and implements the desired data path. The PowerPlug modules are tightly coupled to the core and are viewed by the software as built-in execution units of the DSP data path. This arrangement, however, can be costly in terms of hardware and opcodes to support the modules, as the module generally uses hard- wired logic, so a dedicated module is required for each specific function.

There is hence a need for a signal/data processing system that is capable of improved perforrnanee. There is also a need to overcome or alleviate at least one of the problems of the prior art.

According to one aspect, the present invention provides a signal processing system comprising a processor; one or more reconfigurable devices associated with the processor; a memory unit providing instructions to the processor relating to the functional configuration of the reconfigurable device; and a control unit for controlling configuration of the reconfigurable device during processing by the processor.

Reconfigurable devices, such as field programmable gate arrays (FPGAs), are a

compromise between a pure software solution and a pure hardware solution.

Reconfigurable devices are digital circuits that can be programmed by reconfigurable logic in order to dynamically create and modify custom digital circuits. This ability to create and modify digital logic without physically altering the hardware provides a more flexible and lower cost solution to the implementation of custom hardware.

Reconfigurable logic exploits program parallelism as programming is accomplished by mapping algorithms on demand to a pool of FPGAs. This approach of a FPGA assuming the logic design required to implement the algorithm is to be contrasted to that of a programmed digital signal processor (DSP) which executes a sequence of instructions on predefined hardware resources.

Because the function of the reconfigurable logic device is defined by software, design errors can be corrected without having to fabricate new hardware. Existing system hardware may also be modified and upgraded without any physical modifications. Only a change to the software used by the reconfigurable logic device is required.

Reconfigurable devices therefore offer an increased benefit in computational density over microprocessors, and for highly regular computations, reconfigurable architectures are generally superior to traditional processor architectures. However, on tasks with high functional diversity, microprocessors use custom hardware more efficiently than reconfigurable devices.

While reconfigurable devices have proven extremely efficient for processing tasks, their efficiency is improved in this aspect of the invention, by combining their usage with a controller that dynamically reconfigures the devices. For example, in earlier systems when a particular instruction for a routine was received for which the architecture was

not configured, a reconfigurable device had to be reconfigured, which took time out of the overall signal processing procedure, particularly when one or more other routines were dependent upon the outcome of that particular routine. Where FPGAs were used as the reconfigurable devices, a delay of hundreds of milliseconds to reprogram could be expected where the configuration files were large.

Applications such as 3G cellular handsets and associated hardware, such as base stations, can require a greater performance level, particularly in terms of MIPS, that a conventional DSP core cannot deliver. Hence, in a computing device, the time taken to configure the reconfigurable device may be significant in terms of multiple clock cycles, so the present invention seeks to address this problem.

In this regard, according to a related aspect, the present invention provides a method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of (a) receiving a processor instruction related to a required configuration; (b)checking the current configuration of the one or more reconfigurable devices, and: (i) where the current configuration of one of the reconfigurable devices matches the required configuration, allocating the use of that reconfigurable device for processing the required configuration; or (ii) where none of the existing configurations of the reconfigurable devices matches the required configuration, configuring one of the reconfigurable devices for processing the required configuration. According to a further aspect, the present invention provides a method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of: looking ahead a predetermined number of instructions to determine if a particular configuration is to be required; and where a

particular configuration is to be required subsequently, commencing configuration of a reconfigurable device before the particular configuration is required.

The present invention is therefore able to enhance the performance of existing hardware by making more efficient use of the available resources. That is, these further aspects of the present invention serve to minimise stalling of the processor. This is particularly important in mobile devices, where multi-mode operation, between second and third generation systems requires enhanced performance.

According to a still further aspect the present invention provides a method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of: determining if a reconfigurable device is to be configured; and effecting configuration during compile time or assembly time.

According to another aspect, the present invention provides a method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of: determining if a reconfigurable device is to be configured; and effecting configuration using deep pipelining.

These aspects of the invention are preferably utilised in a signal processing system of a mobile terminal or a mobile base station. By utilising reconfigurable accelerators in the mobile terminal processing system, the number of dedicated accelerators which would be required is reduced, which in turn reduces silicon size.

The present invention will now be described with reference to the following non-

limiting preferred embodiments in which: Figure 1 shows a processor architecture for implementing the present invention.

With reference to Figure 1, a processor core 1 is illustrated which includes a control unit 2. The control unit 2 obtains instructions from a main instruction memory 3 and a

Configuration/Instruction Memory 4. The main instruction memory 3 contains a list of general instructions, which include, among the general instructions, reference instructions 3a. The reference instructions 3a relate to a number of processes that are to be undertaken in parallel, and identify the relevant registers to used, as well as reference a configuration instruction 4a of the Configuration/Lnstruction memory 4 to be used.

The configuration instructions 4a of the Configuration/Instruction Memory defines the number of processes that are to occur in parallel and contain pointers to the relevant hardware configurations to undertake the parallel processing. Therefore, in effect, the Main Instruction Memory is a sub-routine index for the Configuration/Instruction Memory 4. In this regard, the Configuration/Instruction Memory 4 may utilise CLIWs.

At least one accelerator S is provided, which is a module used in conjunction with the processor core 1. Preferably interoperability between the one or more accelerators and the processor core is achieved by mapping accelerator registers in the I/O of the processor core, which respond to op-codes embedded in the configuration instructions.

The one or more accelerators are reconfigurable and operate by taking computation tasks away from the core and executing them on a generally high performance CPU.

The accelerator may be any reconfigurable device, such as a FPGA. Preferably the accelerator 5 is closely coupled with the core 1, particularly for low power mobile devices such as rllobile phones.

While the present invention will be generally described in relation to only one accelerator being coupled to the processor core, it is to be appreciated that the invention can readily be extrapolated to the use of multiple accelerators.

According to the present invention, normal instruction flow between the core 1 and the main instruction memory 3 will proceed until a reference instruction 3a is encountered.

The reference instruction 3a references a configuration instruction 4a in the configuration/instruction memory 4 which, will then be loaded into the control unit 2 as a result of the reference. The configuration instruction 4a preferably contains: - a pointer or reference to the hardware configuration that should be used for the instruction;

- a definition of how the required registers will be passed to the hardware accelerator; and - a definition of the other functions that will be performed in parallel.

In view of the larger amount of information conveyed by the configuration instruction 4a as compared with the reference instructions 3a, it is typically of much wider word size. With the configuration instruction loaded into the control unit, the control unit then loads the relevant hardware with the relevant configuration pointed at by the configuration instruction. The relevant hardware could be any combination of the one or more hardware accelerators S and/or one or more processing elements 7 internal to the processor core 1. The relevant registers and memory access results are also passed to the relevant internal processing elements 7 and/or hardware accelerator 5 which are to undertake the necessary processing before writing the results back to the relevant registers. It is to be appreciated that the whole of a hardware accelerator need not be dedicated to processing a particular task and that it is within the scope of this invention for a hardware accelerator to be divided into a plurality of "reconfigurable logic blocks", such as a row of a FPGA, each of which are able to be configured independently to process a particular task. In this regard, throughout the specification references to a

reconfigurable device are to therefore be understood as meaning a complete reconfigurable device or a portion thereof, such as a row.

It is also to be appreciated that the loading of the relevant hardware may be achieved by any means, but is preferably effected by direct memory access (DMA), or other such mechanism, between the configuration memory 6 and the hardware accelerator 5.

Having the configuration memory 6 directly accessible via the hardware accelerator S means that large amounts of data need not be passed through the processor core 1.

While typically the reconfigurable hardware accelerators are reconfigured as necessary and in as short a space of time as possible, the present invention provides a control mechanism which oversees the reconfiguring of the accelerator 5 in order to optimise its

performance. The control unit 2 preferably provides the control mechanism, although a secondary means may be provided in order to furnish this functionality.

In a first embodiment of the inventive method of the present invention, the controller maintains a record of the current configuration of the accelerator, which is checked before attempting to reconfigure the accelerator. This means that the existing configuration-can be reutilised where possible. Where a configuration is indicated as being active, then the instruction can be acted upon immediately. If a new configuration is required, then this may be initiated whilst the processor is stalled, or while instructions that do not require a result from the new configuration are processed. This control arrangement is therefore capable of increasing the processing speed of the processor core/accelerator combination. In particular, if, for example, a large number of a single instruction were to be executed in a loop, it would only be the first instruction that could require the accelerator to be reconfigured and hence only the first instruction that could stall the processor if configuration were required. Hence, in such a situation, the need to configure on decoding the first usage of an instruction would not be such a large overhead.

Alternatively, a table or other form of record could be maintained which indicates the last known or cu'er.t configuration change from each reconfigurable accelerator. This could be stored within a storage means of the control unit, external memory or within the configuration instruction memory. Where stored within the configuration instruction memory, the memory should be RAM rather than ROM. This is feasible, as the size of the configuration instruction memory should be quite small and could be loaded as part of the boot process from ROM.

Preferably a look-ahead mechanism is utilised so that, if preconfiguration is required, it occurs before the accelerator configuration is required. For example, the control mechanism may, when a particular instruction is being executed, look a number of instructions ahead to see what configurations are to be shortly required.

In a second embodiment, configuration of the accelerator is effected before it is required, during compile time or assembly time. For example, when creating the

compilation or assembly code, the compiler or assembler, as applicable, may automatically insert a special configuration instruction in advance of a hardware accelerator actually requiring the configuration. Preferably the special instruction is placed so that the configuration of the accelerator is completed just in time for the instruction to be executed without stalling the processor. This embodiment of the invention is particularly applicable to linear code.

It is to be appreciated that this second embodiment of the invention may be combined with any other embodiments of the invention, including the first embodiment, whereby the controller also maintains a record of the last configuration, and only reconfigures the accelerator during compile or assembly time if the accelerator is not already so configured. In a third embodiment of the invention, configuration of the accelerator is effected before it is required using deep pipelining. Pipelining involves sequentially processing instructions in terms of the four steps "fetch", "decode", "execute" and "store". There are numerous variations in terms of the number of clock cycles to utilise for completing these steps. For example, in a two stage pipeline, the fetch and decode steps would be performed in a single clock cycle, while execute and store were performed in another.

With a four stage pipeline, on the other hand, each step would be performed in a single clock cycle.

In this third embodiment of the invention, the timing of pipeline is determined so that there is sufficient time between the decode and execution stages for configuration of the accelerator to occur. In this way, the accelerator is configured before the execution stage commences, so that the processor is not stalled. This third embodiment of the invention may also be combined with any other embodiment, including the first embodiment, whereby the controller also maintains a record of the last configuration, and only reconfigures the accelerator between the fetch and decode steps if the accelerator is not already configured.

In a fourth embodiment of the invention, configuration of the accelerator is effected through prediction. In this approach, different blocks of instruction memory could be

identified with different configurations. The controller within the processor would then predict, during run-time, that a particular configuration would be required based upon the current program pointer value and pre-configure the accelerator accordingly.

Preferably where reconfiguration is required, it is effected before the particular configuration is required.

In a fifth embodiment of the invention, configuration of the accelerator is effected before it is required based upon history. For example, a given configuration could be automatically reconfigured according to the last known or current transition. That is, each configuration could have an associated "most likely" transition field. This could

be the last transition that was made from this configuration. Alternatively, the controller may have a record of configuration sequences that are likely to occur, such that the controller pre- configures the accelerator based upon a particular sequence occurring.

That is, the record may indicate that where configuration A followed by configuration B occurs, configuration C is likely to next occur.

In a sixth embodiment of the invention, configuration is effected manually using special opcodes available to the programmer which enable pre-configuration.

it is to be appreciated that the fourth, fifth and sixth erhodi.ments of the invention may readily additionally be combined with the first embodiment, whereby the controller also maintains a record of the last configuration, and only reconfigures the accelerator if the accelerator is not already so configured. Further, any other combination of the embodiments is within the scope of this invention.

Also, with these embodiments, in order to prevent the controller reconfiguring an accelerator before it has finished an existing instruction, the decision to commence reconfiguration could be made based upon an inserted op-code that indicates that a configuration is finished with. Alternatively a time-out mechanism could be used.

Variations and additions are possible within the general inventive concept as will be apparent to those skilled in the art. For example, the allocation of resources need not apply to the accelerator as a whole, but may apply to a component of the accelerator,

such as a reconfigurable row in an FPGA.

It will be appreciated that the broad inventive concept of the present invention may be applied to any field utilising reconfigurable computing, and the embodiments shown are

intended to be merely illustrative and not limiting. For example the present invention may be utilised to enhance signal processing in areas such as encryption/decryption, compression; sequence and string matching, sorting, physical system simulation' video and image processing and specialized arithmetic.

Claims

CLAIMS:

1. A signal processing system comprising: a processor; one or more reconfigurable devices associated with the processor; a memory unit providing instructions to the processor relating to the functional configuration of the reconfigurable device; and a control unit for controlling configuration of the reconfigurable device during processing by the processor.

2. The signal processing system of claim 1 wherein the one or more reeonfigurable device is a field programmable gate array.

3. The signal processing system according to any preceding claim wherein the control unit is adapted to: receive information related to a required functional configuration; check the current configuration of the reconfigurable devices; and where the current configuration of one of the reconfigurable devices matches the required functional configuration, allocating use of that reeonfigurable device without reconfiguration.

4. The signal processing system of claim 3 further including a look ahead mechanism for looking ahead a predetermined number of processor instructions to determine in advance which functional configurations are to be required in the future.

5. The signal processing system according to any preceding claim further comprising a predictor for predicting the next functional configuration to be required by the processor.

6. The signal processing system according to claim 5 wherein the predictor comprises:

storage means for storing a list of known configurations and associated subsequent configurations; and a comparator for comparing the current configuration of a configurable device with the list of known configurations, and where the current configuration matches an entry in the list of known configurations, the subsequent configuration associated with the matched entry is determined as the next configuration to be required by the processor.

7. The signal processing system of claim 5 wherein the predictor comprises: sequence storage means for storing a list of configuration sequences and the corresponding next configurations associated with each configuration sequence; and a comparator for comparing a sequential list of previous configurations of a reconfigurable device with the list of configuration sequences, and where they match, the corresponding next configuration associated with the matched entry is determined as the next configuration to be required by the processor.

8. The signal processing system of claim 4, 5, 6 or 7 such that, where reconfiguration of a reconfigurable device is required, reconfiguration is completed before the reconfigurable device is required.

9. A method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of: a) receiving a processor instruction related to a required configuration; b) checking the current configuration of the one or more reconfigurable devices, and: (iii) where the current configuration of one of the reconfigurable devices matches the required configuration, allocating the use of that reconfigurable device for processing the required configuration; or

(ivy where none of the existing configurations of the reconfigurable devices matches the required configuration, configuring one of the reconfigurable devices for processing the required configuration.

10. The method of claim 9, further comprising the step of: looking ahead a predetermined number of instructions to determine if a particular configuration is to be required shortly; and where a particular configuration is to be required shortly, commencing step (b) before the particular configuration is required.

11. A method of controlling the configuration of one or more reconf gurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of: looking ahead a predetermined number of instructions to determine if a particular configuration is to be required; and where a particular configuration is to be required subsequently, commencing configuration of a reconfigurable device before the particular configuration is required.

12. The method according to any one of claims 9 to 11 wherein if a particular configuration is required and a reconfigurable device is to be configured, effecting configuration during compile time or assembly time.

13. A method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconfigurable devices associated with the processor, the method comprising the steps of: determining if a reconfigurable device is to be configured; and effecting configuration during compile time or assembly time.

14. The method according to any one of claims 9 to 11 wherein if a particular configuration is required and a reconfigurable device is to be configured, effecting configuration using deep pipelining.

1S. A method of controlling the configuration of one or more reconfigurable devices in a communication system comprising a processor and the one or more reconf gurable devices associated with the processor, the method comprising the steps of: determining if a reconfigurable device is to be configured; and effecting configuration using deep pipelining.

16. A reconfigurable device controller for performing a method according to any one of claims 9 to IS.

17. The reconfigurable device controller of claim 16 for use in a mobile communications device.

18. A mobile communication terminal comprising a signal processing system according to any one of claims 1 to 8.

19. A mobile communication base station comprising a signal processing system according to any one of claims 1 to 8.

20. A signal processing system substantially as herein described with reference to the accompanying drawing.

21. A method of controlling the configuration of one or more reconfigurable devices in a communication system substantially as herein described with reference to the accompanying drawing.