GB2375677A

GB2375677A - Separate horizontal and vertical compression for Picture in Picture display

Info

Publication number: GB2375677A
Application number: GB0206106A
Authority: GB
Inventors: Kevin Bracey; Peter Carr; Robert Sprowson; Andrew Hodgkinson
Original assignee: Pace Micro Technology PLC
Current assignee: Arris Global Ltd
Priority date: 2001-03-22
Filing date: 2002-03-15
Publication date: 2002-11-20
Also published as: GB0206106D0; GB0107198D0

Abstract

A method of providing a PIP on a display screen of, or connected to electrical apparatus, such as a broadcast data receiver or set top box. The method includes the steps of horizontally scaling the PIP using hardware 12 provided in the electrical apparatus, transferring the horizontally scaled PIP to memory 10 in the processor of the apparatus, the PIP being vertically scaled in the memory of the processor before being transferred to the graphics plane of the display screen. The method eliminates the need for external memory in the electrical apparatus.

Description

Picture in Picture Display This invention relates to a method of generating a Picture-inPicture display for a display screen connected to electrical apparatus.

It is known to be able to provide an inset picture/video display in a sub-window on a display screen containing video data and/or graphics and this inset picture/video display is termed Picture-in-Picture (PIP). PIP is used in television systems, computer systems, video conferencing and/or the like. Scaling of the picture/video display to be placed in the PIP window is a complex process, particularly if the video display contains a live broadcast image or images, as the image typically arrives a line at a time.

One possible method of performing scaling of the PIP to allow fitting of the video display in the PIP window is to use analogue circuitry. Scaling of the PIP requires synchronisation of the incoming video data but analogue systems are notoriously unstable and analogue circuitry is typically unable to perform this synchronisation. A further possible method is to digitise the incoming video data signal to stabilise the data and then store the stabilised digitised data in memory, such as a hard disk drive, in the apparatus. Once digitised and stored in memory, the video data can then be scaled. However, this method requires the use of a frame store and RAM controller and, as such, is an expensive method and thus undesirable. A yet further method requires placing the incoming PIP video data directly into the main memory (RAM) of the processor of the apparatus.

As the incoming images are not yet scaled for fitting to the PIP window, the processor software has to perform the scaling and is typically unable to cope with this, thereby significantly slowing the processor down.

It is therefore an aim of the present invention to provide a method for scaling incoming video data for PIP which overcomes the abovementioned problems.

According to a first aspect of the present invention there is provided a method of providing a PIP on a display screen of, or connected to electrical apparatus, said method including the steps of horizontally scaling the PIP using hardware provided in the electrical apparatus, transferring said horizontally scaled PIP to memory in the processor of the apparatus, said PIP being vertically scaled in the memory of the processor, the scaled PIP then being transferred to the graphics plane of the display screen.

Thus the present invention allows scaling of the PIP video data in the processor memory without the requirement of a separate discrete Random Access Memory (RAM), thereby reducing the cost of the process. As the data is partially scaled on being transferred to the processor memory, the operational speed of the processor is not slowed (or at least not to the same degree) as is currently the case with prior art methods.

Preferably software in the processor memory (RAM) of the apparatus vertically scales the PIP data.

Preferably the processor of the apparatus is provided with memory processing means in the form of direct memory access (DMA) and the DMA allows transfer of the horizontally scaled PIP to the processor memory.

Preferably the scaled PIP is stored in a reserved area (or PIP buffer) in the RAM of the processor.

Preferably the PIP includes video and/or graphics data.

In one embodiment the video and/or graphics data are received from a remote location, such as a broadcaster.

In an alternative embodiment the video and/or graphics data are already stored in memory of the electrical apparatus, (although not in the memory of the processor).

Preferably the incoming broadcast image is horizontally scaled by the apparatus hardware by a factor determined by Inter-I. C Communication (I2C) commands sent to the hardware from the processor.

Preferably the hardware is a pixel decoder which scales the horizontal lines of the incoming image.

As the PIP video data is already horizontally scaled when transferred to the processor RAM, this allows the software of the processor to transform the scaled video data, such as by clipping or blending the transformed video image (s), prior to transferring the video data from the RAM to the graphics plane.

Preferably the electrical apparatus is a broadcast data receiver or set top box forming part of a television system.

According to a second aspect of the present invention there is provided a method of adding a PIP for display on a display screen of a television system, said television system including a broadcast data receiver for receiving digital data from a remote location, said broadcast data receiver including hardware and software for the processing of the received data, a processor and memory and said method includes the steps of the receiver hardware horizontally scaling PIP image data, transferring said

horizontally scaled PIP to memory in the processor of the receiver, vertically scaling the PIP in the memory of the processor and then transferring the scaled PIP to the graphics plane of the display screen.

According to a further aspect of the present invention there is provided a method of adding a PIP for display on a display screen of a television system, said television system including a broadcast data receiver for receiving video data from a remote location, said broadcast data receiver including hardware and software for the processing of the received data, a processor and memory and said method includes the steps of the receiver hardware horizontally scaling the PIP image data in real time when in a digital form, flagging active parts of the image line/lines which are required for transferring to the receiver memory, supplying timing signals with the data to allow Direct Memory Access of the data into the memory, the software of the processor accepting the image data, vertically scaling the data and storing said data in a reserved area in the memory, monitoring the field identification of the video display data and then joining the PIP image with the main display screen image in the graphics plane of the display screen when required.

The present invention provides a method of PIP which eliminates the need for external memory (RAM) storage in the electrical apparatus, thereby reducing the cost of the PIP process. In addition, the present invention overcomes the need for the processor of the apparatus to horizontally scale the incoming data, thereby preventing excess processor capacity being used. Thus the present invention provides a method of PIP which uses a combination of hardware and software, which is inexpensive and which reduces the workload of the processor in the apparatus.

A further advantage of the present invention is that the input/output (i/o) pin count of the programmable logic in the processor is reduced due to not having to interface between 2 areas of RAM and the two picture sources (i. e. , the picture on the display screen and the inset picture in the PIP window).

An embodiment of the present invention will now be described with reference to the accompanying figures wherein: Figure 1 is a schematic overview of the present invention; and Figures 2A-2C is a schematic representation of the software involved in the present invention.

The first step requires data to be accepted by DMA from the hardware and storing it in a reserved place in the processor memory (PIP buffer) as shown in Figure 2A. The second step is for the software to monitor the field id of the incoming image.

The field id is a signal generated by the hardware so that the processor knows which field is the current image field as shown in Figure 2B. Broadcast images are sent in fields of alternate lines to reduce the flicker caused by the persistence of phosphor on the television picture tube. The third step is to join the PIP with the processor's image for display on the screen during the time when nothing is being displayed on the screen (i. e. , during vertical flyback).

The described embodiment of the present invention combines a hardware/software approach to provide PIP on a display screen containing video data and/or graphics data, the display screen connected to a broadcast data receiver of a television system.

Referring to the figures, processor hardware in the broadcast data receiver is provided in the form of a pixel decoder/PIP

processor 2, which is able to scale an incoming PIP video image to a factor determined by I2C commands. The pixel decoder 2 scales the horizontal lines of the incoming image 4 within an internal line store.

Active parts of the scaled output lines (video active or VACT) 6 of the image are flagged by the processor hardware as requiring transferring to the processor's memory (RAM). Vertical scaling is performed by discarding lines of data and such lines are termed non-active parts and are not transferred to the processor's memory. This produces a signal which is passed to the control logic 8 for making a DMA request to the processor 10, via DMA control lines 9, that a DMA is required for the line that the pixel decoder 2 is about to output. Thus the request informs the processor that the active regions of the scaled PIP window are ready for transferring. The active pixels 11 forming the image are then transferred to the processor's memory. In addition, the field id 12 is passed to the processor 10 so that the time of the start of a new field is known.

The image data 14 arriving in the processor 10 is stored in a reserved area termed the PIP buffer 16. Software 18 in the processor copies bitmap into an appropriate location or frame buffer 20 in the screen memory and applies any other software transformations required to the data. A video DMA 22 then passes the frame buffer to the video serialiser as according to conventional methods to serialise the PIP image.

The processor software 18 maintains a two-region buffer in the frame store 20, one region is the field which is currently arriving in the processor and the other region is the last completed field. This ensures that a field which has not yet finished arriving is not displayed in the PIP window.

The transfer of image data from the PIP buffer 16 to the graphics buffer takes place during the processors vertical flyback to eliminate flickering, which would otherwise be present, caused by trying to join together two incommensurate video sources. The vertical flyback period is when the electron beam which scans across the screen reaches the bottom right of the display screen and it has to be stopped and moved back to the top left of the screen. During this flyback period no image is being output, so any changes to the image should be made during this time to avoid screen flicker, which would otherwise occur if changes were made to the contents of the screen memory while the video serialiser is trying to display it.

The memory into which the PIP data is direct memory accessed into is shared with that of the processor, i. e. , there is no requirement for a dedicated PIP framestore RAM, instead it uses processor shared memory.

Referring to Figures 2A-2C, the steps necessary to be undertaken by the software of the processor are illustrated.

Direct Memory Access directly into the graphics buffer is not recommended since there is no opportunity to take"palette" into account or to optionally clip or post PIP process the field.

In addition, there are problems associated with hardware scrolling and there would be a requirement of having to run in a mode compatible with the hardware's data format. A further reason why direct memory access is not performed directly into the graphics buffer is that the processor's video timing must match the insert picture timing (i. e. , be in phase), but since the PIP image is coming from an external source it is difficult to phase lock the two images together if DMAing is performed directly, thereby resulting in beating and flickering of the resulting PIP image.

Data rates from data transferred by DMA can be calculated, for example, from 16bpp x 768 pixels x 288 lines x 50 fields per second x 1 (scaling~factor2) Thus, for a quarter screen area PIP of a full screen, this is 16bpp x 768 x 288 x 50 x 0. 25 = 5. 5Mbytes per second.

For full screen video (browser obscured) this is 16bpp x 768 x 288 x 50 x 1 = 22Mbytes per second.

Therefore, the smaller the PIP is, the less data is transferred. This is in contrast to scaling performed entirely in the processors software where a constant 22Mbytes per second would be transferred plus the overhead of the scaling algorithm.

Claims

Claims :- 1. A method of providing a PIP on a display screen of, or connected to electrical apparatus, said method including the steps of horizontally scaling the PIP using hardware provided in the electrical apparatus, transferring said horizontally scaled PIP to memory in the processor of the apparatus, said PIP being vertically scaled in the memory of the processor, the scaled PIP then being transferred to the graphics plane of the display screen.
2. A method according to claim 1 wherein the hardware of the electrical apparatus horizontally scaling said PIP is a pixel decoder.
3. A method according to claim 1 wherein the processor is provided with direct memory access (DMA) and the DMA allows transfer of the horizontal scaled PIP to the memory in the processor.
4. A method according to claim 3 wherein the scaled PIP is stored in a reserved area in the Random Access Memory (RAM) of the processor.
5. A method according to claim 4 wherein software of the processor transforms the scaled PIP data prior to transferring said data from the RAM of the processor to RAM of the graphics plane.
6. A method according to claim 5 wherein the transformations performed by the software include clipping and/or blending of said PIP data.

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7. A method according to claim 1 wherein the PIP includes video and/or graphics data.
8. A method according to claim 7 wherein the video and/or graphics data is already stored in memory of the electrical apparatus.
9. A method according to claim 7 wherein the video and/or graphics data is received from a broadcaster at a remote location.
10. A method according to claim 7 wherein the video and/or graphics data is horizontally scaled by the hardware of the electrical apparatus by a factor determined by I2C commands sent to the hardware from the processor.
11. A method according to claim 1 wherein the electrical apparatus is a broadcast data receiver.
12. A method of adding a PIP for display on a display screen of a television system, said television system including a broadcast data receiver for receiving digital data from a remote location, said broadcast data receiver including hardware and software for the processing of the received data, a processor and memory and said method includes the steps of the receiver hardware horizontally scaling PIP image data, transferring said horizontally scaled PIP to memory in the processor of the receiver, vertically scaling the PIP in the memory of the processor and then transferring the scaled PIP to the graphics plane of the display screen.
13. A method of adding a PIP for display on a display screen of a television system, said television system

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including a broadcast data receiver for receiving video data from a remote location, said broadcast data receiver including hardware and software for the processing of the received data, a processor and memory and said method includes the steps of the receiver hardware horizontally scaling the PIP image data in real time when in a digital form, flagging active parts of the image line/lines which are required for transferring to the receiver memory, supplying timing signals with the data to allow Direct Memory Access of the data into the memory, the software of the processor accepting the image data, vertically scaling the data and storing said data in a reserved area in the memory, monitoring the field identification of the video display data and then joining the PIP image with the main display screen image in the graphics plane of the display screen when required.