GB2370396A - Configuring programmable logic devices - Google Patents

Configuring programmable logic devices Download PDF

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Publication number
GB2370396A
GB2370396A GB0031058A GB0031058A GB2370396A GB 2370396 A GB2370396 A GB 2370396A GB 0031058 A GB0031058 A GB 0031058A GB 0031058 A GB0031058 A GB 0031058A GB 2370396 A GB2370396 A GB 2370396A
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GB
United Kingdom
Prior art keywords
memory
configuration
programmable logic
logic device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0031058A
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GB0031058D0 (en
Inventor
Mel Long
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UbiNetics Ltd
Original Assignee
UbiNetics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UbiNetics Ltd filed Critical UbiNetics Ltd
Priority to GB0031058A priority Critical patent/GB2370396A/en
Publication of GB0031058D0 publication Critical patent/GB0031058D0/en
Publication of GB2370396A publication Critical patent/GB2370396A/en
Application status is Withdrawn legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]

Abstract

Processor 14 reconfigures FPGA (or other programmble logic device) 12 via connector 18 using data from a removable configuration memory 16. Since memory 16 is removable, it can be substituted by a different memory containing different configuration data which is then instantly available to processor 14 for reconfiguring the FPGA 12.

Description

t P101659GB/JKH/MPG

CONFIGURING PROGRAMMABLE DEVICES

The invention relates to programmable logic devices, and to their configuration. Generally speaking, a programmable logic device (PLD) is a device comprising several processing elements which can be configured to perform a selected processing task. A field

programmable gate array (FPGA) is an example of a programmable logic device.

The processing elements and/or the interconnections between the processing elements of a PLD need to be configured to perform a selected function. Large scale PLDs tend to be based on volatile memory and therefore configuration data needs to be stored externally.

Typically, apparatus containing a PLD also comprises a non-voltatile memory from which configuration data can be loaded into the PLD. The configuration data can be extracted from the memory by the PLD itself or by a processor.

It is an object of the invention to enhance the process of configuring a PLD.

According to one.aspect, the invention provides apparatus comprising a programmable logic device and means for connecting removably to the apparatus a configuration memory for providing information for configuring the programmable logic device.

The invention provides the advantage that the configuration memory can be replaced easily with a memory of a different size. This facilitates the use of a very large configuration data set (corresponding to a highly complex configuration or a configuration for a relatively large PLD) or the storage of multiple sets of configuration data. Another advantage of the invention is that, prior to being connected to the apparatus, a configuration memory can be preprogrammed with a desired configuration data set with the result that the configuration data is immediately available upon connection of the configuration memory with the apparatus, i.e., the delay involved in loading the configuration data set into the configuration memory is avoided by the end-user of the PLD. For example, several interchangeable memories could be provided, each storing a different set of configuration data, each set of configuration data being effective to configure the programmable logic device for a different task.

Optionally, the configuration memory is non-volatile. Advantageously, the configuration memory can then be programmed with a set of configuration data, disconnected from the programming equipment, moved to the apparatus containing the programmable logic device, and then connected to the apparatus to make the configuration data available for reprogramming the PLD.

The invention also extends to the case where the apparatus comprises several PLDs, each configurable by data obtained via the connecting means from a removable storage device.

The invention also relates to the case where the apparatus comprises a memory removably connected to the connecting means for configuring the (or each) PLD.

In one embodiment, e, or each, PLD is a FPGA.

By way of example only, an embodiment of the invention will now be described, with reference to the accompanying figure which illustrates a processing system comprising a FPGA. The processing system 10 of Figure 1 comprises a FPGA 12 whose processing elements are configurable to allow the FPGA 12 to perform various processing tasks. Once configured, the FPGA 12 receives processing data from processor 14. The FPGA 12 operates on the processing data received from the data processor 14 and returns the resulting output data to processor 14.

The FPGA 12 is configured and reconfigured under the control of processor 14, which performs the configuration process in accordance win configuration data retrieved from a configuration memory 16. The configuration memory 16 is a non-volatile memory, meaning that it will hold data in a stable state whilst disconnected from uploading or downloading apparatus. The configuration memory 16 is connected to processor 14 via connector 18.

l Connector 18 is such that the configuration memory 16 is removably connectable thereto.

This means that the configuration memory 16 can be removed and replaced with a different configuration memory. This allows for the connection of configuration memories containing different sets of configuration data to the processor 14 in a manner such that their configuration data is immediately available for use in reconfiguring FPGA 12.

Furthermore, a configuration memory of a desired size can be connected to connector 18, which means that the site of the memory employed can be tailored to the amount of configuration data to be stored.

When the processor 14 is required to reconfigure the FPGA 12 to perform a different processing role, it reads the desired set of configuration data from configuration memory 16 via connector 18 and uses the set of configuration data in the reconfiguration of the FPGA, the reconfiguration being achieved in a known manner.

The configuration memory 16 can store configuration data in a compressed format with the advantage that the data can then be stored in a smaller memory area, enabling a reduction in the configuration memory size.

Claims (5)

1. Apparatus comprising a programmable logic device and means for connecting removably to the apparatus a configuration memory for providing information for configuring the programmable logic device.
2. Apparatus according to claim 1, wherein the programmable logic device is a field
programmable gate array.
3. Apparatus according to claim 1 or 2 wherein the configuration memory is non-volatile.
4. Apparatus according to any one of claims 1 to 3, further comprising a memory removably connected to the connecting means for configuring the programmably logic device.
5. A reconfigurable programmable logic device removably connectable to a configuration memory, substantially as hereinbefore described with reference to the accompanying Figure.
GB0031058A 2000-12-20 2000-12-20 Configuring programmable logic devices Withdrawn GB2370396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0031058A GB2370396A (en) 2000-12-20 2000-12-20 Configuring programmable logic devices

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0031058A GB2370396A (en) 2000-12-20 2000-12-20 Configuring programmable logic devices
AU2225502A AU2225502A (en) 2000-12-20 2001-12-18 Configuring programmable devices
PCT/GB2001/005603 WO2002051011A2 (en) 2000-12-20 2001-12-18 Circuit for configuring a programmable logic device

Publications (2)

Publication Number Publication Date
GB0031058D0 GB0031058D0 (en) 2001-01-31
GB2370396A true GB2370396A (en) 2002-06-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB0031058A Withdrawn GB2370396A (en) 2000-12-20 2000-12-20 Configuring programmable logic devices

Country Status (3)

Country Link
AU (1) AU2225502A (en)
GB (1) GB2370396A (en)
WO (1) WO2002051011A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2352548A (en) * 1999-07-26 2001-01-31 Sun Microsystems Inc Executing standard functions in a computer system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548228A (en) * 1994-09-28 1996-08-20 Altera Corporation Reconfigurable programmable logic device having static and non-volatile memory
US5768372A (en) * 1996-03-13 1998-06-16 Altera Corporation Method and apparatus for securing programming data of a programmable logic device
US5898317A (en) * 1996-12-23 1999-04-27 Motorola, Inc. Configurable monolithic semiconductor circuit and method for configuring
US6102963A (en) * 1997-12-29 2000-08-15 Vantis Corporation Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2352548A (en) * 1999-07-26 2001-01-31 Sun Microsystems Inc Executing standard functions in a computer system

Also Published As

Publication number Publication date
WO2002051011A3 (en) 2003-02-27
AU2225502A (en) 2002-07-01
WO2002051011A2 (en) 2002-06-27
GB0031058D0 (en) 2001-01-31

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)