GB2369941A

GB2369941A - A polar loop amplifier arrangement with variable gain in a feedback loop

Info

Publication number: GB2369941A
Application number: GB0030106A
Authority: GB
Inventors: Lee Robinson; Colin Davis; Kevin Cobley
Original assignee: Roke Manor Research Ltd
Current assignee: Roke Manor Research Ltd
Priority date: 2000-12-09
Filing date: 2000-12-09
Publication date: 2002-06-12
Also published as: WO2002047249A2; WO2002047249A3; GB0030106D0

Abstract

The present invention relates to radio frequency signal generation and amplification, and relates to a polar loop amplifier arrangement. The present invention seeks to overcome problems associated with known polar loop amplifiers such as poor dynamic range, which is known to result in spectral regrowth. The present invention provides a polar loop amplifier which includes separate phase and amplitude loops and which includes power control means within the amplifier loop. The amplifier may be used in producing TDMA bursts. Power ramping is disclosed.

Description

A POLAR LOOP AMPLIFIER ARRANGEMENT

FIELD OF INVENTION The present invention relates to radio frequency signal generation and amplification. In particular, the present invention relates to a polar loop amplifier arrangement.

BACKGROUND TO THE INVENTION In the field of mobile communications, amplifiers have been developed to operate at high gain and within narrow frequency bands.

Third generation (3G) mobile telecommunication systems impose higher demands on equipment. Accordingly, not only do telecommunications equipment manufacturers have to continuously improve their equipment by making more efficient devices which reduce input power requirements, with consequential improvements in, inter alia, battery life, heat generation etc, but also provide equipment meeting more demanding operational specifications. The size and cost of devices is also a very important consideration.

Enhanced Data rates for GSM Evolution (EDGE) uses a non constant envelope modulation scheme (8PSK). The standard implementation of a non-constant envelope transmitter uses a linear amplifier transmit chain. Such implementations have several disadvantages when implemented in, for example, a mobile handset.

Such disadvantages arise, inter alia, because linear power amplifiers consume a much higher quiescent current than non linear equivalents, reducing the efficiency of the amplifier and this decreases the battery life of the handset. A standard linear transmitter cannot make use of a modulation up conversion loop. This means that the phase noise rejection properties of such a loop are lost and RF filtering must be provided. RF filters can be large and expensive and filter losses after the PA must also be compensated for by increasing the output power of the PA and thus using more battery power. GSM power amplifiers are widely available, are of low cost, and typically use proven processes and designs. The use

of these components can thus provide production and reliability advantages over alternative EDGE power amplifiers.

As EDGE is an enhancement of the GSM telecommunications standard, it has been believed to be a logical step to take a standard GSM up conversion loop as a base line for a possible EDGE transmitter. The GSM up conversion loop has phase noise advantages over other transmitter architectures, since modulator noise is suppressed by a loop filter as in a phase locked loop. As the up conversion loop suppresses noise, no RF filtering is required and consequently the architecture produces very compact low cost designs.

The main problem with the use of an up conversion loop for EDGE applications is that it is only capable of transmitting phase information and is not capable of transmitting amplitude information. This is due, in part, to the fixed output level from an output of a voltage controlled oscillator (VCO) as shown in figure 1. Thus, as it stands, the up conversion loop 10 is an excellent architecture for phase modulated signals, but is not suitable for a non-constant envelope EDGE signal. One technique has been to apply amplitude restoration; this is where the amplitude information is added to the phase modulated signal. If this technique is practical, the up conversion loop may be used to transmit an EDGE signal maintaining the previously stated benefits of the technique. Similar demands are placed on amplifiers required for standards such as IS 136 and other amplitude and phase modulated standards.

OBJECT OF THE INVENTION Known polar loop amplifiers have not been widely deployed in digital communications system because the dynamic range has not been sufficiently wide resulting in spectral re-growth. The present invention seeks to provide an improved polar loop amplifier architecture.

STATEMENT OF INVENTION

In accordance with the first aspect of the invention, there is provided a polar loop amplifier arrangement comprising: an input, a reference synchronous detector, a phase detector, an RF voltage controlled oscillator, a power amplifier, a feed-back loop and an output, wherein the feed-back loop comprises: a phase loop, an amplitude loop, the phase loop and the amplitude loop having a common loop section; wherein the reference synchronous detector is operable to resolve an input signal to provide demand phase and amplitude input signals to the respective phase and amplitude loops ; wherein the common loop section comprises a feedback coupler operable to couple signals output from the power amplifier, an amplifier, and a feed back synchronous detector; wherein the phase loop comprises the phase detector which is arranged to receive a feed-back phase signal from an output of the feed-back synchronous detector and the demand phase signal, the output of the phase detector being arranged to be input to the RF voltage controlled oscillator and amplified by the power amplifier; wherein the amplitude control loop comprises a comparator which is arranged to receive a feedback amplitude signal from the feed-back synchronous detector and the demand amplitude signal, which signal is amplified to compensate for the amplification provided by the feed-back amplifier, whereby to provide a control signal for the power amplifier.

Conveniently the comparator is operable to subtract a feedback amplitude signal from the feedback synchronous detector from the demand amplitude signal to form an error signal, which error signal is amplified to compensate for the gain of the feedback path. Preferably the error signal is filtered, for example by an integrating capacitor.

The common loop can include a mixer and a local oscillator whereby the feedback synchronous detector may operate at an intermediate frequency. Preferably there is provided a low pass filter operable to filter the output from the phase detector. Preferably there is provided a low pass filter operable to filter the output from the down convert mixer of the feedback synchronous detector. Preferably the

amplitude loop comprises a lineariser, which provides an input to the power amplifier. Preferably the reference and feedback synchronous detectors are provided with buffer amplifiers whereby to provide correct amplitude levels at the respective outputs from the synchronous detectors.

The reference and feedback synchronous detectors can be provided with phase shifters to provide the correct phase relationship at the synchronous detector mixer inputs. The amplifiers in the common loop and the feedback loop can be variable gain amplifiers whereby the output power and loop gain can be adjusted to give the required output signal.

The reference signal can be provided by a vector modulator, which signal may be amplified whereby to ensure that the reference synchronous detector is driven at an appropriate amplitude. The input and output synchronous detectors can each comprise a limiting amplifier and a mixer.

In accordance with a further aspect of the invention, there is provided a mobile communications handset having a polar loop amplifier arrangement made in accordance with the first aspect of the invention.

In accordance with a further aspect of the invention, there is provided a method of operating a polar loop amplifier arrangement comprising: an input, a reference synchronous detector, a phase detector, a voltage controlled oscillator, a power amplifier, a feed-back loop and an output, wherein the feed-back loop comprises: a phase loop, an amplitude loop, the feed-back loop and the amplitude loop having a common loop section; wherein the common loop section comprises a feed-back coupler and a feed-back synchronous detector; wherein the phase loop comprises the phase detector which is arranged to receive a feed-back phase signal from an output of the feedback synchronous detector and the demand phase signal ; wherein the amplitude control loop comprises a comparator which is arranged to receive a feed-back amplitude signal from the feedback synchronous detector and the demand amplitude signal, wherein the

reference synchronous detector is operable to resolve an input signal to provide demand phase and amplitude input signals to respective phase and amplitude loops ; wherein the common loop section feed-back coupler couples signals output from the power amplifier, which are fed to the amplifier, and the feed-back synchronous detector; wherein the phase loop phase detector receives a feed-back phase signal from an output of the feedback synchronous detector and the demand phase signal, and provides a signal to the RF voltage controlled oscillator which is amplified by the power amplifier ; wherein the amplitude control loop comparator receives a feed-back amplitude signal from the feed-back synchronous detector and the demand amplitude signal, to produce a comparative signal which is amplified to compensate for the amplification provided by the feed-back amplifier, whereby to provide a control signal to the power amplifier ; BRIEF DESCRIPTION OF THE FIGURES The invention may be understood more readily, and various other aspects and features of the invention may become apparent, from consideration of the following description and the accompanying drawing sheets, wherein: Figure 1 is a circuit diagram of a GSM up conversion loop transmitter; Figure 2 is a circuit diagram of a known polar loop amplifier ; Figure 3 is a circuit diagram of a first embodiment of the invention; Figure 4 shows a graph comparing output spectrum at a spot frequency relative to the EDGE specification; Figure 5 shows an EVM constellation corresponding to the graph of Figure 4; Figure 6 shows gain and phase response for a first power amplifier ; Figure 7 shows a second graph comparing output spectrum at a spot frequency relative to the EDGE specification; Figure 8 shows an EVM constellation corresponding to the graph of Figure 7; Figure 9 shows a polar loop spectrum with 1S136 modulation;

Figure 10 shows an EVM constellation corresponding to the graph of figure 9 ; and Tables 1,2 & 3 show EVM data corresponding to graphs 5,7 & 9.

DETAILED DESCRIPTION OF INVENTION There will now be described, by way of example, the best mode contemplated by the inventors for carrying out the invention. In the following description, numerous specific details are set out in order to provide a complete understanding of the present invention. It will be apparent, however, to those skilled in the art that the present invention may be put into practice with variations of the specific.

With reference to Figure 2 there is shown a polar loop architecture which comprises a reference signal, which is provided by a vector modulator, a phase loop and an amplitude loop. The phase can be considered as being similar to a standard GSM up-conversion loop ; the only exception being the limiter, which has a negligible effect and the phase feed-back are taken from the output of the power amplifier. The amplitude loop ensures that the power amplifier output amplitude accurately represents that of the reference signal. The phase comparater operates in a similar fashion in respect of phase. Two control loops exist in a polar loop, one for phase and the other for amplitude. The function of the loops is to modulate the signal emitted from a voltage controlled oscillator such that a higher frequency representation of the reference signal is transmitted at the output of the polar loop.

The vector modulated input signal (in Cartesian format) is split and fed into a limiting amplifier 210 and the RF input of a mixer 212. The limiter output is fed into the local oscillator input of the mixer 212. When the mixer mixes the input signal with a constant amplitude version of itself, a DC level is output on the mixer IF port. The voltage of this DC signal is proportional to the amplitude of the RF input, in this case the vector modulator output. Therefore, the limiter and the mixer provide a form of power detector for the polar loop amplifier arrangement. This arrangement is known as a synchronous detector.

The output of the limiter contains all the phase information of the input signal, however, the amplitude information is stripped off. In this way, the synchronous detector acts as a polar resolver, resolving amplitude and phase information. The phase and amplitude outputs of the input detector may be referred to as the reference amplitude and reference phase signals.

The amplitude reference signal is used to control the automatic power control (APC) of the power amplifier 214 such that the amplitude of the output of the modulator is a replica of the reference signal. This is accomplished by using a feedback signal 216, which is sampled from the output 218 of the power amplifier 214. This feed-back signal is down converted by a down convert mixer 220, which converts the output signal 222 to an intermediate frequency (IF) of the vector modulated signal. The output of the down converter mixer is then fed into a second synchronous detector, known as the feed-back detector 225. The amplitude output 226 of the feedback detector is then input to an error amplifier along with the reference amplitude signal 224. The error amplifier supplies the correct voltage to the power amplifier's APC pin to ensure that the amplitude of the polar loop output tracks the amplitude of the reference signal.

The reference phase signal 228 is input into a phase detector 230.

The phase loop ensures that the phase of the polar loop output accurately represents the phase of the reference signal. This is achieved by sampling the output of the power amplifier and down converting the signal to the IF frequency. The signal is then fed into the feedback detector and the phase output 232 is fed into the phase detector 230 along with the reference phase signal. The phase detector has a DC output (when filtered by filter 234), which controls the frequency of the voltage controlled oscillator such that the phases of the reference and feedback signals are the same.

Referring now to Figure 3, there is shown an amplifier circuit constructed in accordance with the invention. Two analogue I and Q base-band input signals are input to a vector modulator 310 at inputs 312

and 314 respectively. The vector modulator includes a splitter 311, a phase shifter 313 and a first local oscillator 315. The outputs of the mixers are summed by summer 316. The summed signal is fed to a mixer/limiter pair 318 which resolves the amplitude and phase components of the vector modulated signal. The phase component is fed to a phase detector 320, the output of which is filtered by a low pass filter 322. This filter provides a control voltage to a voltage controlled oscillator 324. The constant amplitude output of the voltage controlled oscillator is amplified by a power amplifier 326 to provide an output signal connected to a load, such as antenna 328.

A feedback signal is obtained from a coupler 322 positioned between the power amplifier and the load 328. The feedback signal is down-converted in frequency via a down-conversion mixer 332 and a second local oscillator 334. A feedback attenuater 354 may be employed to provide a feedback signal of the correct amplitude to a mixer. A variable gain amplifier 336 provides variable gain with a negligible effect on the phase component of the signal. A first output of this signal is limited by limiter 338 and fed back to phase detector 320 to provide a phase control loop. A mixer 340 in conjunction with limiter 338 function as a synchronous power detector which has a very wide linear dynamic range. The DC output is fed to a first input 342 of a differential amplifier 346 which also has an input 344 which receives signals from the first mixer/limiter pair 318. The differential amplifier 346 functions as an error amplifier and can compare the power amplifier output power with the amplitude component resolved from the reference signal. The output power of the differential amplifier 346 provides a DC signal which provides an automatic power control input to the power amplifier 326. A capacitor is provided across the differential amplifier to provide an integrating function. Accordingly the power amplifier can modulate the constant amplitude signal output from the output or RF voltage control oscillator and restore the amplitude component of the required signal.

A variable gain amplifier 348 is also provided in the feedback loop which provides several advantages:

The transmitter can operate over a wide dynamic range whereby accurate power control can be provided for a wide output power range.

The use of a variable gain amplifier in the feedback loop allows the transmitter output to be bursted, which facilitates implementation in TDMA transceivers, for example. The variable gain amplifier also permits accurate power ramping control which allow the transmitter to meet the power-time mask and switching spectrum specifications. The variable gain amplifier does not contribute to any amplitude modulation of the output signal; it merely allows accurate power control and ensures that the detector's dynamic range is not exceeded. Lineariser 370 linearises the signal from the comparator 346 to minimise the variation in loop gain due to PA control response.

Phase shifters 350,352 ensure that the relative phase of the signals at the local oscillator and radio frequency ports of the detector's mixer are correct. The optional buffers 360,362 ensure that the detector's mixer local oscillator port is driven at the correct level. The phase shifters can be omitted if the length of the transmission line is such that the phase is aligned correctly at the mixer local oscillator and RF port.

The buffer can be omitted if the output level from the limiter is sufficient to drive the local oscillator port of the detector's mixer.

A buffer 356 is also shown at the output of the vector modulator.

This is necessary if the output of the vector modulator is too low to drive the polar loop. The polar loop operates in much the same way as the prior art loop. However, the amplitude modulation is now carried out by the power amplifier, thereby increasing efficiency. The base band variable gain amplifier 348 compensates for the loop gain variation introduced by the intermediate frequency variable gain amplifier 336. For example, the variable gain amplifier 336 could be placed before mixer 332 (i. e. at an intermediate frequency or at radio frequency).

The invention has been applied to several commercially available amplifiers and the response of one particular amplifier, the RF Micro Devices, model RF2173 is discussed with reference to Figures 4,5, table 1 and Figure 6.

Figure 4 shows an EDGE spectrum provided by RF2173 amplifier.

The skirts of the spectrum are well within with the EDGE specification.

Figure 5 shows an error vector magnitude (EVM) graph with the characteristics tabulated in table 1. RMS and peak EVM figures are within the EDGE requirements. Figure 6 shows the AM-PM conversion characteristics of the RF2173 amplifier. The AM-PM is corrected by the polar loop.

The vector modulator used in the design comprises part of a Temic U2894 which provides good overall modulator performance and which was included for its low noise (-115dB @ 400 kHz effect from carrier), 135m Vrms output, and carrier and side-band suppression of-35 and-40 dBc, respectively. Figures 7,8 and Table 2 show vector modulator output with harmonic filter and buffer, vector modulator constellation and EVM data for the Temic U2894, respectively.

The base band variable gain amplifier can be added to the system to assist loop stability over the full output power range. The characteristics required are as follows : A device having a gain control range the same as or greater than the intermediate frequency variable gain amplifier ; a band-width comparable with the feedback variable gain amplifier ; be of low noise and have well defined gain control characteristics. The Analog Devices AD603 Amplifier was found to be capable of meeting these requirements.

In order to provide control of the two variable gain amplifiers in an integrated solution, dynamic control can be carried out in the ramping phases at the beginning and end of each burst. The amount of control needed in each burst will vary depending on the transmit power. If the power output is 0 dBm, no adjustment of the variable gain amplifiers will be necessary as they will already be set for minimum output power.

However, if, for example, the required output power is 27 dBm, the variable gain amplifiers will have to ramp from 0 dBm to 27 dBm during the ramp up period of the burst and from 27 to 0 dBm at the end of the burst.

The Analogue Devices AD603 amplifier has a log linear automatic gain control characteristic with a slope of 22. 1 dBN. The characteristic is very accurate and linear, since one of its applications is as an amplitude modulator. The NEC UPC 3211 intermediate frequency variable gain amplifier has also proven to have appropriate gain control characteristics operable with the above Analogue Devices device. A circuit is required to ensure that the effective cascaded gain of the two amplifiers is constant for all working values of control voltage.

Figures 9 and 10 show a polar loop spectrum, and constellation diagram for a polar loop with 1S136 modulation. The EVM data is particularly good, as shown in the accompanying table.

A variation of the polar loop circuit can be envisaged where the reference synchronous detection is dispensed with in the event that the temperature compensation issues do not arise.

Claims

1. A polar loop amplifier arrangement comprising : an input (301), a reference synchronous detector (318), a phase detector (320), an RF voltage controlled oscillator (324); a power amplifier (326); a feed-back loop and an output (328); wherein the feedback loop comprises: a phase loop and amplitude loop, the feedback loop and the amplitude loop having a common loop section: wherein the reference synchronous detector is operable to resolve an input signal to provide demand phase and amplitude input signals to respective phase and amplitude loops ; wherein the common loop section comprises a feed-back coupler (327) operable to couple signals output from the power amplifier (326), an amplifier (336), and a feed-back synchronous detector; wherein the phase loop comprises the phase detector (320) which is arranged to receive a feed-back phase signal from an output of the feedback synchronous detector and the demand phase signal, the output of the phase detector being arranged to be input to the RF voltage controlled oscillator and amplified by the power amplifier; wherein the amplitude loop comprises a comparator (346) which is arranged to receive a feed-back amplitude signal from the feed-back synchronous detector and the demand amplitude signal, which signal is amplified to compensate for the amplification provided by the feed-back amplifier, whereby to provide a control signal to the power amplifier.

2. An amplifier arrangement according to claim 1 wherein the comparator is operable to subtract a feed-back amplitude signal from the feed-back synchronous detector from the demand signal to form an error signal, which error signal is amplified to compensate for the gain of the feed-back path.

3. An amplifier according to claim 2 wherein the error signal is filtered.

4. An amplifier arrangement according anyone of claims 1-3 wherein the common loop includes a mixer (332) and a local oscillator (334)

whereby the feedback synchronous detector may operate at an intermediate frequency.

5. An amplifier arrangement according to any one of claims 1 to 4, wherein, there is provided a low pass filter (322) operable to filter the output from the phase detector (320).

6. An amplifier arrangement according to any one of claims 1 to 5, wherein the amplitude loop comprises a linerariser, which provides an input to the power amplifier.

7. An amplifier arrangement according to any one of claims 1 to 6, wherein the reference and feed-back synchronous detectors are provided with buffer amplifiers (360,362) whereby to provide correct amplitude levels at the respective outputs from the synchronous detectors.

8. An amplifier arrangement according to any one of claims 1 to 7, wherein the reference and feed-back synchronous detectors are provided with phase shifters (350,352) whereby to provide correct phase rotations at the synchronous detector mixers.

9. An amplifier arrangement according to any one of claims 1 to 8, wherein the amplifiers in the common loop and the feedback loop are variable gain amplifiers whereby it is ensured that the amplitude input to the feed-back synchronous detector and the power amplifier control are at the appropriate amplitude levels.

10. An amplifier arrangement according to any one of claims 1 to 9, wherein the reference signal is received from a vector modulator.

11. An amplifier arrangement according to claim 10, wherein the reference signal is received from the vector modulator is amplified whereby to ensure that the reference synchronous detector is driven at an appropriate amplitude.

12. An amplifier arrangement according to any one of claims 1 to 11, wherein the input synchronous detector comprises a limiting amplifier (310) and a mixer (312).

13. An amplifier arrangement according to any one of claims 1 to 11, wherein the output synchronous detector comprises a limiting amplifier (358) and a mixer (340).

14. A mobile communications handset having a polar loop amplifier arrangement made in accordance with any one of claims 1 to 11.