GB2369542A - Generation of graphics in computer systems - Google Patents

Generation of graphics in computer systems Download PDF

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Publication number
GB2369542A
GB2369542A GB0028191A GB0028191A GB2369542A GB 2369542 A GB2369542 A GB 2369542A GB 0028191 A GB0028191 A GB 0028191A GB 0028191 A GB0028191 A GB 0028191A GB 2369542 A GB2369542 A GB 2369542A
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sep
address
memory
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GB0028191D0 (en )
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David Neil Pether
Stephen John Gibbon
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LSI Corp
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LSI Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/20Function-generator circuits, e.g. circle generators line or curve smoothing circuits
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/125Frame memory handling using unified memory architecture [UMA]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/024Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour registers, e.g. to control background, foreground, surface filling
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363Graphics controllers

Abstract

An apparatus for generating graphics is connectable in a computer system between a system processor and a system memory by way of a data bus. The apparatus comprises two registers for the storage of X and Y coordinates respectively of a single pixel. These coordinates are applied to an address conversion calculation unit for calculating a linear memory address corresponding to the pixel coordinates and the data representative of the pixel is stored in the system memory at the calculated address. The two registers are memory mapped to appear at two or more locations in memory such that operation of the apparatus is dependent on the memory location used by each register. The apparatus carries out many of the repetitive operations required in the generation of graphics.

Description

<img class="EMIRef" id="024185062-00010001" />

<tb>

Title <SEP> : <SEP> Generation <SEP> of <SEP> Graphics <SEP> in <SEP> Computer <SEP> Systems <tb> Background <SEP> of <SEP> the <SEP> Invention <tb> 1 Field of the Invention The present invention relates to the generation of graphics in computer systems and particularly, but not exclusively, to a method and apparatus for generating graphics which reduces the burden on the system processor of carrying out the repetitive operations needed for graphics generation.

2 Description of the Prior Art In order to produce faster graphics at higher resolution on a display screen it is desirable to obtain the maximum performance from any microprocessor responsible for generating <img class="EMIRef" id="024185062-00010002" />

<tb> graphics. <SEP> Known <SEP> computer <SEP> systems <SEP> for <SEP> generating <SEP> graphics <SEP> often <SEP> use <SEP> specialised <SEP> processors <tb> 1- <SEP> c <tb> <RTI>(CPUs)</RTI> which incorporate features designed to speed up certain common drawing algorithms.

The generation of graphics in such computer systems usually involves the calculation of the display coordinates of every point in a given shape and the conversion of these coordinates into an address in the system memory where the data for each point is to be stored. This is normally carried out by the system CPU or, alternatively, a dedicated graphics CPU.

The display on the display screen is conventionally divided into a large number of elements known as pixels which are arranged in an array on the display. The location of any given pixel in the array is defined relative to the top left corner by X, Y coordinates. For example, referring to Figure 1, if the pixel at the top left comer of the display has coordinates (0, 0) then a pixel 2 occupying a position on the display of 4 pixels from the left hand column and 5 pixels down from the top row has coordinates (3,4).

The brightness and colour information for each pixel is stored at a memory address in the <img class="EMIRef" id="024185062-00020001" />

<tb> system <SEP> memory <SEP> for <SEP> access <SEP> by <SEP> a <SEP> system <SEP> display <SEP> processor <SEP> or <SEP> adaptor <SEP> which <SEP> converts <SEP> the <SEP> pixel <tb> information <SEP> into <SEP> a <SEP> visible <SEP> point <SEP> on <SEP> the <SEP> display. <SEP> The <SEP> memory <SEP> address <SEP> itself <SEP> represents <SEP> the <SEP> pixel <tb> coordinates and is a single number generated by the CPU. Generation of the memory address is achieved by a calculation which is performed by the CPU on the X, Y values of the pixel coordinates. A common algorithm for calculating the memory address is.

Address = Base + X + Y * Pitch where: Base = the first address in the memory which is allocated to the storage of pixel data; X and Y = the values of the pixel coordinates as described above; and Pitch = the number of pixels horizontally across the display.

It can be seen that the Base value is the address location in the system memory corresponding to the pixel coordinate (0, 0) of Figure <RTI>I</RTI> and the Pitch value represents the number of memory addresses required for a single row of pixels.

While the above calculation is a relatively simple one, it is required to be computed for every pixel plotted. Since a display may have up to and above one million pixels, the need for the CPU to perform the calculation for all of the pixels in a single display frame greatly reduces the performance of the CPU. This may be disadvantageous since the CPU may be required to perform other functions, in addition to the generating of graphics, which further reduce the operational speed and performance of the CPU. Moreover, the provision within a computer system of a CPU dedicated solely to the generation of graphics is not necessarily a solution to the problem since it may be undesirable to have different types of processor within a single system design. <img class="EMIRef" id="024185062-00030001" />

<tb>

Object <SEP> of <SEP> the <SEP> Invention <tb> An <SEP> object <SEP> of <SEP> the <SEP> present <SEP> invention <SEP> is <SEP> to <SEP> provide <SEP> an <SEP> improved <SEP> method <SEP> and <SEP> apparatus <SEP> for <tb> drawing <SEP> graphics <SEP> in <SEP> order <SEP> to <SEP> address <SEP> the <SEP> problem <SEP> of <SEP> the <SEP> requirement <SEP> for <SEP> faster <SEP> drawing <SEP> of <tb> graphics <SEP> and <SEP> at <SEP> a <SEP> higher <SEP> resolution. <tb>

I <tb> Summary of the Invention Accordingly, the present invention provides an apparatus for generating a region of graphics on a display which comprises a register means for storing the coordinates on the display of a pixel to be drawn; calculation means for receiving the coordinates from the register means and calculating the address of a location in a memory for storage of data corresponding to the pixel in dependance on the coordinates; and control means for controlling the register means and the calculation means to cause the data to be written to and stored in the memory at the calculated address.

The present invention also provides a method of generating a region of graphics on a display, the method comprising: receiving X and Y coordinates of a pixel to be drawn in the region; storing the coordinates ; calculating the address of a location in a memory for storage of data corresponding to the pixel in dependance on the coordinates; and causing the data to be written to and stored in the memory at the calculated address.

The step of storing the coordinates preferably comprises storing X and Y coordinates of the pixel in first and second registers.

The calculation means conveniently calculates the address using the equation: Address = Base + A + B* Pitch where Base and Pitch are predetermined constants; <img class="EMIRef" id="024185062-00040001" />

<tb> A <SEP> is <SEP> one <SEP> of <SEP> the <SEP> X <SEP> and <SEP> Y <SEP> coordinates, <SEP> and <tb> B is the other of the X and Y coordinates In a preferred form of the invention the register means comprises first and second registers for storing X and Y coordinates respectively of the pixel. The first registeris memory mapped to first and second locations in the memory and the second register is memory mapped to third and fourth locations in the memory. The first to fourth memory address locations are monitored and a location signal is applied to the write control means representative of the <img class="EMIRef" id="024185062-00040002" />

<tb> address <SEP> location <SEP> being <SEP> written <SEP> to. <tb>

I <tb> The calculating means calculates the memory address for a pixel coordinate in response to one of the following : an X coordinate being sent to the X register at a preselected one of the first and second memory addresses; or a Y coordinate being sent to the Y register at a preselected one of the third and fourth memory addresses.

In a further preferred embodiment, a style table is provided for storing data corresponding to a predetermined pattern or style for each the pixel to be drawn. A style counter indexes the data in the style table means and generates a style data signal corresponding to the indexed data. The first register is memory mapped to first to fourth locations in the memory and the second register is memory mapped to fifth to eighth locations in the memory. The first to eighth memory address locations are monitored and a location signal is applied to the write control means representative of the address location being written to and the style counter means is indexed in response to the address location being written to. The calculating means calculates the memory address for a pixel coordinate in response to one of the following : an X coordinate being sent to the X register at the second or fourth memory addresses; or a Y coordinate being sent to the Y register at the sixth or eighth memory addresses.

The style counter is advanced in response to one of the following: an X coordinate being sent to the X register at the third or fourth memory addresses; or a Y coordinate being sent to the <img class="EMIRef" id="024185062-00040003" />

<tb> Y <SEP> register <SEP> at <SEP> the <SEP> seventh <SEP> or <SEP> eighth <SEP> memory <SEP> addresses. <tb>

9 <tb> <img class="EMIRef" id="024185062-00050001" />

<tb> Description <SEP> of <SEP> the <SEP> Drawings <tb> The <SEP> present <SEP> invention <SEP> is <SEP> described <SEP> hereinafter, <SEP> by <SEP> way <SEP> of <SEP> example <SEP> only, <SEP> with <SEP> reference <SEP> to <SEP> the <tb> accompanying drawings, in which: Figure 1 is a diagram representing a region of a display on a screen showing an array of pixels ; Figure 2 is a block diagram of part of a computer system incorporating a preferred form of apparatus according to the invention; Figure 3 is a block diagram of a part of the apparatus shown in Figure 2 in greater detail ; Figure 4 is a block diagram of a first modification to the apparatus of Figure 3 ; and Figure 5 is a block diagram of a second modification to the apparatus of <RTI>Figure 3.</RTI>

Detailed Description of the Preferred Embodiments of the Invention Figure 2 shows part of a computer system 10 incorporating a Pixel pipeline 20 and comprising a system or graphics CPU 12 which is connected to a system memory 14 by a system data bus 16. The Pixel pipeline, designated generally at 20, is connected to the system bus 16 and is therefore able to communicate with the CPU 12 and the system memory 14.

The Pixel pipeline 20 is shown in more detail in Figure 3. It is connected to the system bus 16 by its own dedicated input and output data buses 22, 32 and has first and second X and Y data registers 24,26 which are each connected to the input data bus 22. The data registers 24,26 are memory-mapped such that they appear to the CPU 12 as memory locations whose contents can be written to and read from using <RTI>normal"store"and"fetch"operations.</RTI> The data register 24 (X-register) is used for the temporary storage of the X value for a pixel coordinate while the data register 26 (Y-register) is used for the temporary storage of the Y value of the pixel coordinate, as described below. <img class="EMIRef" id="024185062-00060001" />

<tb> Each <SEP> data <SEP> register <SEP> 24, <SEP> 26 <SEP> has <SEP> an <SEP> output <SEP> which <SEP> is <SEP> connected <SEP> to <SEP> a <SEP> data <SEP> buffer <SEP> 28. <SEP> The <SEP> data <tb> buffer <SEP> 28 <SEP> has <SEP> two <SEP> outputs <SEP> corresponding <SEP> to <SEP> the <SEP> outputs <SEP> from <SEP> the <SEP> data <SEP> registers <SEP> 24, <SEP> 26 <SEP> which <tb> are input to an Address Conversion Calculation Block (ACCB) 30. This converts the X and Y values of the pixel coordinates into a number representing an address in memory at which data for the pixel is to be stored. The ACCB 30 has an output connected to the output data bus <RTI>32.</RTI>

The Pixel pipeline 20 also includes a Clip Unit 34 connected to the output of the data registers 24,26, a Write Control Unit 36 connected to the data registers 24,26, the input buffer 28, the ACCB <RTI>30,</RTI> the Clip Unit 34 and the output data bus 32, and an address decoder 35 The purpose of these is described below Operation of the Pixel pipeline of Figure 3 will now be described.

When the CPU 12 calculates the coordinates of a first pixel of a shape such as a rectangle or a circle is to be drawn on a display screen the X and Y values for the pixel are sent sequentially to the Pixel pipeline 20 where the X value is input to the X-register 24 and the Y value is input to the Y-register 26.

The data registers 24,26 apply their respective X and Y coordinate values to the Clip Unit 34 which checks each value to ensure that the pixel to which they correspond lies within a predetermined clipping window. The clip unit is a set of comparators which compare the coordinate data with the clipping window limits stored in a window limits register 38. The clipping window is defined by the CPU 12 and the limits of the window normally corresponding to the limits of the display.. If the pixel location falls outside the clipping window then the pixel is discarded. If the pixel location falls within the clipping window then the address calculation proceeds.

Such clipping is important in situations where only a small part of a large shape is to be visible on the display so that there is no point in plotting the hidden part of the large shape.

Conventionally, it is extremely time consuming for the CPU 12 to test every pixel against the <img class="EMIRef" id="024185062-00070001" />

<tb> clipping <SEP> limits <SEP> and <SEP> so <SEP> the <SEP> application <SEP> of <SEP> this <SEP> task <SEP> to <SEP> the <SEP> Pixel <SEP> pipeline <SEP> 20 <SEP> significantly <SEP> reduces <tb> the burden on the CPU 12.

If the pixel coordinate lies outside the clipping window, the write control unit 36 does not continue with the processing and the data in the data registers 24,26 is ignored. In this particular example, the write control unit 36 does not allow the buffer 28 to pass the coordinate data to the ACCB 30. The data registers 24,26 then receive a further set of coordinates from the CPU 12. If, however, the pixel coordinate lies within the clipping window, the write control unit continues with the processing and loads data from the data registers 24,26 into the data buffer 28.

The presence of the data buffer is optional and will depend upon the relative speed of operation of the CPU 12 and the memory 14 in the computer system 10. In general, algorithms for plotting common graphics shapes, e. g. lines and circles, allow the CPU 12 to calculate a number <RTI>of X,</RTI> Y coordinates at a very high speed but this usually occurs in the form of short bursts of data having a much lower average rate. For example, during the calculation of a circle, once the CPU 12 has calculated a point on the perimeter on the circle using, say, a trigonometric calculation, it is quickly able to calculate the coordinates of a number of other points using lines of symmetry. Thus, the coordinates of these points will be generated and output from the CPU 12 at a high rate. However, the CPU 12 then takes time to calculate the next point on the perimeter on the circle using trigonometry.

Consequently, the CPU 12 outputs the pixel coordinates in the form of short bursts of data having relatively long intervening periods. The data buffer 28 acts to balance or average the input and output data rates to ensure that data is not lost.

The X and Y coordinate values for each pixel are output by the buffer 28 and applied to the ACCB <RTI>30</RTI> which converts the pixel coordinates into a single number representative of an <img class="EMIRef" id="024185062-00070002" />

<tb> address <SEP> in <SEP> the <SEP> system <SEP> memory <SEP> 14 <SEP> using <SEP> the <SEP> calculation <SEP> described <SEP> above <SEP> : <tb> 0 <tb> Address <SEP> = <SEP> Base <SEP> + <SEP> X <SEP> + <SEP> Y <SEP> * <SEP> Pitch <tb> <img class="EMIRef" id="024185062-00080001" />

<tb> The <SEP> Base <SEP> and <SEP> Pitch <SEP> values <SEP> in <SEP> the <SEP> calculation <SEP> are <SEP> defined <SEP> by <SEP> the <SEP> CPU <SEP> 12 <SEP> and <SEP> are <SEP> held <SEP> in <SEP> Base <tb> and Pitch registers 40,42 respectively from which the values are read by the ACCB 30.

The calculated memory address is then output from the ACCB 30 to the output data bus <RTI>32</RTI> which also receives a data value for the pixel, representative of the pixel colour, from a pixel colour register 44. This data value is defined by the CPU 12. The pixel information, comprising the memory address and the data value is then applied to and stored in the system memory 14 via the output data bus 32 and the system bus 16 under the control of the write control unit 36. Thus, the data stored at the selected memory address is a value representing the colour for the pixel to be drawn and the address itself is representative of the pixel location on the display.

It can be seen, therefore, that the Pixel pipeline 20 is able to perform a number of simple but repetitive calculations which would normally be <RTI>performed</RTI> by the system CPU 12. This reduces the burden on the CPU 12 to perform such tasks and thus increases CPU performance and efficiency.

An improvement to the above-described operation of the Pixel pipeline 20 is achieved by the use of double memory-mapping of each of the data registers 24,26. The registers 24,26 are memory-mapped and each is arranged to appear to the CPU 12 as two separate locations in memory each having a unique memory address. Thus the CPU 12 sees two possible Xregisters at memory addresses <RTI>N and N+l andtwoY-registers</RTI> at memory addresses N+2 and N+3. These memory addresses need not be consecutive but are chosen so for convenience. <img class="EMIRef" id="024185062-00080002" />

<tb>

In <SEP> this <SEP> example, <SEP> memory <SEP> addresses <SEP> N <SEP> to <SEP> N+3 <SEP> will <SEP> be <SEP> assumed <SEP> to <SEP> be <SEP> 2000 <SEP> to <SEP> 2003 <SEP> with <tb> addresses <SEP> 2000 <SEP> and <SEP> 2001 <SEP> corresponding <SEP> to <SEP> the <SEP> X-register <SEP> 24 <SEP> and <SEP> addresses <SEP> 2002 <SEP> and <SEP> 2003 <tb> ZD <tb> representing the Y-register 26.

It is often the case that a sequence of pixel coordinates may be constant in a particular direction. For example, in the case of a horizontal line, the Y coordinate value does not change along the length of the line. In order to remove the necessity to assemble an X, Y <img class="EMIRef" id="024185062-00090001" />

<tb> coordinate <SEP> pair <SEP> for <SEP> each <SEP> pixel, <SEP> it <SEP> is <SEP> possible <SEP> merely <SEP> to <SEP> update <SEP> the <SEP> X <SEP> coordinate <SEP> in <SEP> the <SEP> Xregister <SEP> 24 <SEP> and <SEP> perform <SEP> the <SEP> address <SEP> calculation <SEP> on <SEP> the <SEP> new <SEP> X <SEP> coordinate <SEP> and <SEP> the <SEP> old <SEP> Y <tb> coordinate. This is achieved by making the action taken by the Pixel pipeline dependent upon the address used to store the pixel coordinate in the respective register. The address decoder 35 monitors each of the four address locations to see which is written to and applies an address location signal to the write control unit. In response to this the ACCB 30 performs its address calculation in dependence on the address of the X or Y register being updated.

Using the example described above, where the X-register 24 has memory addresses of 2000 and 2001 and the Y-register 26 has addresses of 2002 and 2003, the operation performed when coordinates are written to each address may be as follows: If an X coordinate is sent to the X register memory address 2000 then the X-register is updated but the Write Control unit 36 does not instruct the address calculation by the ACCB 30; If an X coordinate is sent to the X register memory address 2001 then the X-register is updated and the Write Control unit 36 instructs the address calculation by the ACCB 30 using the new X coordinate and the existing Y coordinate ; <img class="EMIRef" id="024185062-00090002" />

<tb> If <SEP> a <SEP> Y <SEP> coordinate <SEP> is <SEP> sent <SEP> to <SEP> the <SEP> Y <SEP> register <SEP> memory <SEP> address <SEP> 2002 <SEP> then <SEP> the <SEP> Y-register <tb> ZD <tb> is updated but the Write Control unit 36 does not instruct the address calculation by the ACCB 30; If a Y coordinate is sent to the Y register memory address 2003 then the Y register is updated and the Write Control unit 36 instructs the address calculation by the <img class="EMIRef" id="024185062-00090003" />

<tb> ACCB <SEP> 30 <SEP> using <SEP> the <SEP> new <SEP> Y <SEP> coordinate <SEP> and <SEP> the <SEP> existing <SEP> X <SEP> coordinate. <tb> c <SEP> 9 <tb> It <SEP> will <SEP> be <SEP> seen <SEP> that <SEP> the <SEP> address <SEP> calculation <SEP> by <SEP> the <SEP> ACCB <SEP> 30 <SEP> is <SEP> only <SEP> triggered <SEP> if <SEP> the <SEP> X <SEP> value <SEP> is <tb> c <SEP> I" <tb> written to the odd numbered X register address 2001 or the Y value is written to the odd numbered Y register address 2003. <img class="EMIRef" id="024185062-00100001" />

<tb>

Thus, <SEP> the <SEP> X-register <SEP> 24 <SEP> may <SEP> be <SEP> updated <SEP> by <SEP> writing <SEP> the <SEP> value <SEP> either <SEP> to <SEP> address <SEP> 2000 <SEP> or <SEP> to <tb> address <SEP> 2001, <SEP> but <SEP> only <SEP> the <SEP> latter <SEP> instructs <SEP> the <SEP> Pixel <SEP> pipeline <SEP> to <SEP> perform <SEP> the <SEP> address <SEP> calculation <tb> using the old Y coordinate and the new X coordinate. Therefore, in the calculation of, for example, a horizontal line, the X and Y coordinates of the first pixel in the line would be input sequentially to register addresses 2000 and 2003 which instructs the Pixel pipeline to perform the ACCB calculation using those values <RTI>of X</RTI> and Y. For generating the remaining pixels on the line, the CPU merely calculates the X coordinates of the remaining pixels and sequentially inputs them to address location 2001 which updates the X-register 24 and then instructs the Pixel pipeline to perform the ACCB calculation using the new X coordinate and the existing (constant) Y coordinate. There is no need for the CPU 12 to assemble an X, Y pair for each pixel, nor to update both data registers 24,26 in situations where one value is known to be constant for a series of pixels.

Whilst the graphics CPU remains responsible for calculating the location of every X, Y point (pixel) for a shape, the pixel pipeline 20 performs the following operations for each pixel of the shape: Accepts each pixel coordinate X, Y value from the graphics CPU; 2 Checks that the pixel falls within a given rectangular clipping window and discards the pixel if it falls outside the window. Plotting continues with the next two steps if the pixel is within the window ; 3 Calculates a linear memory address corresponding to the X, Y coordinate ; 4 Write the pixel as a point of colour to the calculated address location in memory.

Referring now to Figure 4, this shows in block form a modification to the Pixel pipeline 20 <img class="EMIRef" id="024185062-00100002" />

<tb> of <SEP> F*-p <tb> of <SEP> Figure <SEP> 3. <SEP> The <SEP> modification <SEP> comprises <SEP> the <SEP> addition <SEP> of <SEP> a <SEP> so-called <SEP> Style <SEP> Table <SEP> 42, <SEP> a <SEP> Style <tb> Counter <SEP> 44 <SEP> and <SEP> a <SEP> Colour <SEP> Select <SEP> Unit <SEP> 46. <tb> <img class="EMIRef" id="024185062-00110001" />

<tb>

A <SEP> common <SEP> feature <SEP> of <SEP> line <SEP> drawing <SEP> operations <SEP> in <SEP> graphics <SEP> is <SEP> the <SEP> need <SEP> to <SEP> incorporate <SEP> a"style". <tb> A <SEP> style <SEP> may <SEP> include <SEP> such <SEP> details <SEP> as <SEP> width, <SEP> texture, <SEP> end-cap <SEP> design <SEP> and <SEP> dashed <SEP> effects. <SEP> Dashed <tb> lines may be made up of coloured or opaque sections with transparent parts between them, or may be a pattern of two colours alternating along the line. The modification shown in Figure 4 allows the Pixel pipeline to draw dashed or two-colour lines with minimal CPU intervention.

The Style Table 42 is a region of local memory, for example a set of registers, or a small Random Access Memory (RAM), which holds a series of single bits representing the pattern of the style in which the line is to be drawn. Each bit in the Style Table indicates the colour of a corresponding pixel. For example, <RTI>a"I"might</RTI> represent a"foreground"colour and a"0" may represent a"background"colour. In this embodiment, therefore, a series of equal-sized dashes may be represented by ; <RTI>001100110011</RTI> ; while a mixture of dots and dashes may be represented by: 0010011100100111 The Style Table 42 is of sufficient size to hold the longest non-repeating bit pattern which may <img class="EMIRef" id="024185062-00110002" />

<tb> be <SEP> required <SEP> for <SEP> drawing <SEP> operations <SEP> and <SEP> the <SEP> contents <SEP> of <SEP> the <SEP> Style <SEP> Table <SEP> 42 <SEP> are <SEP> updated <SEP> by <SEP> the <tb> I <tb> CPU 12 when a new pattern of dots and dashes is required.

The Style Counter 44 is used to index the Style Table 42 and is advanced along the Style Table 42 as the line is drawn. The incrementing of the Style Counter depends on the thickness of the line. For a line 1 pixel wide the Style Counter 44 may be incremented after the plotting of every pixel. For a line 3 pixels wide the Style Counter 44 may be incremented after the plotting of every third pixel. Wide lines may have many pixels to be plotted across the line for each step along the line. The start position of the Style Counter 44 in the Style Table 42 <img class="EMIRef" id="024185062-00110003" />

<tb> is <SEP> determined <SEP> by <SEP> a <SEP> start <SEP> value <SEP> set <SEP> by <SEP> the <SEP> CPU <SEP> 12 <SEP> and <SEP> stored <SEP> in <SEP> a <SEP> Start <SEP> register <SEP> 48. <SEP> This <SEP> allows <tb> 0 <tb> <img class="EMIRef" id="024185062-00120001" />

<tb> any <SEP> dashed <SEP> effect <SEP> on <SEP> a <SEP> line <SEP> to <SEP> be <SEP> continued <SEP> correctly <SEP> when <SEP> the <SEP> line <SEP> is <SEP> drawn <SEP> in <SEP> a <SEP> number <SEP> of <tb> stages <SEP> as <SEP> in <SEP> the <SEP> case <SEP> of, <SEP> for <SEP> example, <SEP> zig-zag <SEP> lines. <SEP> The <SEP> point <SEP> in <SEP> the <SEP> Style <SEP> Table <SEP> 42 <SEP> at <SEP> which <tb> the Style Counter 44 returns to its start point is determined by a length value set by the CPU 12 and stored in a Length register 50. Thus, the interval at which the line style repeats can be any number of pixels up to the maximum size of the Style Table 42.

The Style Table 42 may operate in a number of modes determined by a value set by the CPU 12 and stored in a Mode register 52. In this embodiment, the value set in the Mode register represents one of three states, these being : <img class="EMIRef" id="024185062-00120002" />

<tb> ''solid"-the <SEP> output <SEP> of <SEP> the <SEP> Style <SEP> Table <SEP> is <SEP> ignored <SEP> and <SEP> all <SEP> pixels <SEP> are <SEP> plotted <SEP> ; <tb> I <tb> "dashed"-the pixel is plotted if the output of the Style Table is a"I"i. e a foreground colour but ignored if it is a"0"i. e. a background colour, the background colour effectively being transparent; "double dashed"-all pixels are plotted and the Style Table output determines whether the pixel is drawn in foreground or background colour.

The colour for each pixel to be plotted is selected by the Colour Select Unit 46 from colour registers 54,56 which store the information determining respectively the foreground (colour 1) and background (colour 2) colours.. The colour select unit is a multiplexor or data selector which selects the foreground or background colour data bits in response to the Fore/Back <img class="EMIRef" id="024185062-00120003" />

<tb> signal <SEP> from <SEP> the <SEP> Style <SEP> Table <SEP> 42. <SEP> A <SEP> Fore <SEP> signal <SEP> selects <SEP> colour <SEP> I <SEP> and <SEP> a <SEP> Back <SEP> signal <SEP> selects <SEP> colour <tb> z <SEP> : <SEP> l <tb> 2 In the embodiment of Figure 4, the X-register 24 and the Y-register 26 are each memorymapped to four locations in the memory, these being N to N+7. Thus, for example, the Xregister 24 may be arranged to appear at memory addresses N to N+3 while the Y-register may be mapped to appear at memory addresses N+4 to N+7. <img class="EMIRef" id="024185062-00130001" />

<tb> As <SEP> in <SEP> the <SEP> previous <SEP> embodiment, <SEP> the <SEP> action <SEP> taken <SEP> by <SEP> the <SEP> Pixel <SEP> pipeline <SEP> depends <SEP> on <SEP> the <SEP> memory <tb> address <SEP> used <SEP> to <SEP> store <SEP> the <SEP> pixel <SEP> coordinates <SEP> in <SEP> the <SEP> registers <SEP> 24, <SEP> 26. <SEP> If, <SEP> as <SEP> an <SEP> example <SEP> we <tb> represent memory addresses N to N+7 by 4000 to 4007 respectively, the operations performed for each memory address may be as follows : If an X coordinate is sent to the X register memory address 4000 then the X-register is updated but the Write Control unit 36 does instruct the address calculation by the ACCB 30 ; If an X coordinate is sent to the X register memory address 4001 then the X-register is updated and the Write Control unit 36 instructs the address calculation by the ACCB <RTI>30</RTI> using the new X coordinate and the existing Y coordinate ; If an X coordinate is sent to the X register memory address 4002 then the X-register is updated and the Style Counter is advanced but the Write Control unit 36 does not instruct the address calculation by the ACCB 30; <img class="EMIRef" id="024185062-00130002" />

<tb> If <SEP> an <SEP> X <SEP> coordinate <SEP> is <SEP> sent <SEP> to <SEP> the <SEP> X <SEP> register <SEP> memory <SEP> address <SEP> 4003 <SEP> then <SEP> the <SEP> X-register <tb> c <tb> is updated and the Write Control unit 36 instructs the address calculation by the ACCB 30 using the new X coordinate and the existing Y coordinate. The Style Counter is advanced; If a Y coordinate is sent to the Y register memory address 4004 then the Y-register is updated but the Write Control unit 36 does not instruct the address calculation by the ACCB 30 ; If a Y coordinate is sent to the Y register memory address 4005 then the Y register is updated and the Write Control unit 36 instructs the address calculation by the ACCB 30 using the new Y coordinate and the existing X coordinate.

If a Y coordinate is sent to the Y register memory address 4006 then the Y-register <img class="EMIRef" id="024185062-00140001" />

<tb> is <SEP> updated <SEP> but <SEP> the <SEP> Write <SEP> Control <SEP> unit <SEP> 36 <SEP> does <SEP> not <SEP> instruct <SEP> the <SEP> address <SEP> calculation <SEP> by <tb> the <SEP> ACCB <SEP> 30. <SEP> The <SEP> Style <SEP> Counter <SEP> is <SEP> advanced <tb> If a Y coordinate is sent to the Y register memory address 4007 then the Y register is updated and the Write Control unit 36 instructs the address calculation by the ACCB 30 using the new Y coordinate and the existing X coordinate. The Style Counter is advanced An example is now described of the generation of a dashed line having a sequence of four, two-pixel dashes which alternate in colour.

Firstly, a style with the following bit pattern is selected in the Style Table 42 by the CPU 12 00110011 The Mode register 52 sets the mode of the Style Table 42 to"double dashed". The start position of the Style Counter 44 is set at zero by the Start register 48 and the length of the repeating pattern or style to be drawn is set at eight by the Length register 50. The appropriate colours, for example green and blue, are set in the first and second colour registers 54,56 respectively by the CPU 12 The CPU 12 then calculates the pixel coordinates for the first pixel in the line and stores the X coordinate in the X-register 24 at memory address 4000 and the Y coordinate in the Yregister at memory address 4007. The latter operation updates the Y-register and instructs the Pixel pipeline to carry out the ACCB calculation and store the data for the pixel at the calculated memory address location. Since the Style Counter initially indexes the first bit in the Style Table (this <RTI>being a"0")</RTI> the Style Table outputs a"0"as the Fore/Back Style signal representing a background colour. This value is applied to the colour select unit 46 which selects the background colour (blue) from the second colour register 56 and outputs the data value representing that colour onto the output data bus 32 for storage at the calculated location in memory. In addition, the use of address 4007 for storage of the Y coordinate <img class="EMIRef" id="024185062-00150001" />

<tb> instructs <SEP> the <SEP> Style <SEP> Counter <SEP> 44 <SEP> to <SEP> advance <SEP> along <SEP> the <SEP> Style <SEP> Table <SEP> 42 <SEP> by <SEP> one. <tb>

The CPU 12 then calculates the coordinates of the next pixel in the line. If the line is horizontal, the Y coordinate will not change and so the CPU 12 applies the X coordinate of the next pixel to memory address 4003. This operation updates the X-register 24 with the new X coordinate and instructs the Pixel pipeline to perform the ACCB calculation on the new X coordinate and the existing Y coordinate. Since the Style Counter is still indexing a zero in the Style Table, the data for the pixel output by the colour select unit 46 is still representative of a blue colour and thus, this data is output to the output data bus 32 for storage at the calculated location in memory. Storage of the new X coordinate at address 4003 also instructs the Style Counter 44 to advance by one in the Style Table 42.

The CPU 12 then calculates the position of the next pixel in the line. Again, the Y coordinate does not change and the new X coordinate is therefore stored at memory address 4003. This operation updates the X-register 24 with the new X coordinate and instructs the Pixel pipeline to perform the ACCB calculation on the new X coordinate and the existing Y coordinate.

Since the Style Counter is now indexing <RTI>a"1",</RTI> this value is applied as the Fore/Back Style signal by the Style Table 42 to the colour select unit 46 which selects the foreground colour (green) from the first colour register 54 and a data value representative of this colour is output by the colour select unit 46 to the output data bus 32 for storage at the calculated memory location.

The further steps in the generation of this line will be clear from the above.

It will be appreciated that a similar line could have been produced using a style of <RTI>0101</RTI> where the Y coordinate of the first pixel is stored at memory address 4005 so that the Style Counter is not incremented after the ACCB calculation is performed. This ensures that the second pixel will be the same colour as the first. The X coordinate of the second pixel is then stored at 4003 to ensure that the Style Counter 44 is incremented after the ACCB calculation is performed such that the third pixel is in the new colour. The X coordinate of the third pixel is stored at 4001 so that the Style Counter 44 is not incremented and the fourth pixel will be <img class="EMIRef" id="024185062-00160001" />

<tb> the <SEP> same <SEP> colour <SEP> as <SEP> the <SEP> third. <tb>

It will also be appreciated that simple styles can be derived from more complex styles stored in the Style Table 42. For example, the style <RTI>001001100111...</RTI> will generate a dashed line having increasing dash lengths. However, the dashed line described in the preceding paragraphs could also be derived from this style by setting the Style Counter 44 start position to"2"and the length value to"2". Thus, the storage of only a small number of complex styles allows the derivation of a large number of more simple styles and hence the amount of memory required to store a selection of styles is reduced.

It can be seen that the above-described embodiment provides a number of advantages. Again, there is no requirement for the CPU 12 to assemble an X, Y coordinate pair for each pixel drawn, nor is there a need to update registers in situations where one value is known to be constant for a series of pixels e. g. drawing a horizontal line. Furthermore, however, simultaneous advance of the Style Counter 44 may be achieved with pixel writing when required.

As can be seen therefore the pixel pipeline 20 performs the following operations: <RTI>1 It</RTI> holds locally a reference pattern of bits representing a line style in a Style Table; 2 It steps through the Style Table as the drawing operation moves along a <RTI>line ;</RTI> 3 It assigns each pixel a foreground or background colour according to the value of the current entry in the Style Table; 4 It can deem a pixel transparent so that the pixel is not plotted.

Referring to Figure 5, this shows a modification to the output stages of the pixel pipeline of Figure 4. The Style Count 44, Style Table 42, Mode register 52, Clip unit 34, X, Y Registers 24,26 and address <RTI>decoder 35</RTI> are omitted for clarity. Since the capacity of the system <img class="EMIRef" id="024185062-00170001" />

<tb> memory <SEP> 14 <SEP> and <SEP> bandwidth <SEP> of <SEP> the <SEP> system <SEP> bus <SEP> 16 <SEP> are <SEP> valuable <SEP> resources <SEP> within <SEP> a <SEP> high <tb> I <tb> performance <SEP> computer <SEP> system, <SEP> it <SEP> is <SEP> desirable <SEP> to <SEP> minimize <SEP> the <SEP> amount <SEP> of <SEP> memory <SEP> used <SEP> in <tb> drawing <SEP> basic <SEP> shapes <SEP> and <SEP> to <SEP> minimize <SEP> the <SEP> number <SEP> of <SEP> write <SEP> operations <SEP> to <SEP> the <SEP> memory <SEP> to <SEP> reduce <tb> 1- <SEP> n <tb> the demand on the system bus.

The pixel depth represents the number of memory bits used to store each pixel (i. e. the length of binary number representing each pixel). In the previously described embodiments, it is assumed that the pixel depth is equal to or greater than the smallest writeable unit or data "word"within the system memory. However, in many instances, the pixel depth will be considerably smaller than the smallest writeable unit in the memory such that data for two or more pixels to be drawn could be stored within a single memory word i. e. at a single memory address.

During operation of the embodiment of figure 5, the X, Y coordinates for each pixel, together with the Style signal value from the Style Table 42, are output by the data buffer 28 and are applied to the ACCB 30 and the make-data unit 60, respectively. The ACCB 30 calculates the linear memory address corresponding to the pixel coordinates and then splits the address into two parts. The first part is a"word <RTI>address"representing the</RTI> word in the system memory 14 which should contain the pixel data, while the second part is a"bit address"representing where within the memory word the data for the pixel is placed. In calculating the bit address for the pixel data, the ACCB 30 uses the pixel depth which represents the number of memory bits used to store each individual pixel.

In the modification of Figure 5 the Fore/Back style signal is applied through the buffer 28 to a Make Data circuit 60 which is in turn connected through a multiplexor logic unit 61 and data register 62 to the bus 32. The make data circuit 60 is a multiplexor or data selector which selects the foreground or background colour data bits in response to the Fore/Back signal from the buffer 28. The ACCB 30 has two outputs. One is for the bit address and is connected to the logic unit 61 whilst the second is for the word address and is connected <img class="EMIRef" id="024185062-00170002" />

<tb> through <SEP> a <SEP> delay <SEP> register <SEP> 63 <SEP> and <SEP> comparator <SEP> 64 <SEP> to <SEP> the <SEP> Read/Write <SEP> Control <SEP> 36. <tb>

I-ZD <tb> <img class="EMIRef" id="024185062-00180001" />

<tb> The <SEP> arrangement <SEP> of <SEP> Figure <SEP> 5 <SEP> enables <SEP> two <SEP> possible <SEP> operations <SEP> to <SEP> be <SEP> carried <SEP> out <SEP> using <SEP> the <SEP> data <tb> register <SEP> 62. <tb>

The <SEP> data <SEP> register <SEP> can <SEP> be <SEP> used <SEP> to <SEP> hold <SEP> pixel <SEP> data <SEP> locally <SEP> while <SEP> new <SEP> pixel <SEP> datais <SEP> inserted <tb> 0 <tb> as part of a Read-Modify-Write (RMW) operation; 2 The data register 64 can be used to combine data for multiple pixels all destined for the same word address in memory 14.

It is possible for these two operations to be used simultaneously.

Read-Modify-Write <RTI>(RMW)</RTI> operation The data register 62 is of a size having the same number of bits as a full memory bus word.

It is used to hold data for a pixel while new pixel data is inserted, replacing the original pixel data. After the ACCB 30 has calculated the word and bit addresses for a pixel, if the pixel depth of a pixel is less than the smallest writeable unit within memory (one example would be where each pixel is four bits long but the memory has byte-wide (8 Bit) words) then the memory word to which the pixel is to be written is read from the memory 14 by the Pixel pipeline and stored in the local data register <RTI>62.</RTI> The colour data selected by the make data <RTI>circuit 60</RTI> using the Fore/Back signal for the pixel is then inserted in the correct position within the word stored in the data register 62 by means of the logic unit 61 using the bit address for the pixel calculated by the ACCB <RTI>30</RTI> and applied to one input of the logic circuit 61. The new pixel data thus replaces the previous pixel data.

The resulting word is then written back to the system memory 14 via the output data bus 32 and the system bus 16. This is under the control of the write control unit 36. Such an operation is termed <RTI>a"read-modify-write"operation</RTI> since the memory word is firstly read from the memory 14, modified in the local data register 62 by the logic unit 61 and then written back to memory. <img class="EMIRef" id="024185062-00190001" />

<tb> The <SEP> steps <SEP> can <SEP> be <SEP> summarised <SEP> as <SEP> follows <SEP> : <tb> 1 <SEP> Calculate <SEP> the <SEP> word <SEP> and <SEP> bit <SEP> addresses <SEP> ; <tb> 2 <SEP> Read <SEP> the <SEP> main <SEP> memory <SEP> 14 <SEP> at <SEP> the <SEP> word <SEP> address <SEP> to <SEP> retrieve <SEP> the <SEP> data <SEP> word <SEP> ; <tb> 3 Store the word in the register 62; 4 Update the word at the bit address with the new pixel data; 5 Write the resulting word back to the memory address.

Same word address The word address for the pixel is applied both to a delay register 63 and to one input of a comparator unit 64. The delay register 63 delays the word address by one cycle or calculation of the ACCB 30 and applies its output to a second input of the comparator 64. The effect is that the comparator 64 compares the word address of the current pixel with the word address of the previous pixel. If the comparison by the comparator 64 indicates that the two compared word addresses are the same, this indicates that the two consecutive pixels are to be stored at the same word address in the memory 14.

In response to the result of this comparison the <RTI>Read/Write</RTI> Control 36 then causes the <img class="EMIRef" id="024185062-00190002" />

<tb> multiplexor <SEP> logic <SEP> unit <SEP> 61 <SEP> to <SEP> insert <SEP> the <SEP> data <SEP> bits <SEP> for <SEP> the <SEP> current <SEP> data <SEP> into <SEP> the <SEP> data <SEP> which <SEP> has <tb> p <SEP> 7 <tb> previously been written to the local data register 62, and update the register 62 with the combined data. A single write operation to the memory 14 is made at the end of the run of identical word addresses. This provides improved performance in terms of speed and bus occupancy.

When it is found that data for a pixel is to be written to the same memory word address as the previous pixel, as determined by the comparator 64 then the read/write control unit 36 <img class="EMIRef" id="024185062-00200001" />

<tb> instructs <SEP> the <SEP> local <SEP> data <SEP> register <SEP> 62 <SEP> to <SEP> carry <SEP> out <SEP> one <SEP> of <SEP> two <SEP> operations. <tb>

ID <tb> If the previous write operation has not yet taken place, this can be postponed and the data for this and the subsequent pixel are multiplexed together by the logic unit 61. The new data <img class="EMIRef" id="024185062-00200002" />

<tb> word <SEP> is <SEP> written <SEP> back <SEP> to <SEP> memory <SEP> once <SEP> all <SEP> pixels <SEP> for <SEP> that <SEP> single <SEP> memory <SEP> word <SEP> have <SEP> been <tb> 0 <tb> combined. Advantageously, only one read and one write operation will have taken place.

Alternatively, if the previous write operation has already occurred, the local data register 62 will still contain the data which was previously modified and written. The data for the next pixel is then inserted into the correct position in the word by the logic unit 61 and the local data register 62 without performing a read operation. The new data word assembled in this way is then written back to memory. In this operation, it will be appreciated that two write operations but only one read operation will have taken place.

It will be appreciated that the logic unit 61, the local data register 62 and the comparator 64 are separate units and it is therefore possible for the read-modify-write operations and the "same address comparison"operation to be used simultaneously.

The embodiment of Figure 5 performs the following operations: Control of loading of the local data register <RTI>62 ;</RTI> 2 Control of multiplex functions for insertion and combination of new pixel data within <img class="EMIRef" id="024185062-00200003" />

<tb> the <SEP> local <SEP> data <SEP> register <SEP> 62 <SEP> ; <tb> c <tb> 3 <SEP> Suppression <SEP> of <SEP> the <SEP> write <SEP> operation <SEP> when <SEP> the <SEP> same <SEP> address <SEP> flag <SEP> indicates <SEP> that <SEP> the <SEP> next <tb> 0 <tb> pixel in the pixel pipeline is to be written to the same memory word.

The write control unit 36 is thus responsible for the control of loading of the local data register 62, the control of the logic unit 61 multiplexing and replacement functions for the insertion or combination of new pixel data within the local data register 62, and the suppression of the write operation when the comparator 64 indicates that the next pixel in the pixel pipeline is to be written to the same memory word.

It will be appreciated by those skilled in the art that the present invention is able to reduce considerably the time needed for the generation of graphics in a computer system and in doing so, significantly reduces the burden on the system CPU. The performance of the system is thus greatly increased with improved efficiency and the ability to generate much higher resolution graphics.

Claims (69)

  1. <img class="EMIRef" id="024185063-00220001" />
    <tb>
    CLAIMS <tb> <RTI>1. An</RTI> apparatus for generating a region of graphics on a display, the apparatus comprising : <img class="EMIRef" id="024185063-00220002" />
    <tb> register <SEP> means <SEP> for <SEP> storing <SEP> the <SEP> coordinates <SEP> on <SEP> the <SEP> display <SEP> of <SEP> a <SEP> pixel <SEP> to <SEP> be <SEP> drawn <SEP> ; <tb> I <tb> calculation means for receiving said coordinates from said register means and calculating the address of a location in a memory for storage of data corresponding to said pixel in dependance on said coordinates ; and <img class="EMIRef" id="024185063-00220003" />
    <tb> control <SEP> means <SEP> for <SEP> controlling <SEP> said <SEP> register <SEP> means <SEP> and <SEP> said <SEP> calculation <SEP> means <SEP> to <SEP> cause <SEP> said <SEP> data <tb> ion <SEP> means <SEP> to <SEP> c <tb> to be written to and stored in said memory at said calculated address.
  2. 2. An apparatus as claimed in claim I wherein said register means comprises first and second registers for storing X and Y coordinates respectively of said pixel.
    <RTI>
  3. 3. An</RTI> apparatus as claimed in claim <RTI>1 or</RTI> 2 wherein said calculation means is operable to calculate said address using the equation: Address = Base + A + B* Pitch where Base and Pitch are predetermined constants; A is one of said X and Y coordinates; and B is the other of said X and Y coordinates.
  4. 4. An apparatus as claimed in claim 3 wherein A is said X coordinate and B is said Y coordinate. <img class="EMIRef" id="024185063-00230001" />
    <tb>
  5. 5. <SEP> An <SEP> apparatus <SEP> as <SEP> claimed <SEP> in <SEP> claim <SEP> 3 <SEP> or <SEP> 4 <SEP> wherein <SEP> : <tb> said <SEP> Base <SEP> is <SEP> the <SEP> coordinate <SEP> of <SEP> a <SEP> reference <SEP> pixel <SEP> of <SEP> the <SEP> region <SEP> to <SEP> be <SEP> displayed <SEP> ; <SEP> and <tb> said Pitch is the number of pixels in one horizontal line of said region.
  6. 6. An apparatus as claimed in any of claims 1 to 5 further comprising clipping means for comparing said coordinates with predetermined clipping limits and generating a clipping signal in dependence thereon.
  7. 7. An apparatus as claimed in claim 6 wherein said control means is operable to control the writing of said data to said calculated address in memory in dependence on said clipping signal.
  8. 8. An apparatus as claimed in claim 6 or 7 wherein said control means is operable to control the calculation of said address in memory in dependence on said clipping signal.
  9. 9. An apparatus as claimed in any of claims 6 to 8 wherein: in response to said coordinates falling within said predetermined clipping limits, said control means controls said calculation means to calculate said address and causes said data to be written to and stored in said calculated address in memory ; and in response to said coordinates falling outside said predetermined limits, said control means prevents said calculation.
  10. 10. An apparatus as claimed in any of claims 6 to 9 further comprising store means for storing said clipping limits.
  11. 11. An apparatus as claimed in any of claims 1 to 10 further including buffer means <img class="EMIRef" id="024185063-00240001" />
    <tb> connected <SEP> between <SEP> said <SEP> register <SEP> means <SEP> and <SEP> said <SEP> calculation <SEP> means <SEP> for <SEP> buffering <SEP> the <tb> transmission <SEP> of <SEP> said <SEP> coordinates <SEP> therebetween <SEP> under <SEP> the <SEP> control <SEP> of <SEP> said <SEP> control <tb> means.
  12. 12. An apparatus as claimed in any of claims 2 to 11 wherein said first register is memory mapped to first and second locations in said memory and said second register is memory mapped to third and fourth locations in said memory; and said apparatus further comprises address decoder means for monitoring said first to fourth memory address locations and applying a location signal to said write control means representative of the address location being written to.
  13. 13. An apparatus as claimed in claim 12 wherein said control means controls said register means, said buffer means and said calculation means in response to receipt of said address location signal from said address decoder means.
  14. 14. An apparatus as claimed in claim 12 or 13 wherein said control means is operable to instruct said calculating means to calculate said memory address for a pixel coordinate in response to one of the following: an X coordinate being sent to the X register at a preselected one of said first and second memory addresses; a Y coordinate being sent to the Y register at a preselected one of said third and fourth memory addresses.
  15. 15. An apparatus as claimed in claim 14 wherein said preselected addresses are the second and fourth address locations.
  16. 16. An apparatus for generating a region of graphics on a display, the apparatus comprising : <img class="EMIRef" id="024185063-00250001" />
    <tb> register <SEP> means <SEP> for <SEP> storing <SEP> the <SEP> coordinates <SEP> on <SEP> said <SEP> display <SEP> of <SEP> a <SEP> pixel <SEP> to <SEP> be <SEP> drawn <SEP> ; <tb> calculation means for receiving said coordinates from said register means and calculating the address of a location in a memory for storage of data corresponding to said pixel in dependance on said coordinates; and control means for controlling said register means and said calculation means to cause said data to be written to and stored in said memory at said calculated address; style table means for storing data corresponding to a predetermined pattern or style for each said pixel to be drawn; and style counter means for indexing said data in said style table means and generating a style data signal corresponding to said indexed data.
  17. 17. An apparatus as claimed in claim 16 wherein said style table means is large enough to store the longest non-repeating bit pattern required for a drawing operation.
  18. 18. An apparatus as claimed in claim 16 or 17 wherein said register means comprises first and second registers for storing X and Y coordinates respectively of said pixel.
  19. 19. An apparatus as claimed in claim 16,17 or 18 wherein said calculation means is operable to calculate said address using the equation: Address = Base + A + B* Pitch where Base and Pitch are predetermined constants; A is one of said X and Y coordinates; and <img class="EMIRef" id="024185063-00260001" />
    <tb> B <SEP> is <SEP> the <SEP> other <SEP> of <SEP> said <SEP> X <SEP> and <SEP> Y <SEP> coordinates. <tb>
  20. 20. <SEP> An <SEP> apparatus <SEP> as <SEP> claimed <SEP> in <SEP> claim <SEP> 19 <SEP> wherein <SEP> A <SEP> is <SEP> said <SEP> X <SEP> coordinate <SEP> and <SEP> B <SEP> is <SEP> said <SEP> Y <tb> coordinate.
  21. 21. An apparatus as claimed in claim 19 or 20 wherein: said Base is the coordinate of a reference pixel of the region to be displayed; and said Pitch is the number of pixels in one horizontal line of said region.
  22. 22. An apparatus as claimed in any of claims 16 to 21 further comprising clipping means for comparing said coordinates with predetermined clipping limits and generating a clipping signal in dependence thereon.
  23. 23. An apparatus as claimed in claim 22 wherein said control means is operable to control the writing of said data to said calculated address in memory in dependence on said clipping signal.
  24. 24. An apparatus as claimed in claim 22 or 23 wherein: in response to said coordinates falling within said predetermined clipping limits, said control means controls said calculation means to calculate said address and causes said data to be written to and stored in said calculated address in memory; and in response to said coordinates falling outside said predetermined limits, said control means prevents said calculation.
  25. 25. An apparatus as claimed in claim 22,23 or 24 further comprising store means for storing said clipping limits. <img class="EMIRef" id="024185063-00270001" />
    <tb>
  26. 26. <SEP> An <SEP> apparatus <SEP> as <SEP> claimed <SEP> in <SEP> any <SEP> of <SEP> claims <SEP> 16 <SEP> to <SEP> 25 <SEP> further <SEP> including <SEP> buffer <SEP> means <tb> connected <SEP> between <SEP> said <SEP> register <SEP> means <SEP> and <SEP> said <SEP> calculation <SEP> means <SEP> for <SEP> buffering <SEP> the <tb> transmission of said coordinates therebetween under the control of said control means.
  27. 27. An apparatus as claimed in claim 18 wherein said first register is memory mapped to first to fourth locations in said memory and said second register is memory mapped to fifth to eighth locations in said memory; and said apparatus further comprises address decoder means for monitoring said first to eighth memory address locations, applying a location signal to said write control means representative of the address location being written to and indexing said style counter means in response to the address location being written to.
  28. 28. An apparatus as claimed in claim 27 wherein said control means controls said register means, said buffer means and said calculation means in response to receipt of said address location signal from said address decoder means.
  29. 29. An apparatus as claimed in claim 27,28 or 29 wherein said control means is operable to instruct said calculating means to calculate said memory address for a pixel coordinate in response to one of the following: an X coordinate being sent to the X register at a preselected one of said first to fourth memory addresses; a Y coordinate being sent to the Y register at a preselected one of said fifth to eighth memory addresses.
  30. 30. An apparatus as claimed in claim 29 wherein said preselected addresses are the second, fourth, sixth and eighth address locations. <img class="EMIRef" id="024185063-00280001" />
    <tb>
  31. 31. <SEP> An <SEP> apparatus <SEP> claimed <SEP> as <SEP> claimed <SEP> in <SEP> any <SEP> of <SEP> claims <SEP> 27 <SEP> to <SEP> 30 <SEP> wherein <SEP> said <SEP> style <SEP> counter <tb> means <SEP> is <SEP> advanced <SEP> in <SEP> response <SEP> to <SEP> one <SEP> of <SEP> the <SEP> following <SEP> : <tb> an X coordinate being sent to the X register at a preselected one of said first to fourth memory addresses; a Y coordinate being sent to the Y register at a preselected one of said fifth to eighth memory addresses.
  32. 32. An apparatus as claimed in claim 31 wherein said preselected addresses are the third, fourth, seventh and eighth address locations.
  33. 33. An apparatus claimed as claimed in claim 29 wherein said style counter means is advanced in response to one of the following: an X coordinate being sent to the X register at a preselected one of said first to fourth memory addresses; a Y coordinate being sent to the Y register at a preselected one of said fifth to eighth memory addresses.
  34. 34. An apparatus as claimed in claim 33 wherein said preselected addresses are the third, fourth, seventh and eighth address locations.
  35. 35. An apparatus as claimed in any of claims 16 to 34 further comprising selector means for selecting a colour for said pixel to be drawn in dependence on said style data signal.
  36. 36. An apparatus for generating a region of graphics on a display, the apparatus comprising : <img class="EMIRef" id="024185063-00290001" />
    <tb> coordinate <SEP> register <SEP> means <SEP> for <SEP> storing <SEP> the <SEP> coordinates <SEP> on <SEP> said <SEP> display <SEP> of <SEP> a <SEP> pixel <SEP> to <SEP> be <SEP> drawn <SEP> ; <tb> calculation <SEP> means <SEP> for <SEP> receiving <SEP> said <SEP> coordinates <SEP> from <SEP> said <SEP> register <SEP> means <SEP> and <SEP> calculating <SEP> the <tb> address of a location in a memory for storage of data corresponding to said pixel in dependance on said coordinates; and control means for controlling said register means and said calculation means to cause said data to be written to and stored in said memory at said calculated address; wherein said calculation means outputs said address in two parts, the first part being a word address corresponding to the calculated address location in said memory and representing the single memory word and the second part being a bit address representing the position of the pixel data within the memory word.
  37. 37. An apparatus as claimed in claim 36 further comprising register means for storing said pixel data in said single memory word prior to said word being written to said calculated address in said memory, said register means being capable of storing one memory word; and multiplexer means for writing data to said register means in dependence on the word or bit addresses calculated by said calculating means.
  38. 38. An apparatus as claimed in claim 37 wherein said multiplexing means combines data for two or more pixels to be drawn in dependence on the word address of each said pixel thereby to permit storage of the data for said two or more pixels in a single memory word.
  39. 39. An apparatus as claimed in claim 37 or 38 further comprising comparator means connected to said calculation means for receiving said word addresses, comparing the word address of consecutive pixels to be drawn and generating a same address signal if said word addresses are identical. <img class="EMIRef" id="024185063-00300001" />
    <tb>
  40. 40. <SEP> An <SEP> apparatus <SEP> as <SEP> claimed <SEP> in <SEP> claim <SEP> 37, <SEP> 38 <SEP> or <SEP> 39 <SEP> wherein <SEP> said <SEP> control <SEP> means <SEP> is <SEP> operable <tb> in <SEP> response <SEP> to <SEP> receipt <SEP> of <SEP> said <SEP> same <SEP> address <SEP> signal <SEP> to <SEP> control <SEP> said <SEP> multiplexing <SEP> means <tb> to combine said data for said pixels to be drawn.
  41. 41. An apparatus as claimed in any of claims 36 to 40 wherein said multiplexing means comprises a multiplexor for receiving said bit address and said pixel data.
  42. 42. An apparatus as claimed in any of claims 36 to 41 wherein said calculation means is operable to calculate said address using the equation: Address = Base + A + B* Pitch where Base and Pitch are predetermined constants; A is one of said X and Y coordinates; and B is the other of said X and Y coordinates.
  43. 43. An apparatus as claimed in claim 42 wherein A is said X coordinate and B is said Y coordinate.
  44. 44. An apparatus as claimed in claim 42 or 43 wherein: said Base is the coordinate of a reference pixel of the region to be displayed; and said Pitch is the number of pixels in one horizontal line of said region.
  45. 45. A method of generating a region of graphics on a display, the method comprising: receiving X and Y coordinates of a pixel to be drawn in said region; <img class="EMIRef" id="024185063-00310001" />
    <tb> storing <SEP> said <SEP> coordinates <SEP> ; <tb> calculating the address of a location in a memory for storage of data corresponding to said pixel in dependance on said coordinates; and causing said data to be written to and stored in said memory at said calculated address.
  46. 46. A method as claimed in claim 45 wherein storing said coordinates comprises storing X and Y coordinates of said pixel in first and second registers.
  47. 47. A method as claimed in claim 45 or 46 wherein said address is calculated using the equation: Address = Base + A + B* Pitch where Base and Pitch are predetermined constants; A is one of said X and Y coordinates; and B is the other of said X and Y coordinates.
  48. 48. A method as claimed in claim 47 wherein A is said X coordinate and B is said Y coordinate.
  49. 49. A method as claimed in claim 47 or 48 wherein: said Base is the coordinate of a reference pixel of the region to be displayed; and said Pitch is the number of pixels in one horizontal line of said region.
  50. 50. A method as claimed in any of claims 45 to 49 further comprising comparing said <img class="EMIRef" id="024185063-00320001" />
    <tb> coordinates <SEP> with <SEP> predetermined <SEP> clipping <SEP> limits <SEP> and <SEP> discarding <SEP> said <SEP> pixel <SEP> data <SEP> in <tb> response to said coordinates exceeding said clipping limits.
  51. 51. A method as claimed in any of claims 46 to 50 wherein said first register is memory mapped to first and second locations in said memory and said second register is memory mapped to third and fourth locations in said memory; and said method further comprises: monitoring said first to fourth memory address locations; and calculating said memory address for a pixel coordinate in response to one of the following: an X coordinate being sent to the X register at a preselected one of said first and second memory addresses; a Y coordinate being sent to the Y register at a preselected one of said third and fourth memory addresses.
  52. 52. A method as claimed in claim 51 wherein said preselected addresses are the second and fourth address locations.
  53. 53. A method for generating a region of graphics on a display, the method comprising: receiving X and Y coordinates of a pixel to be drawn in said region; storing said coordinates; calculating the address of a location in a memory for storage of data corresponding to said pixel in dependance on said coordinates; <img class="EMIRef" id="024185063-00330001" />
    <tb> storing <SEP> style <SEP> data <SEP> corresponding <SEP> to <SEP> a <SEP> predetermined <SEP> pattern <SEP> or <SEP> style <SEP> for <SEP> each <SEP> said <SEP> pixel <SEP> to <SEP> be <tb> drawn <SEP> ; <tb> indexing said style data and generating a style data signal corresponding to said indexed data; and causing said data to be written to and stored in said memory at said calculated address.
  54. 54. A method as claimed in claim 53 wherein said register means comprises first and second registers for storing X and Y coordinates respectively of said pixel.
  55. 55. A method as claimed in claim 54 wherein said first register is memory mapped to first to fourth locations in said memory and said second register is memory mapped to fifth to eighth locations in said memory; and said method further comprises monitoring said first to eighth memory address locations and indexing said style counter means in response to the address location being written to.
  56. 56. A method as claimed in claim 55 wherein said memory address for a pixel coordinate is calculated in response to one of the following: an X coordinate being sent to the X register at a preselected one of said first to fourth memory addresses; a Y coordinate being sent to the Y register at a preselected one of said fifth to eighth memory addresses.
  57. 57. A method as claimed in claim 56 wherein said preselected addresses are the second, fourth, sixth and eighth address locations.
  58. 58. A method claimed as claimed in any of claims 55 to 57 wherein said style data is advanced in response to one of the following: <img class="EMIRef" id="024185063-00340001" />
    <tb> an <SEP> X <SEP> coordinate <SEP> being <SEP> sent <SEP> to <SEP> the <SEP> X <SEP> register <SEP> at <SEP> a <SEP> preselected <SEP> one <SEP> of <SEP> said <SEP> first <SEP> to <SEP> fourth <tb> memory addresses; a Y coordinate being sent to the Y register at a preselected one of said fifth to eighth memory addresses.
  59. 59. A method as claimed in claim 58 wherein said preselected addresses are the third, fourth, seventh and eighth address locations.
  60. 60. A method claimed as claimed in any of claims 56 to 59 wherein said style data is advanced in response to one of the following: an X coordinate being sent to the X register at a preselected one of said first to fourth memory addresses; a Y coordinate being sent to the Y register at a preselected one of said fifth to eighth memory addresses.
  61. 61. A method as claimed in claim 60 wherein said preselected addresses are the third, fourth, seventh and eighth address locations.
  62. 62. A method as claimed in any of claims 53 to 61 further comprising selecting a colour for said pixel to be drawn in dependence on said style data signal.
  63. 63. A method for generating a region of graphics on a display, the method comprising: receiving X and Y coordinates of a pixel to be drawn in said region; storing said coordinates; <img class="EMIRef" id="024185063-00350001" />
    <tb> calculating <SEP> the <SEP> address <SEP> of <SEP> a <SEP> location <SEP> in <SEP> a <SEP> memory <SEP> for <SEP> storage <SEP> of <SEP> data <SEP> corresponding <SEP> to <SEP> said <tb> pixel <SEP> in <SEP> dependance <SEP> on <SEP> said <SEP> coordinates <SEP> ; <tb> causing said data to be written to and stored in said memory at said calculated address. wherein the step of calculating comprises calculating said address in two parts, the first part being a word address corresponding to the calculated address location in said memory and representing the single memory word and the second part being a bit address representing the position of the pixel data within the memory word.
  64. 64. A method as claimed in claim 63 further comprising storing said pixel data in said single memory word prior to said word being written to said calculated address in said memory; and storing said data in said single memory word in dependence on the calculated word or bit addresses.
  65. 65. A method as claimed in claim 64 further comprising combining data for two or more pixels to be drawn in dependence on the word address of each said pixel thereby to <RTI>permit</RTI> storage of the data for said two or more pixels in a single memory word.
  66. 66. A method as claimed in claim 64 or 65 further comprising comparing the word address of consecutive pixels to be drawn and combining said data for said pixels to be drawn if said word addresses are identical.
  67. 67. A method as claimed in any of claims 63 to 66 wherein said calculation means is operable to calculate said address using the equation: Address = Base + A + B* Pitch where Base and Pitch are predetermined constants; <img class="EMIRef" id="024185063-00360001" />
    <tb> A <SEP> is <SEP> one <SEP> of <SEP> said <SEP> X <SEP> and <SEP> Y <SEP> coordinates <SEP> ; <SEP> and <tb> B <SEP> is <SEP> the <SEP> other <SEP> of <SEP> said <SEP> X <SEP> and <SEP> Y <SEP> coordinates. <tb>
  68. 68. A method as claimed in claim 67 wherein A is said X coordinate and B is said Y coordinate.
  69. 69. A method as claimed in claim 67 or 68 wherein: said Base is the coordinate of a reference pixel of the region to be displayed; and said Pitch is the number of pixels in one horizontal line of said region.
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