GB2319131A - Driver for a liquid crystal display - Google Patents

Driver for a liquid crystal display Download PDF

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Publication number
GB2319131A
GB2319131A GB9623401A GB9623401A GB2319131A GB 2319131 A GB2319131 A GB 2319131A GB 9623401 A GB9623401 A GB 9623401A GB 9623401 A GB9623401 A GB 9623401A GB 2319131 A GB2319131 A GB 2319131A
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Patent type
Prior art keywords
data
signal
circuit
latch
video signals
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9623401A
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GB2319131B (en )
GB9623401D0 (en )
Inventor
Hee Gyung Yoon
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LG Electronics Inc
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LG Electronics Inc
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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems
    • H04N3/10Scanning details of television systems by means not exclusively optical-mechanical
    • H04N3/12Scanning details of television systems by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
    • H04N3/127Scanning details of television systems by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/027Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0297Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Abstract

A single integrated circuit (IC) includes a data latch circuit (22, 23) for latching and outputting at least two sets of three video signals (D(A)-D(C)) corresponding to a source video signal. The IC includes a line latch circuit (25, 26) for latching the video signals from the data latch circuit (22, 23) corresponding to the latch clock signal from a shift register (21). The IC includes a digital to analog converter (27, 28) for converting the video signal from the line latch (25, 26) to an analog signal. The IC further includes a data output circuit (29, 30) for outputting the analog signal. The frequency of the clock signal (SCL) is reduced by the number of sets of the three video signals as compared to the frequency of the source video signal.

Description

DRIVER FOR A LIOUID CRYSTAL DISPLAY The present invention relates to a driver, and more particularity, to a data driver for a liquid crystal display.

Referring to Fig. 1, a general active matrix liquid crystal display includes a lower substrate on which gate lines Gl-Gn, data lines Dl-Dn, a thin film transistor for switching pixels, and a pixel electrode are arranged. An upper substrate has a color filter for displaying colors and a common electrode. A liquid crystal panel 1 has a liquid crystal filled between the two upper and lower substrates, and a gate driver 2 sequentially applies driving signals to respective gate lines G1-Gn of liquid crystal panel 1. A data driver 3 applies video data to respective data lines Dl-Dn of liquid crystal panel 1.

In such a liquid crystal display, liquid crystal panel 1 is becoming larger and with higher resolution. In order to drive larger and higher-resolution liquid crystal displays, the driving frequency of respective drivers 2 and 3 becomes higher. However, it is difficult to develop a driver IC capable of directly driving such a high frequency. Even though the driver IC capable of directly driving the high frequency may be developed, direct driving is not feasible due to high-frequency EMI. For this reason, as shown in Fig. 2, a data driver is provided on both sides of liquid crystal panel 1 according to two separate even and odd lines so that the driving frequency is reduced by half.

In the liquid crystal display of Fig. 2, however, because the driver is formed on both sides, the area of the liquid crystal panel for displaying actual images becomes smaller in the overall liquid crystal display. This limits the obtaining of a large-sized screen. The data driver of the conventional liquid crystal display of Fig. 1 will be discussed with reference to Fig. 3.

The data driver of the conventional liquid crystal display includes an m-bit shift register 11 for shifting a source start pulse SSP by a source pulse clock SCL and outputting a latch clock. A data latch 12 latches and outputs three signals DA(n), DB(n), and DC(n) of display data by source clock SCL. A line conversion logic 14 converts the polarity for every horizontal period by an external POL signal for the purpose of inversion. A 3m-by-n-bit two-line latch 13 latches, by lines, all display data of one horizontal line output from data latch 12 by the latch clock output from shift register 11 according to an external load signal and the output of line conversion logic 14. A D/A converter 15 selects and outputs one voltage of 2" levels formed by an external reference voltage so as to convert the data output from line latch 13 into an analog signal to be applied to the liquid crystal. A data output circuit 16 amplifies the signal output from D/A converter 15 to a stable voltage having a sufficient driving capability and a less-deviation output voltage. The amplified signal is output to the liquid crystal.

The operation of the conventional data driver will be described below with reference to Fig. 4. First, shift register 11 receives source clock SCL and source start pulse SSP, and outputs m latch clocks SRO1, SR02, SR03, . . ., and SROm (m=64) sequentially to line Latch 13. Source clock SCL is a clock signal of about 65MHz in XGA.

Data latch 12 latches signals DA(n), DB(n), and DC(n) of the n-bit display data corresponding to the falling edge of source clock SCL, and outputs the latched result to line latch 13. Line latch 13 latches the n-bit display data latched to the falling edge of the source clock to 3m-by-n bit first line latch portion 13a by latch clocks SRO1, SR02, SR03, . . ., and SROm output from shift register 11. After one horizontal line of display data is stored, one line data is stored in second line latch portion 13b at one time by an external load signal LOAD. Simultaneously, the next line data is latched to first line latch portion 13a by latch clocks SRO1, SR02, SR03, . . ., and SROm output from shift register 11 in the same method as above. This operation is performed repeatedly.

The line data stored by line latch 13 is output to D/A converter 15. D/A converter 15 selects and outputs, from the 2" levels formed by an external reference voltage v Ep in an internal decoder, one voltage corresponding to the line data input from line latch 13. Here, line conversion logic 14 converts the polarity for every line by the external POt signal to facilitate the inversion.

The analog signal selected and output from D/A converter 15 is applied and displayed to the liquid crystal as a stable voltage having a sufficient driving capability and less-deviation output voltage. The conventional data driver, however, has the following drawbacks.

With the trend of larger screens and higher resolution, the hardest obstacle in the application of liquid crystal displays to liquid crystal laptop computers and their monitors is the operation frequency (65 MHz for XGA and 107MHz for EWS) in accordance with resolution. The operation frequency of the conventional IC data driver is 55MHz at 5V driving (40 MHz at 3.3V). Hence, the driver cannot be driven directly. Even when a directly drivable driver IC is developed, high frequency EMI is involved, making the direct driving impossible.

An external line memory may be provided in the conventional data driver in order to reduce frequency into half through bisected driving or driving by ICS. In this case, however, the cost as well as the weight of the product increase due to the line memory. Accordingly, power consumption and volume are also increased.

The present invention has been made in view of the above circumstances and has an object to overcome the problems and disadvantages of the prior art.

It is another object of the present invention to provide a data driver for a liquid crystal display in which the main driving frequency is reduced and overcomes problems caused due to operation at high frequency.

Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the data driver of the present invention includes a first signal generation circuit for externally producing a start signal; a second signal generation circuit for externally producing a first clock signal; a third signal generation circuit for externally producing a load signal; means for externally generating a source video signal having a frequency; and a single integrated circuit.

The single integrated circuit including an m-bit register circuit for receiving the start signal corresponding to the first clock signal and outputting a latch clock signal, where m is an integer; a data latch circuit for latching and outputting at least two sets of three video signals corresponding to the source video signal, the data latch circuit receiving all of the video signals simultaneously, each of the video signals having n-bits of data, where n is an integer; a line latch circuit for latching the video signals from the data latch circuit corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting the analog signal from the digital to analog converter, wherein a frequency of the first clock signal is reduced by the number of sets of the three video signals as compared to the frequency of the source video signal.

In another aspect of the present invention, a data driver for a liquid crystal display includes a first signal generation circuit for externally producing a source start signal; a second signal generation circuit for externally producing a first clock signal; a third signal generation circuit for externally producing a load signal; a fourth signal generation circuit for externally producing a polarity signal; and a single integrated circuit. The signal integrated circuit includes an m-bit register circuit for shifting the source start signal corresponding to the first clock signal and outputting a latch clock signal; a data latch circuit for latching and outputting at least two sets of three video signals, the data latch circuit receiving all of the video signals simultaneously, each set representing a pixel in the liquid crystal display, each of the video signals having n-bits of data, where n is an integer; a 3m x n line latch circuit for latching the video signals from the data latch corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a polarity inversion circuit for inverting a polarity of the video signals from the data latch; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting a signal from the digital to analog converter, wherein a driving frequency of the data driver is reduced by the number of sets of the three video signals.

In a further aspect of the present invention, a data driver for a liquid crystal display includes a first signal generation circuit for externally producing a source start signal; a second signal generation circuit for externally producing a first clock signal; a third signal generation circuit for externally producing a load signal; a fourth signal generation circuit for externally producing a polarity signal; and a single integrated circuit. The single integrated circuit includes a register circuit for shifting the source start signal corresponding to the first clock signal and outputting a sampling clock signal; a data sampling circuit for sampling and outputting at least two sets of three video signals, the data sampling circuit receiving all of the video signals simultaneously, each set representing a pixel in the liquid crystal display; a 3m x nline latch circuit for latching the video signals from the data latch corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a polarity inversion circuit for inverting a polarity of the video signals from the data latch; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting a signal from the digital to analog converter, wherein a driving frequency of the data driver is reduced by the number of sets of the three video signals.

For a better understanding of the invention, embodiments will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a liquid crystal display; Fig. 2 is a block diagram of a liquid crystal display having a double-driver; Fig. 3 is a block diagram of a data driver of a conventionalliquid crystal display; Fig. 4 is a timing diagram of the driver shown in Fig. 3; Fig. 5 is a block diagram of a first embodiment of data driver for a liquid crystal display according to the present invention; Fig. 6 is a block diagram of a second embodiment of a data driver for a liquid crystal display according to the present invention; and Fig. 7 is a timing diagram of the first embodiment of the data driver according to the present invention.

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

A data driver for a liquid crystal display includes an m-bit shift register for shifting a source start pulse by a source pulse clock, and outputting a latch clock. A plurality of data latches latch and output three signals of divided n-bit display data and N 3m-by-n-bit line latches latch all display data of one horizontal line output from the respective data latches by the latch clock output from the shift register and store and output the data according to an external load signal. A line conversion logic converts the polarity for every horizontal period by an external POL signal and N D/A converters convert the data output from the respective line latches to an analog signal. N data output circuits amplify the signal output from the respective D/A converters, and apply the amplified signal to liquid crystal.

Fig. 5 is a diagram of an IC structure of the first embodiment of the present invention in which data to be applied to the even and odd portions of a data line is divided and processed in parallel. Hence, the operation frequency of the data driver is reduced by one-half. Fig. 7 is an operation wave form thereof.

As shown in Fig. 5, an m-bit shift register 21 receives source clock SCL which is one-hal the operation frequency.

Latch pulses SRO1, SRo2, . . . of Fig. 7 are produced by the source clock and source start pulse SSP. Data divided into even and odd portions externally from the drive IC is latched in first and second data latches 22 and 23. Three signals of the n-bit odd data and three signals of the even data latched by first and second latches 22 and 23 are latched to 3m-by-n bit odd-line first latch 25a and even-line first latch 26a by the latch pulse of shift register 21.

One horizontal line of display data stored in first line latches 25a and 26a is stored in odd and even second line latches 25b and 26b at one time of the LOAD signal. At the same time, the next line data is sequentially latched to first line latches 25a and 26a by the latch pulse of the shift register 21. The line data stored in the odd and even second line latches 25b and 26b selects a corresponding voltage of two reference voltages by D/A converters 27 and 28. Here, line conversion logic 24 converts the voltage's polarity so as- to facilitate inversion.

The selected reference voltage is applied to liquid crystal as a stable voltage having a sufficient driving capability and less-deviation output voltage through data output circuits 29 and 30. In this embodiment, data may be stored in first and second latches 22 and 23 in the arriving sequence. The output ports of data output circuits 29 and 30 being connected to the data Line of the liquid crystal panel alternately by three.

Referring to Fig. 6, unlike the first embodiment in which data is divided into odd and even portions, the second embodiment has three data latches 32, 33, and 34. Data is divided in such a manner that the data of the first data line is applied to the first latch 32, the data of the second da-ta line is applied to the second latch 33, and the data of the third data line is applied to the third latch 34. The data of the fourth, fifth, and sixth data lines is applied to the first, second, and third latches. Shift register 31 applies one third the frequency of the case of nonparallel driving, thus reducing the operation frequency of the data drive IC by one-third. Other operations are similar to that of the first embodiment.

In the first and second embodiments, the data driver is attached only to one side of the liquid crystal panel. However, when this driver is formed in a double structure as shown in Fig.

2, the main driving frequency is further reduced by one-half.

Accordingly, a plurality of components of the conventional data driver are disposed in a single IC and operate in parallel, allowing the clock frequency to be reduced as compared with conventional circuits.

The data driver of the liquid crystal display described has the following advantages. The main driving frequency may be reduced by one-half or one-third in the driver itself, eliminating the need for an external memory and circuit. Therefore, the data driver is suitable for a module protected against high-frequency EMI, decreasing cost, weight, volume, and power consumption. Furthermore, XGA or EWS resolution can be obtained in a single or double structure in laptop computers or monitors.

The foregoing description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, and their equivalents.

Claims (26)

1. A data driver comprising: a first signal generation circuit for externally producing a start signal; a second signal generation circuit for externally producing a first clock signal; a third signal generation circuit for externally producing a load signal; means for externally generating a source video signal having a frequency; and a single integrated circuit including: an m-bit register circuit for receiving the start signal corresponding to the first clock signal and outputting a latch clock signal, where m is an integer; a data latch circuit for latching and outputting at least two sets of three video signals corresponding to the source video signal, the data latch circuit receiving all of the video signals simultaneously, each of the video signals having nbits of data, where n is an integer; a line latch circuit for latching the video signals from the data latch circuit corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting the analog signal from the digital to analog converter, where a frequency of the first clock signal is reduced by the number of sets of the three video signals as compared to a frequency of the source video signal.
2. A data driver according to claim 1, wherein the m-bit register circuit includes a shift register.
3. A data driver according to claim 1, further comprising: a fourth signal generation circuit for externally producing a polarity signal; and a polarity inversion circuit for inverting a polarity of the video signals from the data latch.
4. A data driver according to claim 3, wherein the m-bit shift register circuit, the data latch circuit, the line latch circuit, the digital to analog converter circuit, the data output circuit, and the polarity inversion circuit are included in a single integrated circuit.
5. A data driver according to claim 1, wherein at least two sets of the video signals correspond to first and second pixels.
6. A data driver according to claim 1, wherein the data latch circuit includes at least two data latches.
7. A data driver according to claim 1, wherein the line latch circuit includes at least two 3m x n line latches.
8. A data driver according to claim 1, wherein the digital to analog converter circuit includes at least two digital to analog converters.
9. A data driver according to claim 1, wherein the line latch circuits each include at least two line memories.
10. A data driver according to claim 1, wherein the data latch circuit includes at least three data latches each of the data latches latching and outputting three video signals, each of the video signals having n-bits of data, where n is an integer.
11. A data driver for a liquid crystal display comprising: a first signal generation circuit for externally producing a source start signal; a second signal generation circuit for externally producing a first clock signal; a third signal generation circuit for externally producing a load signal; a fourth signal generation circuit for externally producing a polarity signal; and a single integrated circuit including: an m-bit register circuit for shifting the source start signal corresponding to the first clock signal and outputting a latch clock signal; a data latch circuit for latching and outputting at least two sets of three video signals, the data latch circuit receiving all of the video signals simultaneously, each set representing a pixel in the liquid crystal display, each of the video signals having n-bits of data, where n is an integer; a 3m x n line latch circuit for latching the video signals from the data latch corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a polarity inversion circuit for inverting a polarity of the video signals from the data latch; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting a signal from the digital to analog converter, wherein a driving frequency of the data driver is reduced by the number of sets of the three video signals.
12. A data driver according to claim 11, wherein the n-bit video signal is divided into odd and even bits.
13. A data driver according to claim 11, wherein the data latch circuit includes at least two data latches.
14. A data driver according to claim 11, wherein the line latch circuit includes at least two 3m x n line latches.
15. A data driver according to claim 11, wherein the digital to analog converter circuit includes at least two digital to analog converters.
16. A data driver according to claim 11, wherein the line latch circuits each includes at least two line memories.
17. A driver according to claim 11, wherein the data latch circuit includes three data latches, each of the data latches latching and outputting three video signals, each of the video signals having n-bits of data, where n is an integer.
18. A data driver according to claim 11, further including a second data driver, the two data drivers driving the liquid crystal display further reduce the driving frequency by two.
19. A data driver according to claim 11, wherein the three video signals represent R, G, and B values for each pixel.
20. A data driver for a liquid crystal display comprising: a first signal generation circuit for externally producing a source start signal; a second signal generation circuit for externally producing a first clock signal; a third signal generation circuit for externally producing a load signal; a fourth signal generation circuit for externally producing a polarity signal; and a single integrated circuit including: a register circuit for shifting the source start signal corresponding to the first clock signal and outputting a sampling clock signal; a data sampling circuit for sampling and outputting at least two sets of three video signals, the data sampling circuit receiving all of the video signals simultaneously, each set representing a pixel in the liquid crystal display; a 3m x n line latch circuit for latching the video signals from the data latch corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a polarity inversion circuit for inverting a polarity of the video signals from the data latch; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting a signal from the digital to analog converter, wherein a driving frequency of the data driver is reduced by the number of sets of the three video signals.
21. A driver for a display, the driver comprising means for receiving data to be represented on the display and for arranging simultaneously a plurality of parts of the data into a form for application to the display, and means for applying the arranged data to the lines of the display, the data being applied to each of the lines at the same end thereof.
22. A driver for a display, the driver comprising means for receiving data to be represented on the display and for arranging simultaneously a plurality of parts of the data into a form for application to the display, the said means being implemented on a single integrated circuit.
23. A driver substantially as hereinbefore described with reference to and/or as illustrated in any one of or any combination of Figs. 5 to 7 of the accompanying drawings.
24. A method for driving a display, the method comprising arranging simultaneously a plurality of parts of data to be represented on the display into a form for application to the display, and applying the arranged data to the lines of the display, the data being applied to each of the lines at the same end thereof.
25. A method of driving a display substantially as hereinbefore described with reference to and/or as illustrated in any one of or any combination of Figs. 5 to 7 of the accompanying drawings.
26. A liquid crystal display comprising the driver as claimed in any one of claims 1 to 23, or operated according to the method of claims 24 or 25.
GB9623401A 1996-11-08 1996-11-08 Driver for a liquid crystal display Expired - Lifetime GB2319131B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9623401A GB2319131B (en) 1996-11-08 1996-11-08 Driver for a liquid crystal display
FR9613770A FR2755786B1 (en) 1996-11-08 1996-11-12 A driving device for a display device
DE1996147367 DE19647367B4 (en) 1996-11-08 1996-11-15 Data driver for a liquid crystal display

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9623401A GB2319131B (en) 1996-11-08 1996-11-08 Driver for a liquid crystal display
FR9613770A FR2755786B1 (en) 1996-11-08 1996-11-12 A driving device for a display device
DE1996147367 DE19647367B4 (en) 1996-11-08 1996-11-15 Data driver for a liquid crystal display

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Publication Number Publication Date
GB9623401D0 true GB9623401D0 (en) 1997-01-08
GB2319131A true true GB2319131A (en) 1998-05-13
GB2319131B GB2319131B (en) 1998-12-23

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DE (1) DE19647367B4 (en)
FR (1) FR2755786B1 (en)
GB (1) GB2319131B (en)

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US4965566A (en) * 1987-11-30 1990-10-23 Casio Computer Co., Ltd. Signal electrode drive circuit for image display apparatus operable under low frequency

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JPS6337394A (en) * 1986-08-01 1988-02-18 Hitachi Ltd Matrix display device
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GB2205191A (en) * 1987-05-29 1988-11-30 Philips Electronic Associated Active matrix display system
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JPH02245793A (en) * 1989-03-20 1990-10-01 Hitachi Ltd Matrix display device
DE69020036T2 (en) * 1989-04-04 1996-02-15 Sharp Kk Drive circuit for a matrix display device with liquid crystals.
JP3582082B2 (en) * 1992-07-07 2004-10-27 セイコーエプソン株式会社 Matrix display device, a matrix type display control device and matrix display driving apparatus
JP2626595B2 (en) * 1994-11-17 1997-07-02 日本電気株式会社 Active matrix liquid crystal display-integrated type tablet and a driving method
JPH08278769A (en) * 1995-04-05 1996-10-22 Citizen Watch Co Ltd Microcomputer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4447812A (en) * 1981-06-04 1984-05-08 Sony Corporation Liquid crystal matrix display device
US4745485A (en) * 1985-01-28 1988-05-17 Sanyo Electric Co., Ltd Picture display device
EP0261901A2 (en) * 1986-09-20 1988-03-30 THORN EMI plc Display device
US4965566A (en) * 1987-11-30 1990-10-23 Casio Computer Co., Ltd. Signal electrode drive circuit for image display apparatus operable under low frequency

Also Published As

Publication number Publication date Type
DE19647367A1 (en) 1998-05-28 application
GB2319131B (en) 1998-12-23 grant
FR2755786B1 (en) 1999-01-08 grant
GB9623401D0 (en) 1997-01-08 application
FR2755786A1 (en) 1998-05-15 application
DE19647367B4 (en) 2010-10-21 grant

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