GB2315377A - Power-on reset circuit using a bistable and an EXOR gate - Google Patents

Power-on reset circuit using a bistable and an EXOR gate Download PDF

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Publication number
GB2315377A
GB2315377A GB9713797A GB9713797A GB2315377A GB 2315377 A GB2315377 A GB 2315377A GB 9713797 A GB9713797 A GB 9713797A GB 9713797 A GB9713797 A GB 9713797A GB 2315377 A GB2315377 A GB 2315377A
Authority
GB
United Kingdom
Prior art keywords
flip
power
circuit
flop
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9713797A
Other versions
GB9713797D0 (en
Inventor
Gert Teutsch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Semiconductors Ltd
Original Assignee
Plessey Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB9614799.6A external-priority patent/GB9614799D0/en
Application filed by Plessey Semiconductors Ltd filed Critical Plessey Semiconductors Ltd
Priority to GB9713797A priority Critical patent/GB2315377A/en
Publication of GB9713797D0 publication Critical patent/GB9713797D0/en
Publication of GB2315377A publication Critical patent/GB2315377A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Abstract

In an IC incorporating flip-flops, one of the flip-flops 3 is dedicated to provision of a power-on reset (POR) signal. The Q and Q bar flip-flop outputs are coupled to an EXOR gate 6, such that on power-up, as soon as the flip-flop 3 is energised sufficiently to take up one or other state, the EXOR gate disables transistor 7. This allows capacitor 8 to charge up, actuating Schmitt trigger circuit 10. The R and S flip-flop inputs are both tied to a potential which is one diode drop 4 below the supply potential 2, so that the flip-flop 3 tends not to latch until the supply voltage 2 is higher than that needed for the other flip-flops in the IC.

Description

Power-on Reset Circuit The present invention relates to power-on reset circuits.
Very often in digital integrated circuits a power-on reset signal is required to establish a defined logic state at power-on. This is particularly so in integrated circuits incorporating flip-flops, which would otherwise latch in an unpredictable state. The reset signal may be derived from circuitry outside the integrated circuit or from a special reset circuit built in to the integrated circuit.
Known reset circuits make use of comparators and voltage reference sources to determine when the supply voltage is high enough for flip-flops to set or reset reliably. For application specific integrated circuits or for gate arrays the required reference voltage sources are not generally available.
In accordance with one aspect of the present invention a power-on reset circuit for an integrated circuit comprises a sensor flip-flop and exclusive OR gating means arranged to initiate a reset signal when the potentials at the outputs of the sensor flip-flop diverge.
In accordance with another aspect of the present invention a power-on reset circuit for an integrated circuit incorporating a plurality of flip-flops comprises a sensor flip-flop formed in said integrated circuit and having two inputs and two outputs, the two outputs being connected to respective inputs of exclusive OR gating means arranged to initiate a reset signal when the potentials at the outputs of said sensor flip-flop diverge.
Preferably the two inputs of said sensor flip-flop are connected together and to an intermediate point in a potential divider path connected between supply lines of said integrated circuit.
A power-on reset circuit in accordance with the present invention will now be described by way of example with reference to the accompanying drawing, which shows the circuit schematically.
Referring to the drawing, in an integrated circuit incorporating a plurality of flip-flops (not shown) which are energised by way of supply lines 1 and 2, a sensor flip-flop 3, which may be of the same basic structure as the plurality of flip-flops and which is energised from the supply lines 1 and 2, has its R and S inputs connected together and to an intermediate point in a potential divider path comprising a diode 4 and a current source 5.
The Q and Q bar outputs of the flip-flop 3 are connected to the inputs of an exclusive OR gate 6, the output of this gate being connected to the gate electrode of a field effect transistor 7 whose source-drain path is connected across a capacitor 8. The capacitor 8 is connected in series with a current source 9 between supply lines 1 and 2, the node between the capacitor 8 and the current source 9 being connected to an input of a Schmitt trigger circuit 10.
While the integrated circuit is unpowered the outputs of the flip-flop 3 are both at effectively zero volts. As the potential difference between the supply lines 1 and 2 increases at power-on a point is reached where the difference is sufficient for the flip-flops in the integrated circuit to operate, although with its inputs both connected to the potential divider, and therefore at the diode voltage below VDD, the flip-flop 3 tends not to latch until the supply voltage is higher than that needed for the other flip-flops.
When the flip-flop 3 latches its outputs diverge in potential and the exclusive OR circuit 6 operates to bias off the transistor 7, thereby allowing the capacitor 8 to charge by way of the current source 9. While the capacitor 8 is charging the Schmitt trigger circuit 10 provides an output pulse to reset the integrated circuit.
Since the sensor flip-flop 3 is part of the integrated circuit the working threshold for the power-on reset autornatically adapts to variations of operating temperature or chip technology parameters.

Claims (6)

Claims
1. A power-on reset circuit for an integrated circuit, comprising a sensor flipflop and exclusive OR gating means arranged to initiate a reset signal when the potentials at the outputs of the sensor flip-flop diverge.
2. A power-on reset circuit for an integrated circuit incorporating a plurality of flip-flops, comprising a sensor flip-flop formed in said integrated circuit and having two inputs and two outputs, the two outputs being connected to respective inputs of exclusive OR gating means arranged to initiate a reset signal when the potentials at the outputs of said sensor flip-flop diverge.
3. A power-on reset circuit in accordance with Claim 2 wherein the two inputs of said sensor flip-flop are connected together and to an intermediate point in a potential divider path connected between supply lines of said integrated circuit.
4. A power-on reset circuit in accordance with any preceding claim wherein an output of said exclusive OR gating means is arranged to enable a trigger circuit to generate said reset signal.
5. A power-on reset circuit in accordance with Claim 4 wherein the trigger circuit is a Schmitt trigger circuit operable to provide said reset signal while a capacitor charges towards a supply voltage for the circuit, said output of said exclusive OR gating means being arranged to bias off a transistor switch means connected in parallel with said capacitor.
6. A power-on reset circuit substantially as hereinbefore described with reference to the accompanying drawing.
GB9713797A 1996-07-13 1997-06-30 Power-on reset circuit using a bistable and an EXOR gate Withdrawn GB2315377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9713797A GB2315377A (en) 1996-07-13 1997-06-30 Power-on reset circuit using a bistable and an EXOR gate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9614799.6A GB9614799D0 (en) 1996-07-13 1996-07-13 Power-on reset circuit
GB9713797A GB2315377A (en) 1996-07-13 1997-06-30 Power-on reset circuit using a bistable and an EXOR gate

Publications (2)

Publication Number Publication Date
GB9713797D0 GB9713797D0 (en) 1997-09-03
GB2315377A true GB2315377A (en) 1998-01-28

Family

ID=26309697

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9713797A Withdrawn GB2315377A (en) 1996-07-13 1997-06-30 Power-on reset circuit using a bistable and an EXOR gate

Country Status (1)

Country Link
GB (1) GB2315377A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166545A (en) * 1991-07-10 1992-11-24 Dallas Semiconductor Corporation Power-on-reset circuit including integration capacitor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166545A (en) * 1991-07-10 1992-11-24 Dallas Semiconductor Corporation Power-on-reset circuit including integration capacitor

Also Published As

Publication number Publication date
GB9713797D0 (en) 1997-09-03

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)