GB2297221A - Switching arrangement capable of carrying both ATM and CBR traffic - Google Patents

Abstract

A modified ATM format having a plurality of cells, each cell having a predetermined number of segments, each segment having an equal predetermined number of data bytes provides a universal transport and switching arrangement able to carry both ATM cells and Constant Bit Rate traffic. The Constant Bit Rate traffic does not incur the extent of the delay nor the delay variation associated with ordinary ATM. A switch would provide a predetermined timeslot for the modified format traffic.

Description

ASYNCHRONOUS AND PLESIOCHRONOUS TRANSFER MODE TRAFFIC The present invention relates to transformations of the current Asynchronous Transfer Mode (ATM) cell structure and will be referred to as ATM-T.

ATM-T is a universal transport and switching arrangement that is able to carry both ATM cells and constant bit rate traffic. The constant bit rate traffic does not incur anything like the delay and none of the delay variation associated with using ordinary ATM to carry constant bit rate traffic.

6 segment and 9 segment transforms are described, but only one size of segment should be employed.

ATM-T is suitable for main networks and access networks.

Only the principles behind the transforms are described and not how ATM-T can be applied to access networks. However, the use of ATM-T would significantly simplify access proposals because ATM-T is intended to be directly compatible with Time Division Multiple Access (TDMA) and Sub-Carrier Multiplex (SCM) techniques at both high and low subscriber access bit rates. ATM-T is also expected to be suitable for the grooming and consolidation functions associated with access networks. In order to help access applications provision has been made, within the 160 kbit/s basic format for an additional associated outbound supervisory/signalling capability over and above the minimum 144 kbit/s 2B channels plus one D channel (2B+D) and is referred to as the 'dd' channel later.

ATM-T is a compromise and as a result the performance when carrying pure ATM traffic will not be quite as efficient (98%) as ordinary ATM and there can be 2 ms of added transform delay converting ATM-T to ordinary ATM.

The delay of 64 kbit/s circuits will be a little higher than a dedicated 64 kbit/s switch.

The delay of 2048 kbit/s circuits will be a little higher than an SDH crossconnect.

However the constant bit rate traffic will be carried with a defined delay and no significant delay variation.

It is preferable to operate totally using one of the transform segment sizes described, but conversion to ordinary ATM for interfacing to ordinary ATM networks is straight forward.

According to the present invention there is provided a time division multiplex and switch arrangement to carry both asynchronous traffic and Constant Bit Rate (CBR) traffic using a plurality of cell streams wherein each cell has a format having a predetermined number of segments each segment having an equal and predetermined number of data bytes each subsequent segment of a cell being transmitted an equal and predetermined time after a former segment whereby CBR traffic incurs a constant switching delay when traversing a switch which provides a predetermined segmented cell transfer function.

There is further provided a time division multiplex format wherein the traffic is carried within segmented cells.

The present invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows the format of a transformed six segment asynchronous cell; Figure 2 shows the format of a Constant Bit Rate 160 kbit/s transformed six segment cell; Figure 3 shows the format of a transformed nine segment asynchronous cell; and Figure 4 shows the format of a Constant Bit Rate 160 kbit/s transformed nine segment cell.

The concept is based on three principles.

1) Considering existing packet switches and constant bit rate circuit switches, it is possible to design a switch which in addition to packet switching takes a defined regularly positioned stream of packets from an input port and copies them to a similarly defined regularly positioned stream of packets on an output port.

2) If a stream of packets contains a suitable justification scheme, then a rejustification function would be able to rejustify the stream of packets so that they arrive at the switch at a rate which is fully synchronous to the switch. This will require the definition of a new ATM Adaption Layer (AAL).

3) Because the normal way of defining a packet is for the packet to consist of so many bytes which are transmitted as consecutive bytes, there can be considerable packetisation and depacketisation delays as well as rejustification and switching delays.

A solution is not to send the cells as consecutive bytes, but to send them as several linked sets over a defined period of time, or as regularly spaced individual bytes over a defined period of time. The number of bytes and the period of time would be arranged to correspond naturally to a particular data rate.

Transforming the fixed length packets into distributed packets would affect the switches.

The switches as mentioned in 1 above would be required to work with transformed packets (and not consecutive byte packets), similarly the rejustification functions as mentioned in 2 above would also be required to work with transformed packets (and not consecutive byte packets which would have incurred a heavy rejustification delay).

Possible transform formats as in 3 above are arranged to carry a minimum of 2B+D and to have a practical repeat loop. 2B+D being the basic access of Integrated Services Digital Network (ISDN) where a B channel is 64 kbit/s full duplex and a D channel 16 kbit/s full duplex. The B channel is normally an information or voice channel and the D channel is used for common channel signalling, low speed telemetry or packet switching.

A normal ATM cell is 53 bytes long, this does not make division very easy so this transform works on a 54 byte format.

Whereas for 53 bytes per cell ATM there are 2340 cells in a 53 frame loop, for the transformed format (54 bytes) there are 780 cells in an 18 frame loop (which equals 2340 cells over a 54 frame loop).

It is assumed that each cell will be carried as 6 segments each of 9 bytes (or 9 segments of 6 bytes).

The possible formats are shown in the figures.

A cell segment is sent every 3 frames for the 6 segment transform (2 frames for 9 segment transform).

A constant bit rate transformed cell carries 45 bytes of useful payload over 18 frames (a period of 2.25 ms), which equates to 45 x 8/0.00225 kbit/s namely 160 kbit/s.

For the 6 segment transform, the first segment of a cell is controlled and the other 5 segments follow the same path 3, 6, 9, 12 and 15 frames later. This would be used for regular rate cells and asynchronous cells. (For the 9 segment transforms; 2, 4, 6, 8, 10, 12, 14 and 16 frames later).

For the 6 segment transform, cell control normally only has to run every sixth segment but this reduces to 5 once every 3 frames, except once every 18 frames when it changes to 11.

(For the 9 segment transform, every 9th segment reduces to 8 once every 2 frames and up to 17 once every 18 frames).

For the 6 segment transform, 160 kbit/s (2B+D +dd) requires 7/8 bytes per alternate segment (a regular 5 bytes for the 9 segment transform). The header is carried as 1 byte per segment for 5 segments. The first byte of the first segment is used to indicate constant bit rate or asynchronous. Distributing the header is only done for the constant bit rate cells as the header is not needed for cell switching and is only used for checking purposes.

Because the arrival rate has been made fairly regular (very regular for the 9 segment transform), the rejustification delay (which should be a constant) should only be a certain amount longer than the segment time of 375 ps (250 is for 9 segment).

The average one way switching delay (per time switching stage) is 1.5 frames (187.5 ;is) for the 6 segment transform (1.0 frames for the 9 segment transform).

Applying 3) above to ATM cells by distributing them over a 18 frame period would help 64 kbit/s traffic, but it would have some consequences: a) A high data rate application will incur delay as it will have data to fill a cell. but it will take 2 ms before the cell has been completely launched. If this is really unacceptable for constant high bit rate traffic or for long asynchronous transfers, new cells would be being started before old cells were completed. Consequently it should be possible (in particular for the constant high bit rate traffic) to spread the data into the next outgoing byte regardless of which cell it was carried by. However, in order for the receiving end to interpret the data, a defined spreading algorithm should be used.The 2048 kbit/s delay figures in the Appendix are based on this spreading principle: b) Distributing the cells into segments should spread the effect of burst errors into several cells. This could improve the effectiveness of any forward error correction.

Considering 160 kbit/s rejustification (described for 6 segment transform); For a bit rate of 160 kbit/s one byte should occur every 50 lls.

A segment will arrive every 375 ,us with 7 or 8 useful data bytes.

For a simple explanation it is assumed that the fixed rejustifier delay is 4 Frames (500 pus). The difference in phase between a cell segment arriving and the time a cell segment is required for the switch can be in the range of 0 to 3 frames. Because sometimes 8 bytes may be required but only 7 arrived (or vice versa) the delay has to be more than 3 frames and 4 flames has been assumed.

When there is a phase change between a cell segment arriving and the switch timing reference, byte justifications are required for each 50Cls of phase change.

The justification control byte carries 1 bit marking every fifth cell, up to 3 bits of a timing indicator (part of a timing indicator), up to 2 bits of the pointer, as well as a pair of justification control bits. Over 5 cells (90 frames) the justification control is majority voted, to determine if a justification action has been signalled, in which case either the JUST-OPP byte is regarded as being valid or the DATA 23 byte is regarded as being invalid.

Considering 2048 kbit/s rejustification, 13 parallel Constant Bit Rate 160 kbit/s Transform Cell Circuits are required to provide the capacity to carry a 2048 kbitls link. If they are treated as 13 separate circuits then the delays incurred will correspond to those quoted below for single circuits. If the 13 circuits are operated as a group then the delays can be reduced.

12 circuits of the group would each carry 160 kbit/s without any active justification. The 13th circuit would only carry 128 kbit/s (by not using data bytes 05, 10, 15, 20, 25, 30, 35, 40 and 45) and the justification mechanism would be used. A single justification mechanism has plenty of range for a 2048 kbit/s link. The rejustification functions will have to be able to operate as group rejustification functions Pre-defined Multislot groups can also enable the switching delay to be reduced. A list of predicted delays for both 6 and 9 segment transforms can be found in the appendix.

The present invention provides a Universal Transport with defined fixed delay characteristics with effectively no delay variation. The use of the ATM Transforms allows an acceptable delay performance to be specified for general networks as well as for access networks. The choice between the 6 and 9 segment transforms is based on delay, memory usage, complexity and the advantage for TDMA systems to use longer segments. The present invention enables asynchronous and plesiochronous traffic to be transported and switched using synchronous based techniques.

APPENDIX PREDICTED DELAYS USING ATM TRANSFORM 6 9 Segment Segment ATM Combined one way Conversion and Reconversion Delay from ordinary ATM cell into Transformed Asynchronous Cell and back to ordinary ATM cell 2 ms 2 ms 160 kbit/s Combined one way Packetisation and Depacketisation Delay from 64 kbit/s into Constant Bit Rate 160 kbit/s transform cell and back to 64 kbit/s including desynchronisation 500 s 300 s Rejustification delay 500 ps 300 Two way time switching delay 375 IlS 250 lls Average one way time switching delay 188 s 125is 2048 kbit/s Combined one way Packetisation and Depacketisation Delay from 2048 kbit/s into a defined group of 13 Constant Bit Rate 160 kbit/s transform cells and back to 2048 kbit/s including desynchronisation 40 ,us 30ts Rejustification delay 40 s 30is Two way time switching delay 40 s 30 pis Average one way time switching delay 20 ps 15 tis

Claims (25)

1. CLAIMS 1. A time division multiplex and switch arrangement to carry both asynchronous traffic and Constant Bit Rate (CBR) traffic using a plurality of cell streams wherein each cell has a format having a predetermined number of segments each segment having an equal and predetermined number of data bytes each subsequent segment of a cell being transmitted an equal and predetermned time after a former segment whereby CBR traffic incurs a constant switching delay when traversing a switch which provides a predetermined segmented cell transfer function.
2. 2. An arrangement as claimed in Claim 1 wherein the CBR traffic is carried within the segmented cells in a justified form and wherein the switch has a corresponding input rejustification function for the CBR traffic.
3. 3. An arrangement as claimed in Claim 1 or 2, where the cell formats are transformations of the standard ATM cell formats.
4. 4. An arrangement as claimed in Claim 1, 2 or 3, wherein the predetermined number of segments is six and the predetermined number of bytes is nine.
5. 5. An arrangement as claimed in Claim 1, 2 or 3, wherein the period between cell segments is 375 microseconds.
6. 6. An arrangement as claimed in Claim 1, 2 or 3, wherein the predetermined number of segments is nine and the predetermined number of bytes is six.
7. 7. An arrangement as claimed in Claim 6, wherein the period between cell segments is 250 microseconds.
8. 8. An arrangement as claimed in any preceding claim, wherein the CBR traffic consists of a data stream carried by a combination of segmented cell streams.
9. 9. An arrangement as claimed in Claim 1,2,3,4,5,6 or7, wherein the CBR traffic consists of a data stream carried by a combination of segmented cell streams.
10. 10. An arrangement as claimed in Claim 1,2,3,4,5,6 or 7, wherein the CBR traffic consists of a data stream of 2048 kbit/s carried by a combination of 13 segmented cell streams.
11. 11. A time division multiplex format wherein the traffic is carried within segmented cells.
12. 12. A format as claimed in Claim 11, wherein asynchronous traffic is carried within segmented cells with a cell header carried in the first segment of each cell.
13. 13. A format as claimed in Claim 11, wherein the CB R traffic is carried within segmented cells in ajustified form.
14. 14. A format as claimed in Claim 13, wherein a cell header is spread across several of the cell segments.
15. 15. A format as claimed in Claim 11, wherein the standard ATM cell format is carried in segments with the addition of one extra byte.
16. 16. A format as claimed in Claim 11 or 12, wherein the first byte of the first cell segment is used to indicate whether CBR or asynchronous traffic is being transported.
17. 17. A format as claimed in Claim 11 or 12, wherein the predetermined number of segments is six and the predetermined number of bytes is nine.
18. 18. A format as claimed in Claim 17 wherein the period between cell segments is 375 microseconds.
19. 19. A format as claimed in Claim 11, 12, 13, 14, 15 or 16, wherein the predetermined number of segments is nine and the predetermined number of bytes is six.
20. 20. A format as claimed in Claim 19, wherein the period between cell segments is 250 microseconds.
21. 21. A format as claimed in Claim 11, 13, 14, 16, 17, 18, 19 or 20, wherein the CBR traffic consists of a data stream of 160 kbit/s carried within a single segmented cell stream.
22. 22. A format as claimed in Claim 11, 13, 14, 16, 17, 18, 19 or 20, wherein the CBR traffic consists of a data stream carried by a combination of segmented cell streams.
23. 23. A format as claimed in Claim 11, 13, 14, 16, 17, 18, 19 or 20, wherein the CBR traffic consists of a data stream of 2048 kbit/s carried by a combination of 13 segmented cell streams.
24. 24. A time division multiplex and switch arrangement substantially as hereinbefore described with reference to and illustrated in the accompanying drawings.
25. 25. A time division multiplex format substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.