GB2295061A

GB2295061A - Circuit for charging and discharging storage capacitors of a power supply

Info

Publication number: GB2295061A
Application number: GB9522629A
Authority: GB
Inventors: Franz-Juergen Riewe
Original assignee: Honeywell GmbH
Current assignee: Honeywell GmbH
Priority date: 1994-11-12
Filing date: 1995-11-06
Publication date: 1996-05-15
Anticipated expiration: 2015-11-06
Also published as: FR2727536A1; GB2295061B; DE4440529A1; GB9522629D0; DE4440529C2

Description

CIRCUIT DEVICE FOR CHARGING AND DISCHARGING STORAGE CAPACITORS 2295061 The

present invention relates to a circuit device according to the preamble of claim 1.

Memory flip-flops, in particular in C-MOS technique, as they are used with micro computers and memory circuits, show the behavior that they partly retain their latest status in the event where the operational voltage is reduced far below their operating range so that at resumption of the operational voltage the old data remains partly present. The supply current is not proportionally reduced at the switching-off of the operational voltage. For instance with a micro computer the current will be drastically reduced at the failure of the clock oscillator in order to fa far below the residual currents of the memory capacitors with a value in the range of current-conducting diodes. Due to the remaining residual voltage, reset circuits are not able to function properly at si&ritching-on and switching-off and malfunctions may appear in the according system or apparatus, respectively.

Normally, those problems may be solved in a simple manner by ohmic loads which may be inserted or are present anyway. However, ohmic loads are current-utilization devices which are undesired in apparatus operated by batteries. In particular in the event where due to the operation condition large storage capacitors are required a quick and thorough discharge of the storage capacitors at switching-off must be attained by other appropriate means without burdening the operational voltage in case of operation.

The present invention provides a circuit device for charging and discharging of storage capacitors providing a supply voltage for electronic components as e.g. micro computers, characterized by a selfconducting MOS field effect transistor. connected in parallel to each of said storage capacitors and by circuit means for generating an inhibiting voltage for the selfconducting MOS field effect transistor when the circuit is operated and the operational voltage (U13) is present.

Further advantageous embodiments of the inventive circuit device may be taken from the dependent claims.

1 78100818 GB The solution of the problem is achieved by means of an electronic discharge circuit which automatically implements the discharge of the storage capacitor in the event where the operating voltage falls below a certain value. For this purpose self-conducting MOS-field effect transistors of the depletion type are particularly appropriate which ' show the conducting state without any control voltage and therefor can implement the discharge when the control voltage is lacking. During the normal operation of the circuit device when the operational voltage is present, an inhibiting voltage is applied to the self- conducting MOS-field effect transistors (FET's).

is With respect to the sole figure of the attached drawing in the following an embodiment of the inventive circuit device shall be described.

The shown circuit device serves to provide two voltages UI and U2 which are tapped over two storage capacitors Cl and C2. To the storage capacitor CI a discharge circuit is connected in parallel which consists of the series connection of a resistor R4 and a selfconducting MOS-FET TI and to the storage capacitor C2 a discharge circuit is connected in parallel which consists of the series connection of a resistor R5 and a self-conducting MOS-FET T2.

Whereas the charging voltage of the storage capacitor Cl is derived directly from the battery voltage UB and is supplied via an electronic switch ES, the charging voltage of the storage capacitor C2 is applied via a switching controller SR before it is applied to the storage capacitor C2.

The switching-on procedure of the circuit device is as follows:

Via a switch S the battery voltage UB is connected and is applied via a self-wiping contact S2 and a diode D3 to a capacitor C6. By charging of the capacitor C6, the electronic switch ES is closed so that a charging current is applied to the storage capacitor Cl. During charging of the 30 storage capacitor Cl, firstly a discharging current is flowing via the resistor R4 and the MOS-FET TI. Due to the operation of the switching controller SR, a capacitor C4, however, is charged with a negative voltage via a charging pump circuit consisting of a capacitor C3 and of two diodes DI and D2. Since both MOS-FET's TI and T2 are connected to the capacitor 2 78100818 GB C4, those MOS-FET's are inhibited. Therefore, also the storage capacitor C2 is charged, and the supply voltage U2 is made available. A micro computer pC with the supply voltage U2 being present delivers permanently at its output P2 a signal which is applied via a capacitor CS to a hold circuit HK which keeps the capacitor C6 via a diode D4 in its charged condition and 5 therefore delivers the hold voltage for the electronic switch ES.

The switching-off procedure of the circuit device is as follows:

By opening the switch S the circuit device is separated from the operational voltage U13 so that the storage capacitor C1 also is not further charged. At a certain value which is adjusted by the voltage divider Rl, R2, a voltage breakdown is signalled to the micro computer, whereupon it finishes its program and suspends the signals to the hold circuit HK at its output P2, where upon the electronic switch ES is opened. At a further decrease of the voltage the switching controller SR does not further receive an enable signal via the voltage divider R6, R7 so that it suspends its function. Therefore, also the charging pump circuit C3, D I and D2 is not further in operation and the capacitor C4 is discharged via the resistor R3 connected in parallel. Due to the discharge of the capacitor C4, an inhibiting potential is not further present at the control electrode of the self-conducting MOS-FET's T I and T2 so that those transistors take the conducting state and discharge completely the storage capacitors C I and C2, whereat the discharge current is limited by means of the resistors R4 and R5 connected in series. By means of the self-conducting MOS-FET's TI and T2 the supply voltage lines UI and U2 are protected against external voltages and their harmful influences, and also with a momentary regeneration of the operational voltage a safe reset function is guaranteed. The switching-off procedure also may be released when the voltage falls below the minimum voltage of the battery UB or by means of the micro computer at the end of the program.

The hold circuit may be operated by means of a timing program, whereat after expiration of a pre-programmed time the micro computer pC via its output.P2 also suspends the signals to the hold circuit HK, whereupon the electronic switch ES is opened. In this event a discharge circuit (shown in dotted lines) for the battery voltage UB may be activated for safety relevant applications with the discharge circuit being connected in parallel to the battery UB and consisting of the series connection of a self- conducting MOS-FET T3 and a resistor R8. The control electrode of the MOS- FET T3 also is connected to the capacitor C4.

3 78100818 GB It is obvious for a man skilled in the art that the present invention also is applicable at the generation of voltages of different polarity. Storage capacitors which store a voltage with opposite polarity may be charged and discharged in the same way, whereat, however, the capacitors controlled by the MOS-FET's must be charged via a separate charging pump circuit with an opposite voltage. For voltages of one polarity one control capacitor for providing the inhibiting voltage at the control electrode of each of the MOS-FET's is sufficient.

4

Claims

78100818 GB 1. Circuit device for charging and discharging of storage capacitors providing a supply voltage for electronic components as e.g. micro computers, c h a r a c t c r i ze d b y a 5 self-conducting MOS field effect transistor (TI, T2) connected in parallel to each of said storage capacitors (C 1, C2) and by circuit means (S1; C3, D 1, D2, R3, C4) for generating an inhibiting voltage for the self-conducting MOS field effect transistor (TI, T2) when the circuit is operated and the operational voltage (UB) is present.
2. Circuit device according to claim 1, c h a r a c t e r i z e d b y a switching controller (SR) which charges a control capacitor (C4) via a charging pump circuit (C3, DI, D2) with the control capacitor being connected to the control electrode of each of said MOS field effect transistor (TI, T2).

is
3. Circuit device according to claim 2, c h a r a c t e r i z e d i n t h a t a resistor (R3) is connected in parallel to the control capacitor (C4).
4. Circuit device according to claim 2 or 3, c h a r a c t e r i z c d i n t h a t the switching controller (SR) is supplied with the operational voltage (UB) via an electronic 20 switch (ES).
5. Circuit device according to claim 4, c h a r a c t c r i z c d b y a first storage capacitor (Cl) which is connected to the output of the electronic switch (ES) and a second storage capacitor (C2) which is connected to the output of the switching controller (SR).
6. Circuit device according to claim 5, c h a r a c t e r i z e d i n t h a t the electronic switch (ES) initially is actuated via an auxiliary circuit (S2, D3, C6) when the operational voltage (UB) is supplied and that the actuation of the electronic switch (ES) is maintained via a hold circuit (HK), whereat the hold circuit is actuated by a micro computer (VC) 30 when the switching controller is operated and the supply voltage (U2) is applied to the micro computer via the second storage capacitor (C2).

78100818 GB
7. Circuit device according to claim 6, characterized in that two voltage dividers (RI, R2; R6, R7) are connected in parallel to the first storage capacitor (CI), whereat the first voltage divider (RI, R2) signals to the micro computer (PC) a voltage breakdown via the switching controller (SR), whereupon it interrupts its program and actuates the hold circuit (HK) in order to open the electronic switch (ES) and whereat the second voltage divider (R6, R7) is inhibiting the switching controller (SR) at a further lowering of the voltage (U I).

c
8. Circuit device according to any preceding Claim, c h a r a c t c r i z e d i n t h a t the self-conducting MOS field effect transistor (TI, D2) contains in its drain circuit a series- connected resistor (R4, R5) for limiting the discharge current of the storage capacitors (C I, C2).
9. Circuit device according to any one of claims 1 to 8, c h a r a c t c r i z e d b y a discharge circuit (T3, R8) comprising a further selfconducting MOS field effect transistor (T3) and being connected in parallel to a battery providing the operational voltage (UB).

is
10. Circuit device according to claim 9, c h a r a c t c r i z e d i n t h a t a plurality of MOS field effect transistors (TI, T2, T3) are driven by the same inhibiting voltage.
11. Circuit device substantially as hereinbefore described with reference to and/or as illustrated in the sole accompanying Figure.

6