GB2290877A - Integrated circuit test controller - Google Patents
Integrated circuit test controller Download PDFInfo
- Publication number
- GB2290877A GB2290877A GB9413222A GB9413222A GB2290877A GB 2290877 A GB2290877 A GB 2290877A GB 9413222 A GB9413222 A GB 9413222A GB 9413222 A GB9413222 A GB 9413222A GB 2290877 A GB2290877 A GB 2290877A
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuit
- serial
- data
- scan chain
- identifying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
- G01R31/318561—Identification of the subpart
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31702—Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/006—Identification
Abstract
An intergrated circuit 2 implementing JTAG debugging and analysis functions has an IDCODE Instruction which returns predetermined data characteristic of the intergrated circuit, e.g. manufacturer, part number and version. A portion 20 of the serial test scan chain of the integrated circuit 2 is re-used to load and then serially output this identifying data. The serial input of the test and debugging system is connected during such IDCODE Instructions to the start of the portion 20 of the serial test scan chain. This enables the identifying data of a plurality of integrated circuits with linked serial test scan chains to successively output their identifying data in one operation. <IMAGE>
Description
INTEGRATED CIRCUIT TEST CONTROLLER
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuits having serial test scan chains of the type used for debugging and analysing integrated circuit operation.
It is known from the JTAG system described in IEEE Standard 1149.1-1990 to provide an integrated circuit with a serial test scan chain for applying signals to and capturing signals from predetermined points within an integrated circuit. An example of such an arrangement is illustrated in Figure 1 of the accompanying drawings.
Figure 1 shows an integrated circuit 2 having a block of core logic 4 for performing the desired operation functions of the integrated circuit 2. For example, if the integrated circuit 2 is a microprocessor, then the core logic 4 could be a processor core and associated cache memory, co-processor, memory management unit and the like that are used when the integrated circuit 2 is operating normally to achieve its desired functions. The core logic 4 is surrounded by a serial test scan chain 6.
The serial test scan chain 6 is composed of a plurality of scan chains cells. Each scan chain cell can either apply a signal value, capture a signal value or be transparent relative to a predetermined point within the integrated circuit 2 to which it is coupled. The scan chain cells are connected together in a manner similar to a shift register, whereby signals to be applied or signals that have been captured can be shifted in or shifted out of the serial test scan chain 6.
The serial test scan chain 6 operates under control of a scan chain controller 8. The scan chain controller 8 has a test access port connecting it to elements outside of the integrated circuit 2. The test access port has five signal lines, i.e. a test data output line (TDO), a test data input line (TDI), a test mode selecting line (TMS), a test clock line (TCK) and an active low test reset line (nTRST). The
TDI line acts as a serial input. the TDO line acts as a serial output, the TCK line supplies the clock signal based upon which all test and analysis operations proceed and the nTRST line supplies a reset signal using which the test system can be forced to return to a predetermined known state. The TMS line supplies a mode signal which moves a state machine 10 within the scan chain controller 8 between states.
Dependent upon the current state of the state machine 10, control logic 12 within the scan chain controller 8 operates to configure the test systems in different ways, e.g. there will be states in which a serial test instruction is received, serial test data is received, serial test data is output, instructions that have been received are acted upon etc. Depending upon the particular state of the scan chain controller 8, a multiplexer 14 within the scan chain controller 8 serves to connect different points within the integrated circuit 2 to the TDO line.
One instruction implemented by the scan chain controller 8 is the
IDCODE instruction that is described within the IEEE Standard 1149.11990. Upon receipt of this instruction, the scan chain controller serves to output on the TDO line a series of bits that comprise identifying data that characterises the particular integrated circuit 2. Such a feature can be extremely useful in a debugging environment in which it is vitally important to know exactly what integrated circuit is being dealt with including its part number and the precise version of that part. This function is achieved by providing a shift register 16 into which the identifying data is loaded upon receipt of an IDCODE instruction and from where it is output to the TDO line via the multiplexer 14.
It is strongly advantageous within the field of integrated circuits to reduce the number of circuit elements within an integrated circuit. An integrated circuit having fewer components is generally easier to manufacture, less expensive, consumes less power and allows greater flexibility for the provision of circuit elements to provide other functions.
Viewed from one aspect this invention provides an integrated circuit comprising:
a circuit unit for performing an operational function within said integrated circuit;
a serial test scan chain coupled to said circuit unit for capturing signals from and applying signals to predetermined points within said circuit unit; and
a scan chain controller for controlling test operation of said serial test scan chain and having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit,
wherein said scan chain controller is responsive to an identifying-data-requesting-instruction input via said serial data input to control loading of predetermined identifying data characteristic of and stored within said integrated circuit into a portion of said serial test scan chain and to control serial output via said serial data output of said identifying data from said portion of said serial test scan chain.
The invention recognises and exploits the potential of the serial test scan chain to also serve as a mechanism for handling the output of the identifying data. Accordingly, in the example illustrated in
Figure 1, the shift register 16 is no longer required. The integrated circuit area needed to implement the shift register 16 might typically account for 30% of the area of the scan chain controller 8 and so the invention provides a significant reduction in the circuit area required for debugging and analysis purposes. A comparatively small increase in the number of other components of the scan chain controller 8 is required in order to switch an appropriate portion of the serial test scan chain 6 for use in outputting the identifying data, but this is outweighed by the saving in not having to provide a dedicated shift register.
The invention provides an additional advantage in embodiments in which said scan chain controller includes a multiplexer for connecting one of a plurality of points within said integrated circuit to said serial data output.
By removing the requirement for a dedicated shift register, it is possible to utilise a multiplexer having one fewer channel. This saves on circuit area and yields further of the advantages discussed above.
The identifying data could take many forms. However, it is usual and highly useful that the identifying data includes one or more of:
data identifying a manufacturer of said integrated circuit;
data identifying a part number of said integrated circuit; and
data identifying a version number for said integrated circuit.
It will be appreciated that the identifying data will usually be provided by the manufacturer of the integrated circuit. In this case the identifying data is stored within non-volatile storage within the integrated circuit.
The non-volatile storage could take the form of fusible links, read only memory or a series of connections to one or other of the voltage rail or ground rail depending upon the bit of data to be represented (i.e. the data may be hardwired into the IC).
Preferred embodiments of the invention further comprise an input multiplexer for connecting said portion of said serial test scan chain into which said identifying data is loaded to one of said serial data input or an output of a portion of said serial test scan chain immediately preceding said portion into which said identifying data is loaded, said input multiplexer switching to connect to said serial data input in response to said identifying-data-requesting-instruction.
The input multiplexer provides the ability to chain together the portions of the serial test scan chains from different ICs that will shift out the identifying data and so make possible the recovery of identifying data from a plurality of ICs in one operation.
Viewed from another aspect this invention provides a method of operating an integrated circuit, said method comprising the steps of:
performing an operational function with a circuit unit within said integrated circuit;
capturing signals from and applying signals to predetermined points within said circuit unit using a serial test scan chain coupled to said circuit unit for;
controlling test operation of said serial test scan chain with a scan chain controller having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit; and
in response to an identifying-data-requesting-instruction input via said serial data input, loading predetermined identifying data characteristic of and stored within said integrated circuit into a portion of said serial test scan chain and serially outputting said identifying data via said serial data output from said portion of said serial test scan chain.
An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Figure 1 illustrates an integrated circuit having a debugging and analysis system;
Figure 2 illustrates an integrated circuit having a debugging and analysis system in which the serial test scan chain is re-used as a mechanism for outputting identifying data characteristic of the integrated circuit; and
Figure 3 illustrates a state diagram for a state machine within a scan chain controller.
Figure 2 illustrates an integrated circuit 2 having core logic 4 and a serial test scan chain having a first portion 18 and a second portion 20. A scan chain controller 8 controls the operation of the serial test scan chain. The operation of the debugging and analysis system is essentially the same as that for Figure 1 as previously discussed other than in relation to the IDCODE instruction.
Upon receipt of an IDCODE instruction, the control logic 12 within the scan chain controller 8 outputs a signal to the second portion 20 of the serial test scan chain to trigger the second portion 20 to load the identifying data relating to the manufacturer, part number and version number of the integrated circuit 2 (typically 32 bits of data). Once this data has been loaded into the second portion 20, it is serially clocked out under control of the debugging clock TCK via the multiplexer 14 onto the TDO line. In this way, a dedicated shift register does not have to be provided within the scan chain controller for this purpose and the multiplexer 14 can be made to have one channel fewer.
An input multiplexer 22 is connected between the first portion 18 and the second portion 20 of the serial test scan chain. This input multiplexer 22 serves to direct data received on the TDI line to the second portion 20 during the action of an IDCODE instruction. This ensures that after the identifying data has been shifted out, any data shifted into the scan chain passes straight through after the delay of the second portion 20. This is significant when the serial test scan chains of a plurality of discrete integrated circuits are connected together to enable the identifying data for all the integrated circuits to be recovered in sequence by clocking the data through successive second portions 20 of the serial test scan chains of each integrated circuit.
Figure 3 illustrates the states through which the state machine 10 may be passed in accordance with the JTAG standard. Broadly speaking, the states can be considered as having an instruction capturing and interpretation section 24 and a data capturing and interpretation section 26. The manner in which the identifying-datarequesting-instruction IDCODE is handled relative to this state diagram can be described with reference to Table 1.
Action/State Mode Bit Required Data In Bits Received Start at Test-Logic- N/A N/A Reset State Move to Capture-IR 0110 State Cycle around Shift- 0000 1110 IR State to receive IDCODE Instruction Move to Update-IR 1011 State; Activate Instruction Decoder Move to Capture-DR 10 ** State; Load 2nd Portion and Switch Input Mux Cycle around Shift- 32 x '0' 32 x DR State to output Identifying Data Return to Run- 10110 Test/Idle State Table 1
The state machine 10 starts in the Test-Logic-Reset State, it being unimportant what mode bits or received data bits have proceeded that state. The state machine 10 is then moved through the state diagram illustrated in Figure 3 to the Capture-IR State. The mode bit sequence required to achieve this is "0110". During this move to the
Capture-IR State, it is unimportant what bits are present on the TDI line. The state machine 10 then cycles four times through the Shift-IR
State to receive the IDCODE Instruction.The mode bits required to achieve this are "0000" and the bits that will be captured from the TDI line during this cycling to specify the IDCODE Instruction will be "1110". After the IDCODE Instruction has been captured and stored, the state machine 10 moves to the Update-IR State by receipt of modes bits "1011". As the state machine 10 passes through the Update-IR State, it generates a signal that activates an instruction decoder and makes the
IDCODE Instruction the current instruction active within the scan chain controller 8.
The state machine 10 is then moved to the Capture-DR State by received mode bits "10". The control logic 12 then generates signals supplied to the second portion 20 of the serial test scan chain and the input multiplexer 22 to trigger the loading of the identifying data from hardwired non-volatile storage into the second portion 20 of the serial test scan chain and to switch the input multiplexer 22 to select the TDI line as its input. The state machine 10 then cycles for 32 clock periods about the Shift-DR State by application of 32 successive "O" bits to the TMS line. During this period the identifying data is clocked out of the second portion 20 of the serial test scan chain onto the TDO line via the multiplexer 14.The switched state of the input multiplexer 22 ensures and data applied to TDI is passed straight through the second portion 20 after the associated delay. In particular, if another integrated circuit is also in the identifying data output state, then its identifying data will be clocked into the uppermost part of the second portion 20 of the serial test scan chain and be available to be immediately output on the TDO line if more than 32 cycles through the Shift-DR State are made. Once all the identifying data that is desired has been recovered, the state machine is returned to the Run-Test/Idle State by application of mode bits "10110".
The IDCODE instruction is the default active instruction for the scan chain controller 8 following a reset. In this way, when starting from the Test-Logic-Reset State it is possible if so desired to move directly to the Capture-DR State relying upon the IDCODE instruction being active by default. In order to achieve this the mode bits "010" would be applied. Thereafter, the process would proceed as described in relation to the last three rows of Table 1.
It will be appreciated that the second portion 20 of the serial test scan chain could have any length, a greater length allowing more complex identifying data. It will also be appreciated that the portion of the serial test scan chain that is used for loading the identifying data and clocking it out from the integrated circuit need not necessarily be at the end of the serial test scan chain. If the portions so used is in the middle of the serial test scan chain, then a connection needs to be made from the end of that portion to the multiplexer 14.
Claims (8)
1. An integrated circuit comprising:
a circuit unit for performing an operational function within said integrated circuit;
a serial test scan chain coupled to said circuit unit for capturing signals from and applying signals to predetermined points within said circuit unit; and
a scan chain controller for controlling test operation of said serial test scan chain and having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit,
wherein said scan chain controller is responsive to an identifying-data-requesting-instruction input via said serial data input to control loading of predetermined identifying data characteristic of and stored within said integrated circuit into a portion of said serial test scan chain and to control serial output via said serial data output of said identifying data from said portion of said serial test scan chain.
2. An integrated circuit as claimed in claim 1, wherein said scan chain controller includes a multiplexer for connecting one of a plurality of points within said integrated circuit to said serial data output.
3. An integrated circuit as claimed in any one of claims 1 and 2, wherein said identifying data includes one or more of:
data identifying a manufacturer of said integrated circuit;
data identifying a part number of said integrated circuit; and
data identifying a version number for said integrated circuit.
4. An integrated circuit as claimed in any one of claims 1, 2 and 3, wherein said identifying data is stored within non-volatile storage within said integrated circuit.
5. An integrated circuit as claimed in any one of the preceding claims, comprising an input multiplexer for connecting said portion of said serial test scan chain into which said identifying data is loaded to one of said serial data input or an output of a portion of said serial test scan chain immediately preceding said portion into which said identifying data is loaded, said input multiplexer switching to connect to said serial data input in response to said identifying-datarequesting-instruction.
6. A method of operating an integrated circuit, said method comprising the steps of:
performing an operational function with a circuit unit within said integrated circuit;
capturing signals from and applying signals to predetermined points within said circuit unit using a serial test scan chain coupled to said circuit unit for;
controlling test operation of said serial test scan chain with a scan chain controller having a serial data input for input of serial data from outside of said integrated circuit and a serial data output for output of serial data to outside of said integrated circuit; and
in response to an identifying-data-requesting-instruction input via said serial data input, loading predetermined identifying data characteristic of and stored within said integrated circuit into a portion of said serial test scan chain and serially outputting said identifying data via said serial data output from said portion of said serial test scan chain.
7. An integrated circuit substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.
8. A method of operating an integrated circuit substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9413222A GB2290877B (en) | 1994-07-01 | 1994-07-01 | Integrated circuit test controller |
JP7142083A JPH0815376A (en) | 1994-07-01 | 1995-06-08 | Integrated-circuit testing controller |
US08/758,292 US5757819A (en) | 1994-07-01 | 1996-12-03 | Integrated circuit test controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9413222A GB2290877B (en) | 1994-07-01 | 1994-07-01 | Integrated circuit test controller |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9413222D0 GB9413222D0 (en) | 1994-08-24 |
GB2290877A true GB2290877A (en) | 1996-01-10 |
GB2290877B GB2290877B (en) | 1997-08-20 |
Family
ID=10757625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9413222A Expired - Lifetime GB2290877B (en) | 1994-07-01 | 1994-07-01 | Integrated circuit test controller |
Country Status (3)
Country | Link |
---|---|
US (1) | US5757819A (en) |
JP (1) | JPH0815376A (en) |
GB (1) | GB2290877B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0791836A1 (en) * | 1996-02-20 | 1997-08-27 | International Computers Limited | Electronic assembly identification device |
Families Citing this family (19)
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WO1999048001A1 (en) * | 1998-03-18 | 1999-09-23 | Lsi Logic Corporation | Improvements in microprocessor development systems |
US6694467B2 (en) * | 1999-06-24 | 2004-02-17 | Texas Instruments Incorporated | Low power testing of very large circuits |
US6412104B1 (en) * | 1999-02-01 | 2002-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit debugging system |
US6931572B1 (en) | 1999-11-30 | 2005-08-16 | Synplicity, Inc. | Design instrumentation circuitry |
US7065481B2 (en) | 1999-11-30 | 2006-06-20 | Synplicity, Inc. | Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer |
US7072818B1 (en) | 1999-11-30 | 2006-07-04 | Synplicity, Inc. | Method and system for debugging an electronic system |
US6618839B1 (en) * | 1999-11-30 | 2003-09-09 | Synplicity, Inc. | Method and system for providing an electronic system design with enhanced debugging capabilities |
US6823497B2 (en) | 1999-11-30 | 2004-11-23 | Synplicity, Inc. | Method and user interface for debugging an electronic system |
US7356786B2 (en) * | 1999-11-30 | 2008-04-08 | Synplicity, Inc. | Method and user interface for debugging an electronic system |
US6618827B1 (en) * | 2000-04-13 | 2003-09-09 | Hewlett-Packard Development Company, L.P. | System and method for parallel testing of IEEE 1149.1 compliant integrated circuits |
US6725387B1 (en) * | 2000-04-28 | 2004-04-20 | Hewlett-Packard Development Company, L.P. | Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed |
US6785854B1 (en) * | 2000-10-02 | 2004-08-31 | Koninklijke Philips Electronics N.V. | Test access port (TAP) controller system and method to debug internal intermediate scan test faults |
JP2004511045A (en) * | 2000-10-02 | 2004-04-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | System and method for enhancing manufacturing test failure analysis with dedicated pins |
US7222315B2 (en) * | 2000-11-28 | 2007-05-22 | Synplicity, Inc. | Hardware-based HDL code coverage and design analysis |
US7185249B2 (en) * | 2002-04-30 | 2007-02-27 | Freescale Semiconductor, Inc. | Method and apparatus for secure scan testing |
US7308631B2 (en) * | 2002-09-13 | 2007-12-11 | Arm Limited | Wrapper serial scan chain functional segmentation |
US7519883B1 (en) | 2005-04-05 | 2009-04-14 | Advanced Micro Devices, Inc. | Method of configuring a system and system therefor |
US7260491B2 (en) * | 2005-10-27 | 2007-08-21 | International Business Machines Corporation | Duty cycle measurement apparatus and method |
US8407541B1 (en) | 2010-06-18 | 2013-03-26 | Altera Corporation | Dynamic test signal routing controller |
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WO1984002580A1 (en) * | 1982-12-27 | 1984-07-05 | Storage Technology Partners | Vlsi chip with integral testing circuit |
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JP2676169B2 (en) * | 1989-12-27 | 1997-11-12 | 三菱電機株式会社 | Scan path circuit |
JP2561164B2 (en) * | 1990-02-26 | 1996-12-04 | 三菱電機株式会社 | Semiconductor integrated circuit |
GB9111179D0 (en) * | 1991-05-23 | 1991-07-17 | Motorola Gmbh | An implementation of the ieee 1149.1 boundary-scan architecture |
DE4232271C1 (en) * | 1992-09-25 | 1994-02-17 | Siemens Ag | Electronic component with a shift register test architecture (boundary scan) |
US5448576A (en) * | 1992-10-29 | 1995-09-05 | Bull Hn Information Systems Inc. | Boundary scan architecture extension |
US5333139A (en) * | 1992-12-30 | 1994-07-26 | Intel Corporation | Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain |
JP2727930B2 (en) * | 1993-10-04 | 1998-03-18 | 日本電気株式会社 | Boundary scan test circuit |
US5487074A (en) * | 1995-03-20 | 1996-01-23 | Cray Research, Inc. | Boundary scan testing using clocked signal |
-
1994
- 1994-07-01 GB GB9413222A patent/GB2290877B/en not_active Expired - Lifetime
-
1995
- 1995-06-08 JP JP7142083A patent/JPH0815376A/en active Pending
-
1996
- 1996-12-03 US US08/758,292 patent/US5757819A/en not_active Expired - Lifetime
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WO1984002580A1 (en) * | 1982-12-27 | 1984-07-05 | Storage Technology Partners | Vlsi chip with integral testing circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0791836A1 (en) * | 1996-02-20 | 1997-08-27 | International Computers Limited | Electronic assembly identification device |
Also Published As
Publication number | Publication date |
---|---|
US5757819A (en) | 1998-05-26 |
GB9413222D0 (en) | 1994-08-24 |
GB2290877B (en) | 1997-08-20 |
JPH0815376A (en) | 1996-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20140630 |