GB2290640A - Expanded I/O address space - Google Patents

Abstract

An information processing system includes a processor (12) having a circuit for omitting input/output (I/O) address signals within a predetermined n-bit I/O address range, and apparatus (14) for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to an I/O signal from the processor, to provide an expanded I/O address space. A bus bridge (Fig. 4) is also described. If the high bits of an address fall within a predetermined range then the low bits are transmitted to another bus. <IMAGE>

Description

COMPUTER SYSTEM The present invention relates to computer systems and more particularly to computer systems, such as personal computer systems, having multiple bus architectures.

Computer systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. Examples of the different types of buses present in typical computer systems are a system bus to which a host central processing unit is attached and one or more peripheral buses.

System-wide communication over different buses is required, that is, a device attached to one bus may need to read or write information to or from a device on another bus. To permit system-wide communication between devices on different buses, bus-to-bus bridges (interfaces) are provided to match the communications protocol and timing of one bus with that of another.

Each bus-to-bus bridge in a multiple bus computer system is used to connect two buses in the system. Various types of buses are available to construct a given computer system. One such bus which is becoming widely accepted is the PCI (Peripheral Component Interconnect) bus, which is capable of performing significant data transfer in a relatively short period of time. The PCI bus achieves a high level of performance, in part, because it may be directly linked to other high speed buses, such as system buses to which a CPU may be connected, and thus may provide for rapid transfer of data between devices attached to the PCI bus and devices attached to the system bus. In fact, the operation of several high integration devices, such as certain high performance graphics package controllers, require a direct link to a system bus through a high performance bus such as the PCI bus.In addition, the PCI bus architecture does not require any "glue logic to operate peripheral devices connected to it. Glue logic for other buses typically consists of miscellaneous hardware components such as decoders, buffers or latches that are installed intermediate the peripheral devices and the bus.

The primary PCI bus operates on a synchronous clock signal of 33 MHz, and the strings of data transmitted over the PCI bus are 32 bits wide. A 32-bit data string on the PCI bus is called a double word (DWORD), which is divided into 4 bytes each comprising 8 bits of data.

The address and data information carried by the PCI bus are multiplexed onto one set of signals. Multiplexing eliminates the need for separate address and data lines, which in turn, reduces the amount of signals required in a PCI bus environment as opposed to other bus architectures.

The number of signals required in PCI bus architecture is between 45-47 while non-multiplexed buses typically require twice this number.

Accordingly, because the number of signals are reduced, the number of connection pins required to support a device linked to the PCI bus is also reduced by a corresponding number. PCI architecture is thus particularly adapted for highly integrated desktop computer systems.

A more detailed description of the structure and operation of PCI bus architecture is provided in "Peripheral Component Interconnect (PCI) Revision 2.0 Specification", published April 30, 1993 and "Preliminary PCI System Design Guide", revision 0.6, published November 1, 1992, by the PCI Special Interest Group. It is assumed that the reader of this application is familiar with the contents of these references.

To satisfy user requirements for higher reliability and performance (e.g., as in servers) personal computer systems are being built with more and faster processors, faster networks and redundancy. The processors include Intel x86, RISC and other microprocessors. Some of these microprocessors do not support I/O address space. In addition, redundancy requirements have driven system designers to include more expansion slots in multiple expansion channels (for example, IBM Model 295 servers have two Micro Channels). Future computer systems will include multiple buses.

Personal computers and workstations are required to have expansion capability which allows the user to add adapters and devices to the base system after initial installation. To satisfy this requirement, these systems contain expansion buses. The two most common are the Industry Standard Bus and the Micro Channel.

As processor and I/O device speeds increased, the industry direction has been to satisfy the demands for high speed I/O functions by implementing local buses. Local buses support higher speed devices by attaching them in close proximity to the processor.

Personal computer systems constructed with the PCI or other local bus supporting multiple Micro Channel buses introduce an environment that may contain multiple instances of the same adapter. Since many Micro Channel adapters have been designed to support only two, three, or four instances in a system, addressing conflicts arise when more adapters are installed. New functions and features in personal computers have introduced a need for I/O addresses beyond the 64K supported by the Intel x86 architectures.

In today's environment, the address space architecture may be required to be compatible with the following architectures: (1) Micro Channel; (2) Industry Standard Architecture (ISA); (3) Peripheral Component Interface (PCI); (5) Personal System/2; (7) PowerPC; and (8) Personal Computer Memory Card International Association (PCMCIA).

Moreover, the address space architecture should support: (1) Processors with and without I/O address space; (2) Systems with multiple processors; (3) Systems with hierarchical buses; (4) Systems with multiple expansion buses (Micro Channel or EISA) ; (5) Addressability of system memory and non-system (I/O) memory by system master; (6) Addressability of I/O devices by System masters; (7) Addressability of system memory and non-system memory by bus masters on any bus; (8) Addressability of I/O devices by bus masters on any bus ; and (9) Protection of I/O addresses.

Accordingly, the invention provides a computer system comprising: a processor including means for emitting input/output (I/O) address signals within a predetermined n-bit I/O address range; and means for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to an I/O signal from the processor to provide an expanded I/O address space.

In a preferred embodiment, the additional m-bit address segment is appended to the I/O address emitted by the processor to form an n+m bit I/O address range comprising the I/O address emitted by the processor as a lower order portion and the additional m-bit address segment as a higher order portion. The means for appending an additional address segment comprises a segment register, coupled to the processor, for storing the additional m-bit address segment.

It is also preferred that the computer system further comprises a host bus, coupled to the processor; at least one subordinate expansion bus, coupled to the host bus; and a bus bridge for coupling the host bus to the subordinate expansion bus. The bus bridge comprises an address range filter for determining whether an I/O address received is within a predefined range of I/O addresses corresponding to the bus bridge, and for providing an output when the I/O address received is within the predefined range of I/O addresses.The bus bridge comprises a register set for defining the predefined range of I/O addresses, the register set comprising a first register for storing a first value corresponding to the I/O device having the lowest address segment associated therewith, and a second register for storing a second value corresponding to the I/O device having the highest address segment associated therewith.

Typically m and n represent equal numbers, for example n and m are both 16 in a preferred embodiment, in order to provide a mechanism that extends the 16 bit I/O address range of Intel x86 architectures to 32 bits.

The invention also provides a bus bridge for use in an information processing system having one or more processors, the one or more processors providing a first signal for selecting an I/O device, and one or more segment registers for providing a second signal for selecting a bus bridge, the bus bridge serving to couple a first bus to a second bus, the bus bridge comprising: a first input for receiving the first signal; a second input for receiving the second signal; an address comparator, coupled to the first and second inputs, for determining whether the second signal is within a predefined range of values corresponding to I/O segments subordinate to the bus bridge; and means for transmitting the first signal when the address comparator determines that the second signal is within the predefined range of values.

It is preferred that the bus bridge further comprises: a translator for converting the second signal to an I/O signal corresponding to the I/O device selected.

Thus a computer system or information processing apparatus may include a processor having an output for providing input/output (I/O) addresses, a host bus for coupling I/o devices to the processor, and means for appending an additional segment to an I/O address emitted by the processor, in response to an I/O signal from the processor.

A preferred embodiment of the invention will now be described in detail by way of example only, with reference to the following drawings: FIG. 1 shows a segmented 4GB I/O address space.

FIG. 2 is a block diagram of a computer system including segment registers, in accordance with the invention.

FIG. 3. is a block diagram showing extension of a CPU 16-bit I/O address to 32 bit.

FIG. 4 is a block diagram illustrating the operation of a bus bridge.

FIG. 5 is a block diagram futher illustrating the operation of a bus bridge.

Referring to FIG. 1, there is shown an expanded I/O address space of 32 bits or 4GB address space. The 4 GB I/O address space can be visualized as 64K individual address spaces, each 64 KB long. Each of the individual address spaces is called an I/O segment.

Referring to FIG. 2, there is shown a simplified block diagram of a computer system 10 having segment registers. The system 10 has a hierarchical PCI bus structure with Micro Channel buses subordinate to the PCI buses. In this system, one or more processor units 12 are coupled to a primary bus 16 and each processor is coupled to a segment register 14. The primary (or host) bus 16 is coupled to a subordinate bus 19 (a PCI bus in the preferred embodiment) via a host-to-PCI bus bridge 18. The primary PCI bus 19 may have attached devices or bus bridges to other PCI, Micro Channel (MC) or ISA buses. The computer system 10 has the capability of supporting multiple processors 12 and multiple expansion buses. The PCI bus 19 has a peripheral device 20, PCI bus bridges 22 and 26, and a MC/ISA bridge 28 attached thereto.PCI bus bridge 22 is coupled to another PCI bridge 30 and to a peripheral device 32, via PCI bus 23. The system memory 24 is actually coupled to the Host/PCI bridge 18 but is shown in FIG. 2 as being coupled to the I/O bus 19 to show how the processor 12 views the address space. The PCI bridge 26 is coupled to a MC or ISA bus bridge 34 and to a PCI bus bridge 36, via PCI bus 27. The PCI bus bridge 30 is coupled to an I/O device 38 and to a MC/ISA bridge 40, via PCI bus 31. MC/ISA bridge 40 is coupled to a Micro Channel device 48. The PCI bus bridge 36 is coupled to MC/ISA bus bridges 42 and 44, via PCI bus 37. Bus bridge 44 is coupled to a Micro Channel device 48 (which is the same type of device as device 46 and has the same I/O address).

The bus hierarchy is compatible with the PCI architecture and the Micro Channel architecture. In a preferred embodiment, the processor complex 12 includes one (or more) microprocessors, each of which includes an output that emits 16-bit I/O addresses with the M/IO (memory or I/O) in the I/O state. Thus, in this structure, the processor complex 12 emits an I/o address directed to an I/O device attached to one the expansion buses. The I/O address emitted by the processor 12 is augmented by an n-bit value appended in the high order bit positions when the M/IO signal is in the I/O state. This is accomplished with the segment registers 14 which may be external to the processor.

Devices on the PCI buses will be configured with I/O addresses that correspond to the bus I/O segment number. The Micro Channel or ISA expansion bus bridges use address range filtering registers to determine which I/O addresses are used by the devices on the subordinate bus. The input 32-bit address is compared to a start and end address range. If the address is within the specified range, the input address is transferred to an address compatible with the intended I/O device. In FIG. 2, the bridge 22 will recognize all addresses between 00010000 and 0003FFFF as corresponding to a subordinate bus. If the I/O device addresses for device 38 were 00020404, for example, the cpu 12 would output the address for device 38 (0404) and the segment register would have been loaded with the segment address 0002 (corresponding to the I/O segment for the bus to which device 38 is attached).Bridge 22 would recognize 0002 as corresponding to a device attached to one of its subordinate buses (i.e., bus 31) and it would transmit the I/O address downstream to its subordinate bus (i.e., bus 23). Bus bridge 30 would also recognize the segment address as being within its range and would transmit the I/O address to its subordinate bus 31. Device 38 would then respond to the device address (which was originally transmitted by the CPU 12).

System 10 solves the problem of addressing devices having the same 16-bit I/O address as follows. Assume that MC devices 46 and 48 both have address value 0404. The CPU 12 emits an I/O address 0404 on bus 16.

The segment register 14 appends a high order segment with the value 0003 to the bus 16 resulting in the address 00030404. The bus bridge 18 transmits that address to bus 19. 32-bit decoders in PCI devices 20 and 28 and PCI bridge 26 recognize that the address 00030404 does not correspond to them. PCI bus bridge 22 recognizes the address as corresponding to a device attached to one of its subordinate buses, so it transmits the address to bus 31. Bridge 40 recognizes the high order 16 bits (representing value 0003) as corresponding to it and, accordingly, transmits a 16-bit I/O address (representing the value 0404) directed to the selected device 46. Thus, identical I/O devices on different subordinate buses can share the same device address (the low-order 16 bits) without any conflicts.

Referring to FIG. 3, there is shown a block diagram illustrating the mechanism that is used to append the (high order) segment register bits to the high order bits of the I/O address as emitted by the processor 12. The bits from the 16-bit segment register 14 are gated onto the address component of bus 19, whenever the M/IO signal is in the I/O state. In the preferred embodiment bus 19 is a PCI bus with a 32 bit address bus but the invention is also applicable to buses having address bus components with other widths (e.g., 64 bits). When the M/IO signal is in its M state the CPU transmits a 32-bit address that is fully transferred to the address component of bus 19.

In operation, when the system 10 is initiated, the setup routine searches the I/O buses for devices and sets up a table for the operating system. The table identifies where I/O adapters are and what the segment register value is to load into the segment register. When the process needs to access an I/O adapter, it loads a device driver to interface the operating system to the hardware device. Before entering the device driver, the hardware abstraction code layer indexes into the table to find the device and the appropriate segment register value, loads the segment register and then calls the device driver. This function, loading, and resetting the device driver may also be done in a device driver. The device driver must, however, be designed or rewritten to enable it to do this function.

Referring now to FIG. 4, the operation of a bus bridge is illustrated. The segment register is issued at an address stage on the upper 'M1' bits of the address bus along with the I/O address on the lower 'M2' bits. The bus bridges monitor these upper 'Ml' bits to determine whether the transfer is intended for it. When the bridge determines that the transfer is destined for it, the bridge strips off the upper 'M1' bits and issues the lower 'M2' bits to the appropriate adapter on its I/O bus. This enables the system to support multiple I/O devices on different I/O buses with the same I/O address, providing a higher level of scalability and redundancy.

Referring now to FIG. 5, there is shown a bus bridge 100, in accordance with an aspect of the invention. The bridge 100 includes an address comparator 102 that is coupled to the address component of the primary bus for receiving the address signal and comparing it with a predetermined range of addresses corresponding to the values of the segment registers subordinate to the bridge 100. A filter 104 is coupled to the address comparator for filtering the received address to produce a signal for identifying the selected device (which is subordinate to the bridge 100). A translator 106 is coupled to the filter 104 to translate the output of the filter 104 into an address recognizable by the selected I/O device.

Claims (10)

1. A computer system comprising: a processor (12) including means for emitting input/output (I/O) address signals within a predetermined n-bit I/O address range; and means (14) for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to an I/O signal from the processor to provide an expanded I/O address space.

2. The computer system of claim 1, wherein the additional m-bit address segment is appended to the I/O address emitted by the processor to form an n+m bit I/O address range comprising the I/O address emitted by the processor as a lower order portion and the additional m-bit address segment as a higher order portion.

3. The computer system of claim 1 or 2, wherein the means for appending an additional address segment comprises a segment register, coupled to the processor, for storing the additional m-bit address segment.

4. The computer system of any preceding claim, further comprising: a host bus (16), coupled to the processor; at least one subordinate expansion bus (19), coupled to the host bus; and a bus bridge (18) for coupling the host bus to the subordinate expansion bus.

5. The computer system of claim 4, wherein the bus bridge comprises an address range filter (102, 104) for determining whether an I/O address received is within a predefined range of I/O addresses corresponding to the bus bridge, and for providing an output when the I/O address received is within the predefined range of I/O addresses.

6. The computer system of claim 5, wherein the bus bridge comprises a register set for defining the predefined range of I/O addresses, the register set comprising a first register for storing a first value corresponding to the I/O device having the lowest address segment associated therewith, and a second register for storing a second value corresponding to the I/O device having the highest address segment associated therewith.

7. The computer system of any preceding claim, wherein m and n represent equal numbers.

8. The computer system of claim 7, wherein m and n represent sixteen.

9. A bus bridge for use in an information processing system having one or more processors, the one or more processors providing a first signal for selecting an I/O device, and one or more segment registers for providing a second signal for selecting a bus bridge, the bus bridge serving to couple a first bus to a second bus, the bus bridge comprising: a first input for receiving the first signal; a second input for receiving the second signal; an address comparator, coupled to the first and second inputs, for determining whether the second signal is within a predefined range of values corresponding to I/O segments subordinate to the bus bridge; and means for transmitting the first signal when the address comparator determines that the second signal is within the predefined range of values.

10. The bus bridge of claim 9, further comprising: a translator for converting the second signal to an I/O signal corresponding to the I/O device selected.