GB2280320A - Capacitively coupled switch driver - Google Patents

Abstract

A digital system 14 operating at low voltage is capacitively coupled 3 to bistables 4, 5 controlling high voltage MOS switches 6. The digital system 14 and the bistables 4, 5 have the same logic swing but are displaced by a large common mode voltage difference. The digital system 14 may be a PLA configured to switch on either the high or low side switch to provide either a positive or negative output at 7. To set the output 7 to 0 V, both switches 6 are briefly turned on together. <IMAGE>

Description

VOLTAGE LEVEL CONVERSION This invention relates to the conversion of voltage levels for the purpose of interfacing different types of circuitry.

It is often required to interface TTL (Transistor-Transistor-Logic), which operates between 0 and 5 volts, or other standard logic to systems or devices requiring different, often higher, voltage levels. For example TTL logic may be used to control optical switches in optical fibre systems. These optical switches require drive voltages of typically + 75volts. Zener diodes have been used previously but these devices have a high power consumption making integration difficult. Since a specific Zener diode is needed for a given required voltage, the voltage levels can only be altered by replacing the diode. Additionally such a circuit is intolerant to drift in the voltage rails powering the circuit.

This invention provides a voltage level conversion circuit comprising an input capacitively coupled to a bi-stable latch the output of which triggers a solid state switch for the desired output voltage.

Such an arrangement can be switched rapidly and have low power consumption making it particularly suitable for electro-optical applications.

Preferably the bi-stable latch operates between two voltage levels the difference of which is equal to the voltage swing of the input, and for this purpose the input preferably includes a buffer to ensure that the voltage swings are equal.

Three embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which Figures 1 to 3 show respective circuit diagrams.

Referring to Figure 1 there is shown a circuit for converting TTL signals, which are typically 0 and 5 volts, to signals of 0 and 75 volts. The circuit includes an input stage 1 comprising an inverting buffer 2, having an input 2a, and which is powered from voltage rails operating at 0 and V, volts, as shown V, is equal to 5 volts. The output 2b of the inverting buffer 2 is coupled through a capacitor 3 to a buffer 4 and a resistor 5 which is connected between the input 4a and output 4b of the buffer 4.

The buffer 4 is powered from voltage rails V2 and V3, which in the present example are 70 and 75 volts respectively. The output 4b of the buffer 4 is connected to the gate electrode 6a of a p-channel Metal Oxide Field Effect Transistor (MOSFET) 6. The source electrode 6b is connected to the supply rail V3 and the drain electrode 6c to the output 7 of the circuit. A current limiting resistor 8 is connected between the output 7 and ground.

The inverting buffer 2 provides a low impedance drive to the capacitor 3 and ensures that the circuit as a whole is non-inverting; that is a 'high' voltage state at the input will produce a 'high' voltage state at the output and vice versa. The inverting buffer 2 whilst desirable is not an essential feature of the present invention since the correct drive conditions would be provided by connecting capacitor 3 to the TTL logic to be interfaced.

In use, assume firstly that when the circuit is initially powered up the voltage at the input 2a is held at a'low state, ie 0 volts. The output 2b of the inverting buffer 2 will charge plate 3a of the capacitor to a level of V, (5 volts). The plate 3b can only sit at voltage V2 or V3, that is 70 or 75 volts, which is a result of the positive feedback provided by the resistor 5 across the buffer 4. Assuming the voltage at the input 4a to the buffer 4 is V3 then the output 4b will also be Vs. As a result the Gate/Source voltage Vgs will be zero with respect to the level of V3 and the MOSFET 6 will be switched off pulling the level at the output 7 to zero volts.

When the voltage at the input 2a, changes state to voltage level V1 (5 volts), the voltage on the plate 3a of capacitor 3 will be brought down to zero volts due to the inverting action of inverting buffer 2. In response the voltage on plate 3b will also reduce by 5 volts to maintain charge balance. The voltage at the input 4a to buffer 4 will therefore be at a level Vz (70 volts) and will be held at this value due to the positive feedback provided by resistor 5. The buffer 4 now provides a positive value of Vgs above the switching threshold of the MOSFET 6. The MOSFET 6 switches on, becomes conductive and draws the level at the output 7 up to the level V3 (75 volts).

The buffer 4 and resistor 5 function as a bi-stable latch maintaining the voltage at the gate of the MOSFET at either V2 or V3 volts. The circuit is self correcting in that it is immaterial in which state the circuit powers up to since after a single change in input state the correct output state will be achieved.

Figure 2 shows a circuit for converting TTL levels to voltage levels V3 (+75 volts) and V5 (-75 volts). The circuit can be considered to comprise two circuit parts 9, 10 which are each similar to the circuit shown in Figure 1, and the same components are indicated by the same reference numerals. These parts 9, 10 are connected in parallel with a shared input stage 1 and have a common output 7. The circuit part 9 is the same circuit as that depicted in Figure 1 except that the output 7 is connected to the end of the current limiting resistor 8 remote from the p-channel MOSFET 6 . The circuit part 10 is the same as part 9 except that the p-channel MOSFET 6 is replaced with an n-channel MOSFET 11 and the buffer 4 is operated between voltage rails V4 and V5; -70 and -75 volts respectively.Additionally a capacitor 12is provided between the gate 6a, 1 la and drain 6c, 1 ic of each MOSFET 6, 11.

In use when MOSFET 6 is switched on MOSFET 11 will always be off and vice versa. The level at output 7 can therefore only be equal to V5 (-75) or V3 (+75) volts.

In optical switching applications it is often desirable to convert TTL logic drive levels to one of three possible states, most commonly -75, 0 or +75 volts. Figure 3 shows a further embodiment of the invention which converts binary logic applied to inputs 9a and 1 0a to a tri-state signal at the output 7. The circuit is the same as that in Figure 2 except that the circuit parts 9,10 now have discrete inputs 9a and lOaThe circuit operation when the voltage levels at both inputs 9a, 1 0a are the same is the same as that described with reference to Figure 2. However when they are not equal the situation can arise when both MOSFET's 6, 11 are conductive leading to damagingly large current as the full potential difference (V3-V5) is dropped across current limiting resistors 8.The circuit therefore has a different type of input stage 13 to prevent this occuring.

The input stage 13 comprises a programmable logic array (PLA) 14. Data on inputs 1 4a, 1 4b is loaded into the PLA 14 under control of a clock signal 15. The PLA 14 is configured such that when the logic levels at inputs 14a, 14b are the same, the outputs 1 4c, 1 4d will be held at the opposite levels so as to perform the necessary inverting action. However if the logic levels at inputs 14a, 1 4b are different (ie 'highl/'low' or 'low/high'), indicating that an intermediate (0 volt), output is required on line 7, the PLA 14 is programmed to produce for a short period of time a 'low' state on output 1 4c and a 'high' state on output 14d. In this condition both MOSFET's 6, 11, are conductive and the level at the output 7 is set to 0 volts. If the circuit was maintained in this condition the MOSFET's 6, 11 could overheat, therefore after this short period the levels at outputs 14c, 14d are reversed to turn off the MOSFET's 6, 11. The output 7 is therefore isolated and the level remains at its prevailing value, ie 0 volts. In this way the level at output 7 can be maintained at 0 volts for a prolonged period of time.

To prevent the level at the output 7 drifting over a prolonged period of time due to leakage via parasitic capacitances associated with the circuit it may be desirable to configure the PLA 14 to switch the MOSFET's 6,11 into a conducting state more than once within a given clock period.

Claims (15)

1 A voltage level conversion circuit comprising an input capacitively coupled to a bi-stable latch the output of which triggers a solid state switch for the desired output voltage.

2 A voltage level conversion circuit comprising a single input connected in parallel to two circuit parts, each part comprising a circuit according to claim 1 in which the respective switches are connected in series between two desired output voltage levels with the output of the circuit being taken from between the switches, the circuit being operable such that only one switch closes at a time to output either one of the output voltage levels.

3 A voltage level conversion circuit comprising two inputs each connected to a respective circuit part, each part comprising a circuit according to claim 1, the respective switches being connected in series between two desired output voltage levels with the output of the circuit being taken from between the switches, the circuit being operable to output either one of the two output voltage levels or an intermediate voltage level.

4 A voltage level conversion circuit according to any preceding claim in which the or each bi-stable latch comprises a buffer with a gain greater than unity.

5 A voltage level conversion circuit according to any preceding claim in which the or each bi-stable latch operates between two voltage levels the difference of which is equal to the voltage swing of the or each input.

6 A voltage level conversion circuit according to any preceding claim in which the or each input includes a buffer to ensure that the voltage swing at the input equals the voltage difference of the or each latch.

7 A voltage level conversion circuit according to any preceding claim in which the or each input includes an inverter.

8 A voltage level conversion circuit according to any preceding claim in which the or each bi-stable latch operates between two voltage levels and in which the or each solid state switch switches one of the two voltage levels for the switch's respective latch.

9 A voltage level conversion circuit according to any preceding claim in which the or each solid state switch is a field effect transistor.

10 A voltage level conversion circuit according to claim 2 or 3 in which one of the latches is connected between a pair of positive voltage levels and the other latch is connected to a pair of negative voltage levels.

11 A voltage level conversion circuit according to claim 3 including means for preventing the solid state switches from being both closed for any substantial period of time.

12 A voltage level conversion circuit according to claim 11 in which the intermediate voltage level is generated by applying a logic high to either one of the inputs and a logic low to the other input, the means being operative to reverse the logic on the two inputs after short period of time.

13 A voltage level conversion circuit according to claim 11 or 12 in which the means is a programmable logic array (PLA).

14 A voltage level conversion circuit according to any preceding claim in which a capacitor is connected between the control terminal of the or each solid state switch and one of its respective output terminals.

15 A voltage level conversion circuit substantially as described with reference to any one of the accompanying drawings.