GB2269720A

GB2269720A - Multi image display system

Info

Publication number: GB2269720A
Application number: GB9306785A
Authority: GB
Inventors: Koichi Sato
Original assignee: Asahi Kogaku Kogyo Co Ltd
Current assignee: Pentax Corp
Priority date: 1992-08-03
Filing date: 1993-04-01
Publication date: 1994-02-16
Also published as: FR2694428A1; GB9306785D0; DE4310907A1

Abstract

An image signal processing device provided in a still video device allows the display of a plurality of images in one frame. A plurality of image signals displayed in one frame are stored in a memory in synchronization with a clock signal having a relatively low frequency fSL The plurality of image signals are read out from the memory in synchronization with a clock signal having a relatively high frequency fSH and are outputted to a display which can output an image in a high definition mode. Since pixels of the images are not thinned out to be indicated in the frame, the resolution of the original images is maintained. <IMAGE>

Description

2269720 IMAGE SIGNAL PROCESSING DEVICE The present invention relates to an

image signal processing device by which a plurality of images can be simultaneously indicated on a display in one frame.

A conventional multi-frame forming device having an image signal processing device is disclosed in Japanese Unexamined Patent Publication No.2-82767. This multi-frame forming device is constructed in such a manner that a plurality of image signals stored in a memory are read as a plurality of multi-frame indicating signals arranged in a predetermined order, and thus, these multi-frame indicating signals are supplied to a display to be indicated as one multi-frame image.

In this conventional multi-frame forming device, however, to indicate a plurality of image signals which were originally indicated in single frames, in one frame at the same time, some pixels of each of the frames are thinned out. Namely, all of the information included in one image signal cannot be indicated in one section of a multi-frame image. Therefore, in the conventional multi-frame forming device, the resolution of each of the images is lowered, and thus, a sufficiently clear image cannot be obtained.

Therefore, an object of the present invention is to provide an image signal processing device by which a plurality of images are indicated in one frame without lowering the resolution of 2 each of the individual image signals.

According to the present invention, there is provided an image signal processing device comprising storing means, and reading means. The storing means stores a plurality of image signals in a memory in synchronization with a first clock signal. The reading means reads the plurality of image signals from the memory in synchronization with a second clock signal which has a higher frequency than the first clock signal.

Further, according the present invention, there is provided a one-frame image signal forming device comprising a memory, storing means, reading means and outputting means. The memory is provided for storing a plurality of image signals. The storing means stores the plurality of image signals in the memory in synchronization with a first clock signal. The reading means reads image signals from the memory in synchronization with a second clock signal which has a higher frequency than the first clock signal. The outputting means outputs a one-frame image signal in accordance with the image signals read by the reading means.

Furthermore, according to the present invention, there is provided a oneframe image signal forming device comprising a recording medium, a memory, first reading means, storing means, and second reading means. A plurality of image signals are stored in the recording medium. The memory is provided for storing the plurality of image signals. The f irst reading means reads a plurality of image signals from the recording medium. The storing 3 means stores a plurality of image signals in the memory in synchroniza ' tion with a first clock signal. The second reading means reads the plurality of image signals from the memory in synchronization with a second clock signal which has a higher frequency than the first clock signal in such a manner that a one-frame image signal formed by the plurality of image signals is indicated on a display which can output a high definition image.

The present invention will be better understood from the description of the preferred embodiments of the invention set forth below, together with the accompanying drawings, in which:-

Figure 1 is a block diagram showing a reproducing system of a still video device to which an embodiment of the present invention is applied; Figure 2 is a diagram schematically showing an example of recording image signals in memories in the embodiment; Figure 3 is a diagram showing a relationship between image signals recorded on a magnetic disk and image signals stored in the memories; Figure 4 is a diagram showing an operation of a blanking sync mix circuit; Figure 5 is a flowchart of a program by which image signals recorded on a magnetic disk in the frame record mode are reproduced; and 4 Figure 6 is a flowchart of a program by which image signals recorded on a magnetic disk in the field record mode are reproduced.

The present invention will now be described with reference to embodiment shown in the drawings.

Figure 1 is a block diagram showing a reproducing system of a still video device to which an embodiment of the present invention is applied.

A system control circuit 10 is a microcomputer controlling the still video device as a whole. A disk device including the still video device has a magnetic head 11 and a spindle motor 12 for rotating a magnetic disk D. The magnetic head 11 is controlled by the system control circuit 10 to be displaced along a radial direction of the magnetic disk D, and thus be positioned at a predetermined track of the magnetic disk D. The spindle motor 12 is controlled by the system control circuit 10 to rotate the magnetic disk D at a rotation speed of 3600 rpm, for example. During the rotation of the magnetic disk D, the magnetic head 11 is positioned at a ipredetermined track of the magnetic disk D and reproduces image signals and identification (ID) codes recorded on this track. Note, the magnetic disk D has 52 tracks, and the image signals and the other signals are recorded on 50 tracks starting from the outermost track and continuing inward on the magnetic disk D.

An operation unit 14 is connected to the system control circuit 10 to operate the still video device. The operation unit 14 has a multi-f rame indicating button (not shown) which is operated in a multi-frame indication mode, i.e., when a plurality of images are to be indicated in one frame at the same time.

A reproducing amplifier 41 is provided for reading an image signal and an ID code recorded on the magnetic disk D, and outputs the signals to a Yreproducing circuit 42, a C-reproducing circuit 43 and an ID-reproducing circuit 44. The Y-reproducing circuit 42 FM-demodulates a luminance signal (Y+S) including a synchronizing signal S (including a horizontal synchronizing signal and a horizontal synchronizing signal), and outputs the FM-demodulated signal. The C-reproducing circuit 43 FM-demodulates differential colour signals (R-Y, B-Y), and outputs the FM-demodulated signals. The ID-reproducing circuit 44 DPSK-demodulates the ID code, and outputs the DPSK-demodulated signal. Note, image signals have been recorded on the magnetic disk D according to the NTSC system (the National Television System Committee colour system), for example, by a usual still video device.

The synchronizing signal S included in the luminance signal (Y+S) is separated from the luminance signal (Y+S) by a synchronizing signal separating circuit 45, and is transmitted to a memory control circuit 46 and the control circuit 10. The memory control circuit 46 controls A/D converters 47, 48, a Y memory 51 and a C memory 52, based on the synchronizing signal S. The memory control circuit 46 controls D/A converters 54, 55, 56, the Y memory 51,and the C memory 52, based on a synchronizing 6 signal outputted from a synchronizing signal generating circuit 53, which outputs a synchronizing signal S (H) which conforms with the HDTV (High Definition TV) mode.

The luminance signal (Y+S) including the synchronizing signal is A-D converted by the A/D converter 47, and a luminance signal Y recorded between two horizontal synchronizing signals is stored in the Y memory 51 in synchronization with the horizontal synchronizing signal (a writing reference clock signal) of the synchronizing signal S under control of the memory control circuit 46. The luminance signal Y stored in the Y memory 51 is D-A converted by the D/A converter 54 based on the synchronizing signal S (H) (a reading reference clock signal) outputted from the synchronizing signal generating circuit 53. Similarly, the differential colour signals (R-Y, B-Y) are A-D converted by the A/D converter 48 and stored in the C memory 52. The differential colour signals (R-Y, B-Y) are alternately outputted from the C memory 52 based on the reading reference clock signal, and simultaneously outputted from a synchronization circuit 57 by an operation of the memory control circuit 46. Then, the differential colour signals (R-Y, B-Y) are D-A converted by the D/A converters 55, 56, based on the reading reference clock signal outputted from the synchronizing signal generating circuit 53.

The reading reference clock signal has a frequency which is, for example, four times the writing reference clock signal used for recording the image signals in the memories 51, 52.

7 Accordingly, the image signals are read out from each of the memories 51, 52 at relatively high speed so that the image signals are time-compressed.

Blanking sync mix circuits 61, 62, 63 are provided f or setting a predetermined portion in front of each of the luminance signal Y and the dif f erential colour signals (R-Y, B-Y) to a zero level, and superimposing a synchronizing signal S(H) on that portion. By an operation of the blanking sync mix circuits 61, 62, 63, a clear synchronizing signal S (H) which conforms with a system such as the HDTV mode, is supplemented in a portion in front of the luminance signal Y and the differential colour signals (R-Y, B-Y), respectively. Each of the signals (Y+S), (R-Y+S) and (B-Y+S) outputted from the blanking sync mix circuits 61, 62, 63 is a television signal which is in conformity with the HDTV mode (the high-vision mode, for example), and is outputted to a display which can output a high definition image.

Note, in the drawing, the reference 'W' added to the luminance signal and the differential colour signal refers to high quality. Further note, the signals generated by the device of this embodiment have a bandwidth which is four times that of a television signal generated by a usual still video reproducing device, and the display has a resolution which is four times that of a usual dispI y.

The ID code stored on the magnetic disk D is processed by the IDreproducing circuit 44 to be subjected to a DPSK-demodulation and so on, so that the ID code is decoded by the system control 1 8 circuit 10.

Figure._2 schematically shows an example of recording image signals in the Y memory 51 and the C memory 52 in such a manner that the image signals are indicated on an actual frame. Note, in the drawing, the number of scanning lines and the positions at which the scanning lines are started in the frame are not shown exactly. Fig. 2 shows a state in which the four frame image signals recorded on the magnetic disk D in a frame record mode are recorded in the Y memory 51 and the C memory 52. Namely, one frame is composed of a f irst f ield and a second f ield, and as shown in the drawing, the scanning lines shown by solid lines denote the f irst f ield and the scanning lines shown by broken lines denote the second field. The frame A is divided into four parts by a centre line E extending in a vertical direction and passing through the centre of the frame, and a centre line F extending in a horizontal direction and passing through the centre of the frame. Namely, one frame includes f our images, i.e., a first image to a fourth image.

The memories 51, 52 have a first recording area to an eighth recording area, and each of the individual fields of each image is stored in one of the recording areas. Namely, the image signal corresponding to a first field of the first image is stored in a f irst recording area of the memory, and the image signal corresponding to a second field of the first image is stored in the second recording area of the memory. Similarly, the image signal corresponding to a f irst f ield of the second image is

9 stored in a third recording area of the memory, and the image signal corresponding to a second field of the second image is stored in a fourth recording area of the memory. Further, the image signal corresponding to a first field of the third image is stored in a fifth recording area of the memory, and the image signal corresponding to a second field of the third image is stored in a sixth recording area of the memory. The image signal corresponding to a first field of the fourth image is stored in a seventh recording area of the memory, and the image signal corresponding to a second field of the fourth image is stored in an eighth recording area of the memory.

The image signals stored in the first to the eighth recording areas are recorded in f irst to eighth tracks of the magnetic disk D.

Figure 3 shows a relationship between an image signal stored on the magnetic disk D and an image signal stored in the memories 51, 52. With reference to Figs. 2 and 3, the relationship is described below.

An image signal K1 of the first field of the first image is recorded in the first track of the magnetic disk, and an image signal K2 of the first field of the third image is recorded in the fifth track of the magnetic disk. These image signals KI, K2 are stored in the memories 51, 52, respectively. The image signal G1 corresponding to the image signal K1 and the image signal G2 corresponding to the image signal K2 are stored at sequential addresses in the memories, and thus, by reading the data of the image signal sequentially f rom left to right in Fig. 2, these image signals G1, G2 form one scanning line. This same applies for the second field.

The image signals G1, G2 stored in the memories 51, 52 are timecompressed by four times relative to the image signals K1, K2 stored on the magnetic disk D. Namely, when the bands of the image signals stored on the magnetic disk D are fH/4, the bands of the image signals stored in the memories 51, 52 are fH- The image signals in the memories 51, 52 are read in sequence by scanning lines. Namely, the image signals are read out by scanning lines, in the order of the first recording area, the fifth recording area, the third recording area and the seventh recording area, so that the first field is reproduced, and then, the image signals are read in order of the second recording area, the sixth recording area, the fourth recording area and the eighth recording area so that the second field is reproduced.

Figure 4 shows an operation of the blanking sync mix circuits 61, 62, 63. Image signals L read out from the memories 51, 52 are added to pulse signals (the synchronizing signal S(H)) outputted from the synchronizing signal generating circuit 53, by adders 71 provided in the blanking sync mix circuits 61, 62, 63, whereby image signals according to the highvision television mode are obtained, and thus, the image signals are outputted to a display which can output a high definition image. Note, in Figure 4, a horizontal synchronizing signal is added in front of each of signals Y, R-Y, B-Y, and a vertical synchronizing signal is not shown.

Figure 5 shows a flowchart of a program by which image signals recorded in the frame record mode are reproduced and indicated in one frame, i.e., a multi-frame is indicated by a display. This program is started by pushing the multi-frame indicating button of the operation unit 14.

To A-D convert image signals and store them in the memories 51, 52, the image signals must be sampled with a frequency of more than twice the band of the image signals, according to the Nyquist theorem. Therefore, in Step 101, the frequency of the memory clock is set to fs,,, which is more than or equal to twice the bandwidth of the image signals recorded on the magnetic disk. This memory clock is generated based on the reference clock signals outputted from the synchronizing signal generating circuit 45. In Step 102, a counter N is set to 11111.

Then, in Step 103, the ID code of a track at which the magnetic head is located is decoded, whereby it is determined whether the image signal of the track is recorded in the frame record mode or the field record mode. Furthermore, in the case of the frame record mode, a track forming a pair with the track at which the magnetic head is located is determined.

In Step 104, the record mode is determined based on the ID code. When the record mode of the track which is being reproduced at present is the field record mode, it is determined in Step 105 whether or not this track is the 50th track, i.e., the innermost track. In the case of the 50th track, Step 121 described later

12 is carried out, and in the other cases, the magnetic head is moved inwardly by one track in Step 106. Then, Steps 103 and 104 are carried out again. When it is determined in Step 104 that the record mode of the track which is being reproduced at present is the frame record mode, Steps 111 through 117 are carried out so that the image signals are stored in the memories 51, 52, as described later.

In Step 111, it is determined whether the track which is being reproduced at present is located at the outer position of the disk relative to a track forming a pair with the former track. As is well known, in the frame record mode, one image is recorded in two tracks which are located adjacent to each other, and a first field is stored in the outer track and a second field is stored in the relatively inner track. Furthermore, in the inner track, the track number of the outer track forming a pair with the inner track is recorded. In Step 111, when it is determined that the track which is being reproduced at present is the outer track, Step 113 is carried out so that the first field is stored in the memories. Conversely, in Step 111, when it is determined that the track which is being reproduced at present is the inner track, Step 113 is carried out after the magnetic head is moved outwardly by one track in Step 112.

In Step 113, an image signal is stored in the Nth recording area of each of the memories. When this Step 113 is carried out f or the f irst time, the image signal is stored in the f irst recording area. Namely, f or example, the f irst f ield of the f irst 13 image is stored in the first recording area of the memory. Then, the magnet-_ic head is moved inwardly by one track in Step 114, and thus, an image signal is stored in the (N+1)th recording area of the memory. In this example, the second field of the first image is stored in the second recording area of the memory, and thus, the image signals forming a pair are stored in the memory.

After the counter N is increased by 11211 in Step 116, it is determined in Step 117 whether or not the counter N is larger than 11711. When the counter N is larger than 11711, since this means that image signals have been already stored in the first recording area to the eighth recording area of the memory, the process goes to Step 121 so that reproduction of the image is carried out as described later. Conversely, when the counter N is less than or equal to 11791, the process returns to Step 104, and thus, Step 104 and the following Steps are carried out again. such an operation is repeatedly carried out so that image signals of the first image to the fourth image are stored in the first recording area to the eighth recording area of each of the memories 51, 52.

In Step 121, the memory clock is set to f SH which is four times the frequency f SL set in Step 101. In Step 122, the image signals stored in the recording areas of the memories 51, 52 are reproduced, in synchronization with this high speed memory clock. Namely, after one scanning line of the first recording area is reproduced, one scanning line which follows the scanning line of the first recording area and includes the fifth recording area 14 is reproduced. Such an operation is repeatedly carried out so that the image signals of the first recording area and the fifth recording area are reproduced. Similarly, the image signals of the third recording area and the seventh recording area are reproduced. Accordingly, the first fields of four images are reproduced. Similarly, image signals of the second, the sixth, the fourth and the eighth recording areas are reproduced so that the second fields of the four images are reproduced.

Thus, one frame is reproduced, and four different images are indicated in the frame. Since the four images are stored in the memories 51, 52 based on the memory clock signal having the frequency fSL, the pixels of the image signals are not thinned out when the images are stored in the memories 51, 52. Further, these images are reproduced, time-compressed by 1/4 times the image scanning time of a usual reproducing operation, by the operations of Steps 121, 122, and then, the images are indicated on a display which can indicate a picture in the high definition mode. Accordingly, the resolution of the images indicated on the display are the same as the original images recorded on the disk D. Namely, with this embodiment, images which are as clear as the original images can be obtained.

Figure 6 shows a flowchart of a program by which image signals recorded in the field record mode are reproduced and indicated in the multi-frame mode. Namely, an image signal is stored in each of the first, the third, the fifth and the seventh recording areas, and this program is started by pushing the multi-frame is indicating button of the operation unit 14, similarly to the program shown in Fig. 5.

In Step 201, the frequency of the memory clock is set to fSLY which is more than or equal to twice the bandwidth of the image signals recorded on the magnetic disk, similar to Step 101. In Step 202, a counter N is set to 11111. In Step 203, an image signal is stored in the (2N-1)th recording area of each of the memories. When this Step 203 is carried out for the first time, the image signal is stored in the first recording area. Namely, for example, the first image is stored in the first recording area of the memory. Then, in Step 204, the counter N is increased by 11111. In Step 205, it is determined whether or not the track which is being reproduced at present is the 50th track, i.e., the innermost track. In the case of the 50th track, Step 211 described later is carried out, and in the other cases, it is determined in Step 206 whether or not the counter N is larger than 11411. When the counter N is larger than 11411, since operations in which image signals are stored in the first, the third, the fifth and the seventh recording areas of' the memories are completed, the process goes to Step 212, so that reproduction of the image is carried out as described later. Conversely, when the counter N is less than or equal to 11411, the magnetic head is moved inwardly by one track in Step 207, and then, the process returns to Step 203 so that Step 203 and the following Steps are carried out again. Such an operation is repeatedly carried out, so that image signals of the first image to the fourth image are 16 stored in the first, the third, the fifth and the seventh recording. area of each of the memories 51, 52.

In Step 212, the memory clock is set to f SH which is f our times the frequency f SL set in Step 201. In Step 212, the image signals stored in the recording areas of the memories 51, 52 are reproduced, in synchronization with this high speed memory clock.

With the embodiment shown in Fig. 6, f our different images recorded in the f ield record mode are indicated as one frame. With this embodiment, images which are as clear as the original images can be obtained, similarly to the embodiment shown in Fig. 5.

Note, although a ratio between a frequency of the writing reference clock signal and that of the reading reference clock signal can be set to any value, if an aspect ratio of divided image (a quarter of one frame in the example shown in Figure 2) is the same as that of a display of a highvision device, the frequency f SH is preferably K2 times the frequency f SL, wherein K is an integer larger than or equal to 2.

Although the embodiments of the present invention have been described herein with reference to the accompanying drawings, obviously many modifications and changes may be made by those skilled in this art without departing from the scope of the invention.

The present disclosure relates to subject matter contained in Japanese Patent Application No. 4-226429 (filed on August 3, 1992) which is expressly incorporated herein by reference in its entirety.

Claims

17 CLAIMS

1. A device f or processing a plurality of image signals, the device comprising:means f or storing said plurality of image signals in a memory in synchronization with a first clock signal; and means for reading said plurality of image signals from said memory in synchronization with a second clock signal which has a higher frequency than said first clock signal.

2. A processing device according to claim 1 wherein said reading means outputs said plurality of image signals in such a manner that these image signals are indicated as one frame on a display which can output a high definition image.

3. A processing device according to claim 2 wherein said one frame is divided into a plurality of parts by a f irst line extending in a vertical direction and passing through the centre of said frame and a second line extending in a horizontal direction, each of said parts corresponding to one of said image signals, the number of said parts being K 2, K being an integer larger than or equal to 2.

4. A processing device according to any preceding claim wherein said f irst clock signal is a horizontal synchronizing signal included in a luminance signal included in said image signals.

18

5. A processing device according to any preceding claim further comprising a synchronizing signal generating circuit for generating said second clock signal.

6. A processing device according to any preceding claim wherein said second clock signal has a frequency which is K2 times said first clock signal, wherein K is an integer larger than or equal to 2.

7. A device for forming a one-frame image signal in accordance with a plurality of image signals, the device comprising:a memory provided for storing said plurality of image signals; means f or storing said plurality of image signals in said memory in synchronization with a first clock signal; means f or reading said image signals from said memory in synchronization with a second clock signal which has a higher frequency than said first clock signal; and means for outpitting a one-frame image signal in accordance with said image signals read by said reading means.

8. A device f or f orming a one-frame image signal, the device comprising:a recording medium in which a plurality of image signals are stored; a memory provided for storing said plurality of image signals; 19 means for reading said plurality of image signals from said recording pedium; means f or storing said plurality of image signals in said memory in synchronization with a first clock signal; means for reading said plurality of image signals from said memory in synchronization with a second clock signal which has a higher frequency than said first clock signal in such a manner that said one-frame image signal formed by said plurality of image signals is indicated on a display which can output a high definition image.

9. A device for processing a plurality of image signals substantially as hereinbefore described with reference to the accompanying drawings.