GB2257585A - A comparator circuit - Google Patents
A comparator circuit Download PDFInfo
- Publication number
- GB2257585A GB2257585A GB9219514A GB9219514A GB2257585A GB 2257585 A GB2257585 A GB 2257585A GB 9219514 A GB9219514 A GB 9219514A GB 9219514 A GB9219514 A GB 9219514A GB 2257585 A GB2257585 A GB 2257585A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pair
- mos transistors
- drain
- comparator
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
Abstract
A switched comparator is described for deriving binary values from an input signal. The comparator consists of a long-tailed pair of MOS transistors with the input signal and a threshold value signal respectively applied to the gates, and a crosscoupled pair connected drain-to-drain to the long-tailed pair, with the output taken from one of the commoned drain connections. A gating MOS transistor is connected between the commoned drain connections so that an output is obtained only when the gating transistor is non-conducting. <IMAGE>
Description
IMPROVEMENTS IN OR RELATING TO COMPARATOR CIRCUITS
This invention relates to comparator circuits.
It is an object of the present invention to provide an improved comparator circuit.
According to an aspect of the invention there is provided a comparator circuit for producing an output signal indicating which of two input signals has the higher voltage at a given instant, the circuit including a first pair of MOS transistors of a first conductivity type connected as a long-tailed pair and to the gates of which the input signals are respectively applied, a second pair of MOS transistors of a second conductivity type opposite to the first conductivity type, connected as a crosscoupled pair and with their drains connected respectively to the drains of the first pair of MOS transistors, the output signal being obtained from one or other or both of the commoned drain connections, and a normally conducting fifth MOS transistor having its source-drain path connected between the commoned drain connections of the pairs of MOS transistors and its gate connected to receive a gating signal defining the given instant by assuming for that instant a voltage capable of causing the fifth MOS transistor to be non-conducting.
An example of a comparator circuit in accordance with the invention will now be described with reference to the single figure of the accompanying drawing which shows a circuit diagram of a clocked comparator circuit for comparing a received signal with a threshold level at particular instants in time.
The clocked comparator described herein is suitable for use in the digital signal processor hat is described in the copending Application No. 88.22114.8, Publication No. 2 225 198, entitled "Improvements in or relating to Digital
Signal Processors", filed by Texas Instruments Limited, from which this application is divided. That digital signal processor receives a video signal containing teletext data and separates out the teletext data. In that digital signal processor the clocked comparator described herein is used to sample the video signal at a rate of 55.5 MHz. However it is to be understood that the clocked comparator is not limited in its usefulness to sampling the level of a teletext signal but can be used to compare any two signals-.
The Figure shows the circuit of an example of the clocked comparator. In the Figure, the signals to be compared are applied via terminals 101 and 102 respectively to the gates of p-channel MOSFET's 103 and 104 connected as a long-tailed pair. The tail of the long-tailed pair is a current source formed by a p-channel MOSFET 105 having its source connected to a positive supply conductor 106. The gate of the MOSFET 105 is connected to the gate and drain of another p-channel MOSFET 107 of which the source is connected to the conductor 106. A current source 108 feeds current to the drain of the MOSFET 107, the MOSFET's 105 and 107 forming a current mirror.The current source 108 may be simply a high value resistor connected to ground, but since in sore applications, for example, the digital signal processor mentioned above, the comparator is part of a large integrated circuit the current source may be formed by current mirror means supplying controlled currents to other parts of the circuit and connected to an external resistor.
The drains of the MOSFET's 103 and 104 are connected to the drains of a cross-coupled pair of n-channel MOSFET's 109 and 110, the sources of which are connected to a grounded conductor 111. The cross-coupling of the MOSET's 109 and 110 is formed in each case by a direct connection from the drain of one transistor to the gate of the other.
The commoned drain connections 11 and 113 are interconnected by the source-drain path of an n-channel MOSFET 114, the gate of which is connected to a terminal 115. The commoned drain connection 112 is connected through a CMOS inverter circuit formed by the MOSFET's 116 and 117 to an output terminal 118. The connection 113 is connected through a CMOS inverter circuit formed by the MOSFET's 119 and 120 to a terminal 121. The output from the comparator may be taken from either or both of the connections 112 and 113 or from the terminal 118 or 121.
In the operation of the comparator shown in the
Figure, the input signals are applied via the terminals 101 ana 102, and unless the input signals are of very similar voltage one of the MOSFET's 103 and 104 will be rendered conducting and the other non-conducting, because their sources are maintained at the same potential by the tail of the long-tailed pair. If the voltage of the input signals are similar the transistors 103 and 104 will operate as a differential amplifier so that the amplified difference voltage tends to appear between the drains of the MOSFET's. Initially, the MOSFET 114 is conducting because a positive voltage is applied to the terminal 115, and therefore the connections 112 and 113 are maintained at the same potential.At this time the output voltage or voltages derived from one or other or both of the connections 112 and 113 are the same and do not depend on the input voltages but are set by the current supplied by the MOSFET 105. When the voltage applied to the terminal 115 goes negative, the MOSFET 114 ceases to conduct, so that the drain of one of the MOSFET's 103 and 104 tends to go more positive than that of the other and this difference in voltage rapidly causes the cross-coupled pair of
MOSFET's 109 and 110 to bring the voltage of one of the connections 112 and 113 to be close to ground potential and the other to move towards the positive supply potential.
Under these circumstances, the voltages on the connections 112 and 113 differ, and which is high and which is low is determined by the relative magnitudes of the voltages applied to the input terminals 101 and 102.
When it is required to reset the comparator a positive voltage is again applied to the terminal 115 causing the
MOSFET 114 to conduct again. This rapidly brings the potentials of the connections 112 and 113 to the same value depending entirely on the current supplied by the MOSFET 105. This method of resetting the comparator enables a cross-coupled pair of MOSFET's to be used for the comparison, such a circuit having a very high speed of response to voltage differences by virtue of the regenerative feedback. The disadvantage of a cross-coupled pair that they introduce hysteresis into the comparison is avoided by the use of the short-circuiting MOSFET 114 to reset the comparator; this MOSFET holds the drain voltages of the cross-coupled pair to the same voltages overriding the regenerative feedback.The short-circuiting MOSFET 114 also permits the long-tailed pair of MOSFET's 103 and 104 to establish their conductive states in response to the input signal without hysteresis before the comparator is clocked to produce an output signal.
Since the voltages on the connections 112 and 113 whilst the MOSFET is conducting are dependent on the current supplied by the MOSFET 105, the threshold voltage of conduction of the MOSFET 115 is constant and independent of the input voltages. This means that the sampling of the input signals is carried out at a precise time, that is to say, when the clock voltage falls below the gate threshold voltage of the MOSFET 114.
It will be appreciated that because of the symmetry there is no systematic offset voltage to interfere with the comparison of the two input voltages.
When a clocked comparator is used in the digital signal processor mentioned above, the clocking frequency is 55.5 MHz and it has been found that a 10 -mV difference between the input signals applied to the comparator can cause the production of appropriate 0 and 1 outputs after 3 ns.
Claims (4)
1. A comparator circuit for producing an output signal indicating which of two input signals has the higher voltage at a given instant in time, the circuit including a first pair of MOS transistors of a first conductivity type connected as a long-tailed pair and to the gates of which the input signals are respectively applied, a second pair of MOS transistors of a second conductivity type opposite to the first conductivity type, connected as a crosscoupled pair and with their drains connected respectively to the drains of the first pair of MOS transistors, the output signal being obtained from one or other or both of the commoned drain connections, and a normally conducting fifth MOS transistor having its source-drain path connected between the commoned drain connections of the pairs of MOS transistors and its gate connected to receive a gating signal defining the given instant in time by assuming for that instant a voltage capable of causing the fifth MOS transistor to be non-conducting.
2. A comparator circuit according to claim 1, wherein the sources of the MOS transistors of the first pair are connected to a constant current source.
3. A comparator circuit according to claim 1 or claim 2, wherein the gate of each of the MOS transistors of the second pair is directly connected to the drain of the other
MOS transistors of that pair.
4. A comparator substantially as described herein and as illustrated by the single Figure of the accompanying drawing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9219514A GB2257585B (en) | 1988-09-20 | 1992-09-14 | Improvements in or relating to comparator circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8822114A GB2225198B (en) | 1988-09-20 | 1988-09-20 | Improvements in or relating to digital signal processors |
GB9219514A GB2257585B (en) | 1988-09-20 | 1992-09-14 | Improvements in or relating to comparator circuits |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9219514D0 GB9219514D0 (en) | 1992-10-28 |
GB2257585A true GB2257585A (en) | 1993-01-13 |
GB2257585B GB2257585B (en) | 1993-05-05 |
Family
ID=26294417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9219514A Expired - Fee Related GB2257585B (en) | 1988-09-20 | 1992-09-14 | Improvements in or relating to comparator circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2257585B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10230168A1 (en) * | 2002-07-04 | 2004-01-22 | Infineon Technologies Ag | Level conversion facility |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4511810A (en) * | 1981-09-03 | 1985-04-16 | Nippon Electric Co., Ltd. | Voltage comparator circuit |
-
1992
- 1992-09-14 GB GB9219514A patent/GB2257585B/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4511810A (en) * | 1981-09-03 | 1985-04-16 | Nippon Electric Co., Ltd. | Voltage comparator circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10230168A1 (en) * | 2002-07-04 | 2004-01-22 | Infineon Technologies Ag | Level conversion facility |
DE10230168B4 (en) * | 2002-07-04 | 2004-05-27 | Infineon Technologies Ag | Level conversion facility |
DE10230168B9 (en) * | 2002-07-04 | 2004-09-16 | Infineon Technologies Ag | Level conversion facility |
US6954099B2 (en) | 2002-07-04 | 2005-10-11 | Infineon Technologies Ag | Level shifter without dutycycle distortion |
Also Published As
Publication number | Publication date |
---|---|
GB9219514D0 (en) | 1992-10-28 |
GB2257585B (en) | 1993-05-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20070920 |