GB2256747A - Method for manufacturing semiconductor device capacitor - Google Patents

Method for manufacturing semiconductor device capacitor Download PDF

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Publication number
GB2256747A
GB2256747A GB9124626A GB9124626A GB2256747A GB 2256747 A GB2256747 A GB 2256747A GB 9124626 A GB9124626 A GB 9124626A GB 9124626 A GB9124626 A GB 9124626A GB 2256747 A GB2256747 A GB 2256747A
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GB
United Kingdom
Prior art keywords
layer
capacitor
semiconductor device
sic
silicon carbide
Prior art date
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Withdrawn
Application number
GB9124626A
Other versions
GB9124626D0 (en
Inventor
Geun-Ha Jang
Ang-Goo Lee
Yu-Chan Jin
Tae-Gyu Jang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9124626D0 publication Critical patent/GB9124626D0/en
Publication of GB2256747A publication Critical patent/GB2256747A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen

Description

1 ' - 1 EMOD FOR tk\LF.ACRJRI.14G A SWOONDUCIOR DR-ICE The pTesent i nvent
i on relates to a method for manufacturing a semi conductor dev i ce. and espec i a I 13- to a method which increases the capacitance of a memory device.
Recently, the development of large capacity memory devices has been progressed along with the development of semiconductor manufacturing methods and extension of the applicable field of memory devices. There has been particularly significant progress in dynamic random access memory -,DRAM) devicesin which one memory cell consists of one capacitor and one transistor, creating an integration advantage by enabling four times the integration in just three years. Presently, progress in the respective integration density categories is such that the 41hIb DPkkl is actively manufactured and the I 6INIb is under rapid development for active manufacture, while the 64hIb and 256Mb devices are actively being investigated for development.
Any such semiconductor memory device should possess large capacitance in order reliably to read out and store information. However, when integration density increases by four times. the size of the chip increases by only 1.4, so that relative memory cell size will decrease to one third. Therefore. existing capacitor structures cannot possess the necessary cell capacitance in a limited area. This demands investigation into methods for obtaining larger capacitances 2 for a given area.
These methods can be divided into three basic techniques: making dielectric layers thinner; increasing the ef f ective area of the capacitor; and the use of materials having large dielectric constants. With reference to the first technique, where the thickness of the dielectric layer is below 100A, use is limited by the Fowler-Nordheim current, and there are serious problems with reliability, which results in difficulties when applying this technique to a large capacitance memory device.
The second case, i.e., increasing of the capacitor's effective area, shows the greatest development and is classified into stack-type capacitor cells and trench-type capacitor cells according to the integration density, both of which are converted into a three dimensional structure from the conventional planar capacitor cell structure. However, while effective in 4Mb DRAM devices, these methods experience limitations when applied to 16Mb DRAMs. In addition to this, the stack-type capacitor cell has a severe problem with step, because the capacitor is stacked over the transistor. Similarly, the trench type capacitor cell suffers from current leakage between the trenches due to its scaled-down size. Both techniques exhibit problems when applied to 64Mb DRAMs.
Therefore, new capacitor structures such as stack-trench type capacitors, fin-structured capacitors, box- n 13 structured capaleitors s p re a cl s t a c k. capacitors etc.. are proposed to solve problems in manufacturing large capacity DIR-Ws. However, due to design ru I e limitations and complicated processes, these attempts to increase capacitance by improving the structure of the storage electrode are inadequate to achieve the ne\t generation devices wh i ch require higher integration density. Therefore. even newer capacitor structures are required.
To meet the requirement. a method is proposed, where i n increased capacitance is attained using the characteristics of the storage electrode material itself and does not depend on improvements of the storage electrode's structure. This method can be understood through "A New Stacked Capacitor Structure Using Hemi-Spherical Grain (HSG) Poly- Silicon Electrodes" (H. Watanabe, N. Aoto, S. Adachi, T. Ishijima, E. Ikawa and K. Terada. SSIXI, 1990, pp. 873-876) as reported by INEC Co. and "Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode" (Yoshio Hayashide, Hiroshi Miyatake, Junichi Mitsuhashi, Makoto Birayama, Takashi Higaki and Haruhik-o Abe, SSDM, 1990, pp. 869- 872) as reported by Mitsbishi Co. These two reports teach that to increase cell capacitance, surface area of the storage electrode has to be increased, which can be achieved by enlarging the morphology of the polycrystalline silicon used as the storage electrode. In other words, the above investigators noticed that when polycrystalline silicon constituting the storage electrode is deposited using low- 4 pressure chemical vapor deposition (LPCVD), the surface morphology of the deposited polysilicon exhibits the greatest increase at the phase transition temperature where the amorphous silicon changes to polycrystalline silicon. In this case, however, in addition to the deposition temperature and pressure of the polysilicon, its thickness also plays a major role in changing surface morphology, and so certain applications of this technique to various capacitor structures are impeded. Also, electrostatic concentrations appear, at an inflection point between the HSG grains resulting from the unevenness in the storage electrode's surface, which downgrades the electrical characteristics of the dielectric layer and its reliability.
Therefore, the object of this invention is to provide a method of manufacturing a capacitor which can increase capacitance using a highdielectric material to solve the problems of conventional techniques as above.
According to the present invention there is provided a method of manufacturing a capacitor of comprising a step of -forming an a-type silicon carbide (Sic) layer on a first conductive layer serving as the first electrode, and a step of forming a second conductive layer serving as the capacitor's second electrode, on the a-type Sic layer.
Embodiments of the present invention are described below, by way of example referring to attached drawings, in which:
Fig. 1 is a cross-sectional view of a capacitor employing an O/SiC(a)structured dielectric layer according 1 to an embodiment of the present invention.
Fig. 2 is a cross-sectional view of a capacitor that employs an 0/SiC(a)/SiCxOy-structured dielectric layer according to an embodiment of the present invention.
The dielectric constant of a-type silicon carbide (hereinafter referred to as SiC(a)) is 10.2, superior to an oxide layer by 2.6 times and to a nitride layer by 1.36 times. That is, for a given thickness of the dielectric layer using SiC(a), capacitance will increase 2.6 times as compared with the oxide layer, and 1.36 tines over the nitride layer.
The method of manufacturing an SiC(a) obtained by the reaction equation 1 below.
SiC14 + CH4 --' S'C(') + HC1 - - - - - (Eq. 1) layer can be Two methods use an SiC(a) layer obtained through equation 1 as the dielectric layer of the capacitor as shown in Figs. 1 and 2. One method uses only the SiC(a) layer as illustrated in Fig. 1. Fig. 2 shows the other method which uses a SiC(a) layer plus a SiCxOy layer which is obtained by forcibly oxidizing the surface of the SiC(a) layer of Fig. 1.
Referring to Fig. 1, a natural oxide layer 11 about 15A thick is formed on a first conductive layer 10, such as, for example, an impurity-doped, polycrystalline silicon layer, which is used as the first electrode of a capacitor, followed by a SiC(a) layer 12 of about 70A which is obtained through 6 equation 1. On this structure, a second conductive layer 20, for example, another impurity-doped polycrystalline silicon used as the second electrode of the capacitor, is formed.
Referring to Fig. 2 wherein a method using both SiC(a) layer and SiCxOy layer is illustrated, after forming the first conductive layer 10, the natural oxide layer 11 and the SiC(a) layer 12 of approximately 70A depth as shown in Fig. 1 are formed in cited order and then the SiC(a) layer is forcibly oxidised, creating an SiCxOy layer 13 of approximately 12k. Subsequently, the second conductive layer 20 is formed on the resultant structure. In Fig. 2, I'd" represent the thickness of the SiC(a) layer which was consumed when it was forcibly oxidized.
Table 1, compares the capacitances achieved when the dielectric layer is formed with the SiC(a) layer according to embodiments of the present invention with those obtained via conventional methods wherein the dielectric layer is formed with an oxide nitride oxide (ONO) layer structure, which are generally used for large capacity memory devices. Here, the data is arranged in terms of measured values and expected values, each of which is applied to the stack structure and single stack wrapped (SSW) structure of 16Mb DRAM cell capacitors.
1 <Table l>
Capacitor T(dielectric cell blethod structure layer) capacitance [A] [fF] conventional ONO stack structure 59.5 19.0 structure T(N)=70A measured values) SSIV structure 68.94 23.8 T(N)=80A 0/SiC(a) structure stack structure 41.76 30.7 (expected values, T(Sic(a))=70A S9Y structure 45.58 36.81 Ti,Sic(a))=80A 0/SiC(a)/SiC--,Cv stack structure 52.11 24.65 structure T(Sic(a))=70A (expected values) S&V structure 53.26 31.5 T(Sic(a))=80A In Table 1, T (N) represents the thickness of the nitride layer, T(SiC(a)) the thickness of the SiC(a) layer and T(dielectric layer) the thickness of the dielectric layer which i s interposed between the first and second electrodes of the capacitor. In addition, the O/SiC(a) structure represents tbe.structure composed of the natural oxide]ayer and the SiC(a) layer as illustrated in FIG.1, while the O/Si(a)/SiCxOy structure represents the structure composed of the natural oxide layer, the SiC(a) layer and the SiCxOy layer as shown in FIG. 2.
It is noted from Table 1 that further imptoved capacitances can be obtained by using SiC(a) of the present 8 method as conventional Here. the compared xvith using ONO method.
structure of the dielectric layer thicknesses of the conventional 0.N.O structure as well as their capacitance are electrically measured values. Expected values of the SiC(a) layer structure of the present invention can be obtained by the following calculations:
C = E A yer) T (dielectric la,, ' where. C = capacitance, E = dielectric constant (r=o x Er) A = electrode surface area, and T (dielectric layer) = the thickness of dielectric layer Since A x (eo x er) is constant for a determined capacitor structure and dielectric layer, capacitance can be obtained for a given thickness of the dielectric layer. For example, 1) For an O/SiCW structure and stack structure, T(SiC(a)'. = 70A T(dielectric layer) = T(natural oxide layer) + T(SiC(a)) 3.9 15A + --- 70A 10.2 41.76A then.
C = 30.7 fF/cell 9 2 ') For an 0/SiC(a) SiWy structure (when the forcibly oxidized layer is formed to about a 12A thickness) and stack structure.
T(SiC(a)) = 70A T(dielectric layer) = T(natural oxide layer) + T(SiCW) T(SiCxOy) 3.9 10.2 = 52. 11A then, (70A - 4.32A) + 12A C = 24.65 fF/cell Here. the figure 4.32A approximates the consumed thickness of the SiC(a) layer when forced to oxidize.
In the above example, the capacitor's second electrode is a polycrystalline layer doped with impurities after polycrystal silicon layer was deposited followed by a process of ion implantation. However. when impurities are ion-implanted, they can infiltrate the dielectric layer, and lower the electrical characteristics of the dielectric layer. To prevent this, an insitu-doped polycrystalline silicon layer may be used.
As described above, the method of manufacturing a capacitor in accordance with the present invention is to use a high-dielectric material SiC(a) as the capacitor's dielectric layer to increase memory cell capacitance. In addition. a margin of error is obtained for the process, because a very thin dielectric layer is not required when materials of a low dielectric constant are used as the dielectric layer. which enables an increased yield as compared with the conventional method.

Claims (7)

CLAIMS:
1. A method of manufacturing a semiconductor device comprising the steps of:
forming an a-type silicon carbide layer on a first conductive layer, said first conductive layer serving as a first electrode of a capacitor; and forming a second conductive layer serving as a second electrode of said capacitor, on said a-type silicon carbide layer.
2. A method of manuf acturing a semiconductor device as claimed in claim 1, further comprising forming a forcibly oxidized silicon carbide layer by forcibly oxidizing the upper portion of said a-type silicon carbide layer.
3. A method of manufacturing a semiconductor device as claimed in claim 1 or 2, wherein said a-type silicon carbide layer is obtained by reacting silicon tetrachloride with methane.
4. A method of manufacturing semiconductor device as claimed in any preceding claim, wherein said second conductive layer comprises an in situ-doped polycrystalline silicon layer.
5. A method of manufacturing a semiconductor device substantially as hereinbefore described with reference to Figures 1 and/or 2 of the accompanying drawings.
12
6. A semiconductor device comprising an a-type silicon carbide layer formed on a first conductive layer, said first conductive layer serving as a first electrode of a capacitor; and a semiconductive layer, serving as a second electrode of said capacitor f ormed on said a-type silicon carbide layer.
7. A semiconductor device substantially as hereinbefore described with reference to Figure 1 and/or Figure 2 of the accompanying drawings.
7. A semiconductor device substantially as hereinbefore described with reference to Figure 1 and/or Figure 2 of the accompanying drawings.
c - 1,2)- Amendments to the claims have been filed as follows 6. A semiconductor device comprising an a -type silicon carbide layer formed on a first conductive layer, said first conductive layer serving as a first electrode of a capacitor; and a second conductive layer, serving as a second electrode of said capacitor formed on said a type silicon carbide layer.
GB9124626A 1991-06-12 1991-11-20 Method for manufacturing semiconductor device capacitor Withdrawn GB2256747A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009682A KR930001428A (en) 1991-06-12 1991-06-12 Manufacturing Method of Semiconductor Device

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GB9124626D0 GB9124626D0 (en) 1992-01-08
GB2256747A true GB2256747A (en) 1992-12-16

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JP (1) JPH04369264A (en)
KR (1) KR930001428A (en)
DE (1) DE4136303A1 (en)
FR (1) FR2677810A1 (en)
GB (1) GB2256747A (en)
IT (1) IT1252285B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2370412A (en) * 2000-12-19 2002-06-26 Samsung Electronics Co Ltd Manufacturing capacitor of semiconductor memory device by two-step thermal treatment

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818071A (en) * 1995-02-02 1998-10-06 Dow Corning Corporation Silicon carbide metal diffusion barrier layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897710A (en) * 1986-08-18 1990-01-30 Sharp Kabushiki Kaisha Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5978553A (en) * 1982-10-27 1984-05-07 Hitachi Ltd Capacitor and manufacture thereof
JPS60242678A (en) * 1984-05-17 1985-12-02 Seiko Epson Corp Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897710A (en) * 1986-08-18 1990-01-30 Sharp Kabushiki Kaisha Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2370412A (en) * 2000-12-19 2002-06-26 Samsung Electronics Co Ltd Manufacturing capacitor of semiconductor memory device by two-step thermal treatment
US6472319B2 (en) 2000-12-19 2002-10-29 Samsung Electronics Co., Ltd. Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment
GB2370412B (en) * 2000-12-19 2002-11-06 Samsung Electronics Co Ltd Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment

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Publication number Publication date
DE4136303A1 (en) 1992-12-17
JPH04369264A (en) 1992-12-22
ITMI913097A1 (en) 1993-05-20
KR930001428A (en) 1993-01-16
GB9124626D0 (en) 1992-01-08
ITMI913097A0 (en) 1991-11-20
FR2677810A1 (en) 1992-12-18
IT1252285B (en) 1995-06-08

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