GB2252879A

GB2252879A - Frequency synthesisers

Info

Publication number: GB2252879A
Application number: GB9207347A
Authority: GB
Inventors: Brian Gardner
Original assignee: Racal Research Ltd
Current assignee: Racal Research Ltd
Priority date: 1988-04-15
Filing date: 1992-04-03
Publication date: 1992-08-19
Anticipated expiration: 2012-04-03
Also published as: GB9207347D0; GB2252879B

Abstract

In a frequency synthesiser of the phase lock loop type including a VCO 20, a phase comparator 24, a loop filter 28, a variable divider 22, the division factor is cyclically varied by a control arrangement 50-58 responsive to a desired value of the output frequency to derive a first part which sets the division factor to an integral multiple and to derive a second part applied to accumulators 52A-52D connected in cascade and operable to cyclically vary the division factor in a manner to reduce the jitter on the control signal caused by the variation, and at least one of the accumulators 52C, 52D is smaller in size than a preceding accumulator. <IMAGE>

Description

FREQUENCY SYNTHESIZERS The invention relates to frequency synthesizers.

According to the invent ion, there is provided a frequency synthesiser, comprising a voltage controlled oscillator producing a synthesised output frequency, a divider having a variable division factor and connected to receive and divide the output frequency, a phase comparator connected to compare the phase of the divided output frequency and the phase of a reference frequency whereby to generate an error signal dependent on the error between them, a loop filter connected to filter the error signal and to apply it to the voltage controlled oscillator as a control signal therefor for adjusting the output frequency in a direction and by an amount tending to reduce the error signal to zero, and control means for cyclically varying the division factor of the divider at such a rate that its average value produces a desired value for the output frequency to a significance which is a fraction of the value of the reference frequency, the control means being responsive to a desired value of the output frequency to derive therefrom a first part thereof which is an integral multiple of the reference frequency and to set the division factor to a number equal to that multiple, and to derive a second or remaining part, first accumulator means responsive to the remaining part for producing the said cyclical variation in the division factor, and a plurality of further accumulator means each connected to receive and integrate the contents of the preceding one, each further accumulator means producing successive increases and decreases in the division factor within the period of the cyclical variation of the division factor caused by the first accumulator means whereby to reduce the jitter on the control signal caused by the said cyclical variation, at least one of the further accumulator means having a size which is smaller than the size of the accumulator means preceding it in the cascade.

Digital circuit arrangements and frequency synthesizers embodying the invention will now be described, by way of example only, with reference to the accompanying diagrammatic drawings in which: Figure 1 is a block diagram of one of the circuit arrangements; Figure 2 is a block diagram showing a modified form of the circuit arrangement of Figure 1; Figure 3 shows circuit arrangements of the form shown in Figure 2 connected in cascade; Figure 4 is a block circuit diagram showing the circuit arrangement of Figure 1 arranged to control a frequency synthesiser; Figure 5 is a modified version of the circuit of Figure 3 for explaining the cancellation of phase noise; and Figure 6 shows a modified form of the circuit arrangement of Figure 4.

In Figure 1, an adder 5 has one of its inputs 6 connected to receive a digital input signal F. The adder has two outputs 8 and 10 producing outputs M and L respectively, and the second input of the adder, input 12, is fed with a signal derived from the output L via a digital filter 14. Using conventional notation, the filter 14 operates in accordance with a function G(z) -l (where z 1 is a delay equal to the sampling period), and the output of the filter 14 is therefore L.G(z) and is applied to the adder on the input 12.

Therefore, F + L.G(z) = M + L (1) This therefore gives a value for M as M = F - L.(1 - G(z)) (2) In the general case, the relationship between M and L can be arbitrarily chosen. However, advantageously, M is the most significant part of the adder output while L is the least significant part.

In this example, therefore, M cyclically varies between limits so that its average value represents the value of F. M can therefore be considered to be a low precision representation of F. The- difference, Fe, between F and M is therefore given (from Equation 2) by F = F - M - L.(1 - G(z)) (3) e F can be regarded as a frequency error and the e corresponding phase error, e' is given by = IJ.(1 - G(z))/(1 - z1) (4) Equation (4) is obtained by integrating Fe, integration being achieved by dividing by (1 - z 1) in the normal manner for digital filters.

The signal L likewise varies between upper and lower limits. If its total magnitude variation is B, then an assumption can be made that the upper limit on the phase error is given by b' where = = S.(1 - G(z))/(l - z-l) (5) where S is a square wave of peak to peak amplitude B and of frequency f. Such a signal will have a spectral component at a frequency f of 2B/ . This is thus the upper limit on the spectral content of any frequency f in the signal L.

In this way, a circuit is therefore produced which generates a sequence of low precision numbers (M) from a high precision number (F), and in which the difference between the low precision and high precision numbers has a known spectral shape and known phase error given as explained above.

Such a circuit can be used in a variety of applications. For example, it can be used for digital to analogue conversion, by applying digital to analogue conversion to the signal M so as to give an analogue output representative of the signal F but with known phase error and spectral content and obtained by relatively simple processing of the low precision number M rather than the more complex processing required for the high precision number F.

In practice, it may be advantageous to reduce the precision of the coefficients of G(z) and/or the signal at any point. This has the effect of adding quantisation noise to the output. This is illustrated in Figure 2 where Q now represents the quantisation noise or least significant part and L is the remaining part.

Therefore, Equation (1) now becomes: F + L.G(z) = M + L + Q (6) Equation (2) becomes M = F - L.(1-G(z)) - Q (7) By analogy, Fe (Equation (3)) becomes F = F - M = L.(1-G(z))) + Q (8) e The phase error, e' is now given by = L.(1-G(z)/(l-z l)+Q/(l-z ) (9) Signal L is now of limited precision. The discussion above, with reference to Equation (5), concerning signal L, now applies to signal Q. Q is amplitude-limited and has a flat spectral bound. Being spectrally flat, Q can have a D.C. component which (from Equation (8)) results in a frequency error. The integration involved in producing Equation (9) implies a potentially infinite phase error. Therefore, for a one-stage system (as illustrated in Figures 1 and 2), Q must be zero, that is, the full precision of signal L must be used.

However, circuit arrangements of the form shown in Figure 1 or 2 can be connected in cascade so as to produce an overall output of the same form as the output described above for the circuit of Figure 1. For such multi-stage systems, limited precision may be used for L.

Figure 3 shows such a cascade connection.

In Figure 3, the outputs of adder 5 are now designated M1, L1 and Q1 and the operating function of the digital filter 14 is designated Gl(z). As shown, the output L1 is fed as one input into an adder 5A which produces outputs M2, L2 and Q2. Output L2 is fed back through a digital filter 14A to produce a second input, L2.G2(z), for the adder 5A, where G2(z) is the operating function of the digital filter 14A.

If M1 is fed into one input of an adder 16 whose other input is fed through a digital filter 18 with signal M2, the overall output, P, is given by the following, assuming that the operating function of the digital filter 18 is (1 P = M1 + M2.(1 - Gl(z)) (10) In addition, M2 = L1 - L2 (1 - G2(z)) - Q2 (11) Similarly, M1 = F - Ll.(l - Gl(z)) - Q1 (12) Substituting Equations 11 and 12 into Equation 10, P = F - L2. (1 - Gl(z)).(l - G2(z)) (13) - Ql - Q2.(1-Gl(z)) This corresponds to a frequency error (F-P) of Fe = L2.(1-Gl(z)).(1-G2(z)) + Ql+Q2(1-Gl(z)) (14) and a phase error of #e = [L2 #(1-Gl(z)).(1-G2(z))+Q1+ Q2.(l-Gl(z))/(l-z ) (15) Equations (14) and (15) show that to prevent an infinite phase error, Q1 must be zero. However, Q2 is modified -l by the factor (l-Gl(z))/(l-z ). Therefore, by choosing Gl(z), the spectral shape of the phase noise caused by Q2 can be modified. Of course, the magnitude of Q2 affects the precision used for L.

The foregoing analysis can be extended to any number of cascaded stages.

Figure 4 shows a circuit arrangement of the form shown in Figure 1 used as part of a frequency synthesiser.

As shown in Figure 4, a frequency synthesiser includes a voltage controlled oscillator (VCO) 20 whose output is fed through a divider 22, having an adjustable division factor of N, to one input of a phase comparator 24. The other input of the phase comparator is fed with a reference signal having a frequency Fr The frequency comparator 24 produces an output on a line 26 dependent on the sign and magnitude of the phase error between the two signals compared. The output of the synthesiser is taken on a line 30.

The output frequency, Fo, of the synthesiser on line 30 is varied by varying the division factor N of divider 22. Such variation is achieved by controlling N in dependence on the signal M produced from the adder 5.

If the division factor N is varied by unity (the minimum possible, of course), the output frequency on line 30 will change by Fr. Therefore, in order to produce a smaller step change, it is necessary to vary N cyclically so as to produce an average value for N corresponding to the output, Fo, required.

Accordingly, the signal F which is input to adder 5 is set to represent the desired frequency Fo to high precision and the adder operates so as to produce M as the most significant part of the adder output and L as the least significant part. For example, if Fr is in MHz, F can represent the desired frequency to the nearest Hz. Because of ' the operation of the feedback loop around the adder 5, the signal M will vary cyclically so as to give the required cyclical variation of N necessary to produce the correct value for F .

However, such cyclical variation in N gives rise to jitter at the output of divider 22 and this produces a correspondingly varying output on line 26. After filtering by the loop filter 28, this varying signal is applied to the VCO and produces phase noise on the output F .

In accordance with Equation (4) above, however, the amount of this phase error and its spectral content are limited (Equation (5)). In this way, therefore, a "fractional N" frequency synthesiser can be produced with known and controlled phase error. Advantageously, the phase error and its spectral content can be designed so as to be substantially removed by the loop filter 28.

Figure 5 illustrates a modified form of the frequency synthesiser of Figure 4 in which items corresponding to those in Figure 4 are similarly referenced. The synthesiser of Figure differs from that shown in Figure 4 in that it employs means for cancelling the phase noise. As shown, the output from divider 22 is fed to phase comparator 24 via a phase modulator 32, phase modulator 32 being in turn fed with a phase error correction signal on a line 34 which is derived via a processor 36 from the signal L.

Equation (4) above shows that a signal representing phase error can be generated from the signal L by multiplying the latter by (1 - G(z))/(l - z 1). Such a multiplying factor is generated on a line 38 and fed into processor 36 and therefore produces on line 34 a value for the correction signal equal to the phase error. This is thus fed into the loop via the phase modulator 32 to cancel the phase error. Digital to analogue conversion may be involved in this process.

Instead, the correction signal could be fed into the loop at another point. For example, a corresponding signal voltage could be generated and added in the appropriate sense to the correction signal generated by the phase comparator 24.

If all components are perfect, exact cancellation of phase noise is achieved. In such a case, the form of G(z) is irrelevant. In practice, however, it may be difficult to achieve perfect cancellation. Improvements of the order of 20 to 30 dB can be achieved nevertheless. Any error in phase noise cancellation will produce phase noise with the spectral shape of (1 G(z))/(l - z-1).

The circuit arrangements described thus allow a synthesiser to achieve arbitrarily small frequency increments with a high reference frequency. The use of a high reference frequency implies a wide loop bandwidth for the phase locked loop and the VCO will therefore follow variations in F with high precision. This enables the circuit arrangement of the form shown in Figure 4 or Figure 5 to be used as a high precision frequency or phase modulator, and a frequency response down to DC can be achieved.

The foregoing description with reference to Figures 4 and 5 assumes that the quantisation noise signal Q (see Figure 2) is zero. However, the systems of Figures 4 and 5 can be modified by using cascaded arrangements of the form shown in Figure 3, instead of the single stage of Figure 1, and this enables the quantization noise of the second (and any subsequent) stages to be non-zero if the resultant spectral shape of the phase noise can be made acceptable by a suitable choice of G(z).

Thus, such a cascaded arrangement of adders corresponds to a cascaded arrangement of accumulators such as shown for example in GB-PS-2 026 268 which describes a "fractional N" type of ' synthesizer with two cascaded accumulators receiving a signal representing the desired frequency value. The "carry" outputs of the accumulators appropriately processed and are summed and control the frequency of the divider in the phase-locked loop. The first accumulator produces the necessary periodic variation in the division factor of the divider so that its average value is the value necessary to produce the desired output frequency. The second accumulator integrates the contents of the first accumulator and produces signals which cause further variations of the division factor so as at least partially to back-off the "jitter" in the output of the phase detector resulting from the division factor changes caused by the first accumulator. In such an arrangement, additional accumulators may be added in cascaded form for the purpose of reducing such jitter still further.The above analysis in relation to Figure 3 of the present application, which shows that the quantization noise (represented by Q1, Q2 in Figure 3) can be non-zero for stages after the first one (if its spectral shape is suitably chosen), shows that in an implementation using cascaded accumulators as described above, the second and subsequent accumulators can be successively smaller in size (corresponding to the allowable values for Q2...Qn), thus achieving significant savings in hardware.

Figure 6 shows in diagrammatic form such an implementation, and items in Figure 6 corresponding to items in Figure 4 are similarly referenced.

As shown in Figure 6, the input signal F is fed to an adder 50 and also to the first one, 52A, of four (in this example) cascaded accumulators 52A, 52B, 52C and 52D. The output of the adder 50 on a line 51 is connected to control the division factor of the divider 22. The accumulators are clocked by a signal derived from the reference frequency Fr. When accumulator 52A becomes full, it will produce a "carry" signal on line 54 which, by means of the adder 50, causes a periodic variation in the division factor of the divider 22 so as to cause the average value of the divider to be such as to produce the required value for the output frequency on the line 30. For a more detailed explanation of this, references made to the above-mentioned GB-PS-2 026 268.

Each of the succeeding accumulators 52B, 52C, 52D integrates the contents of the previous accumulator. In the manner explained in more detail in GB-PS-2 026 268, the carry signal on line 56 from the second accumulator 52B is arranged, in combination with a delay circuit indicated generally at 58, to produce sequentially a unit increase and a unit decrease, on a channel 60 in the division factor of divider 22 during each period of variation in the division factor caused by accumulator 52A. The unit increases and decreases caused by the signals on channel 60 reduce the jitter in the output on line 26 from the phase detector 24 caused by the periodic variations in N. In an analogous manner, accumulators 52C and 52D cause further increases and decreases in the division factor N during its basic period of variation and provide further reduction in the jitter on the signal on line 26.As shown in Figure 6, the sizes of accumulators 52C and 52D are successively reduced as compared with the sizes of accumulators 52A and 52B because, as described above and in relation to Figure 3, quantization noise (the production of which will stem from the successive reduction in size of the accumulators of 52C and 52D) can be non-zero if the resultant spectral shape of the phase noise can be made acceptable ty suitable choice of G(z).

There may of course be less or more than the four accumulators shown in Figure 6.

In the more general case, implementation shown in Figure 6 corresponds to an implementation of the Figure 4 circuit with a cascaded arrangement of adders 5, 5A...

(as shown in Figure 3) instead of the single adder 5 of Figure 4, but with the digital filters 14, 14A... (Fig.

3) implemented by arrangements in which the filter coefficients are produced with successively reduced precision.

This application is divided from Application No.

8828947.5 (Serial No. 2217535) which relates to a frequency synthesiser comprising a voltage controlled oscillator (VCO) producing a synthesised output frequency, a divider having a variable division factor and connected to receive and divide the output frequency, a phase comparator connected to compare the phase of the divided output frequency and the phase of a reference frequency whereby to generate an error signal dependent on the error between them, a loop filter connected to filter the error signal and to apply it to the VCO as a control signal therefor for adjusting the output frequency in a direction and by an amount tending to reduce the error signal to zero, and control means for cyclically varying the division factor of the divider at such a rate that its average value produces a desired value for the output frequency to a significance which is a fraction of the value of the reference frequency, the control means comprising a two-input digital adder to one of whose inputs is applied a digital input signal having a value representing the desired value of the output frequency to the said significance, the adder having outputs at a first one of which is produced a first output signal representing the most significant part of the digital input signal and at a second one of which is produced another output signal representing the least significant part of the digital input signal to a predetermined precision dependent on quantisation noise present, the said second output signal being fed back to the second input of the adder through a digital filter having a predetermined operating function such that the difference between the said first output signal and the digital input signal varies with a predetermined spectral shape dependent on the function of the digital rilter, the first output signal being fed to control the changes in value of the division factor of the divider correspondingly.

Application No. 8828947.5 also relates to a digital circuit arrangement, comprising an adder with first and second inputs and having an input signal applied to the first input and whose output is divided into parts, one of which is fed back to the second adder input through a digital filter having a predetermined operating function (G(z)) so that another part of the output varies in such manner that the spectral shape of its difference from the input signal is predetermined and related to G(z), the said other part of the output representing the most significant part of the input signal.

Claims

1. A frequency synthesiser, comprising a voltage controlled oscillator producing a synthesised output frequency, a divider having a variable division factor and connected to receive and divide the output frequency, a phase comparator connected to compare the phase of the divided output frequency and the phase of a reference frequency whereby to generate an error signal dependent on the error between them, a loop filter connected to filter the error signal and to apply it to the voltage controlled oscillator as a control signal therefor for adjusting the output frequency in a direction and by an amount tending to reduce the error signal to zero, and control means for cyclically varying the division factor of the divider at such a rate that its average value produces a desired value for the output frequency to a significance which is a fraction of the value of the reference frequency, the control means being responsive to a desired value of the output frequency to derive therefrom a first part thereof which is an integral multiple of the reference frequency and to set the division factor to a number equal to that multiple, and to derive a second or remaining part, first accumulator means responsive to the remaining part for producing the said cyclical variation in the division factor, and a plurality of further accumulator means each connected to receive and integrate the contents of the preceding one, each further accumulator means producing successive increases and decreases in the division factor within the period of the cyclical variation of the division factor caused by the first accumulator means whereby to reduce the jitter on the control signal caused by the said cyclical variation, at least one of the further accumulator means having a size which is smaller than the size of the accumulator means preceding it in the cascade.

2. A synthesiser according to claim 1, in which the sizes of the further accumulator means are successively smaller.

3. A frequency synthesiser, substantially as described with reference to Figure 6 of the accompanying drawings.