GB2234610A

GB2234610A - Address mapping arrangement

Info

Publication number: GB2234610A
Application number: GB8917648A
Authority: GB
Inventors: Anthony John Matthews; Bryan Hicks
Original assignee: Research Machines PLC
Current assignee: Research Machines PLC
Priority date: 1989-08-02
Filing date: 1989-08-02
Publication date: 1991-02-06
Anticipated expiration: 2009-08-02
Also published as: GB2234610B; GB8917648D0

Abstract

An address mapping arrangement for a computer with memory configurable as expanded memory comprises: an untranslated address bus 5; a mapper chip 2 connected to the address bus for translating addresses it receives therefrom; a bus controller 4 connected to the address bus 5 for controlling access to bus devices 8 and a memory controller 3 connected to the mapper chip 2 and to the bus controller 4 and being arranged so that on receiving a translated address, it either initiates a memory cycle or provides a control signal to enable the bus controller 4 to initiate a bus cycle depending whether the translated address falls within a given address space or outside that space. <IMAGE>

Description

ADDRESS MAPPING ARRANGEMENT This invention relates to an address mapping arrangement for a computer with memory configurable as expanded memory in accordance with the industry standard expanded memory system (EMS).

In a conventional arangement of a personal computer, the address space consists of: 1) 0 - 640K: conventional read/write memory 2) 640K - 768K: video read/write memory devices 3) 768K - 896K: memory mapped input/output (I/O) devices 4) 896K - 960K: user option read only memories (ROMs) 5) 960K - 1024K: basic I/O system ROMs (Items 2, 3 and 4 correspond to the I/O devices and options referred to below) An inherent feature of personal computer architecture is that due to the placement of the video random access memory tRAM) in memory address space at A0000, many applications are limited to using memory only up to 640K.

It is often desirable to have more memory than this in order to use larger packages but still conform to these address limitations.

This is conventionally accomplished by fitting add-on expanded memory boards, configured by jumpers and links, to lie at areas of address space which should be reserved for I/O devices and other options. This creates the possibility of error by the mis-setting of the jumpers and a loss of flexibility as to where the memory resides in address space.

Alternatively, the extra memory can be placed in address locations alongside and higher than the reserved address space and one or more mapping devices used to access it. A mapping device works by intercepting the normal memory range addresses emerging from the microprocessor and converting them to selectable address ranges within an expanded memory. The system must, however, be configured to avoid overlap between accesses to this expanded memory and to the various I/O devices and options.

The conventional method of solving this problem is to design the mapping device to enable it to be configured for various addresses to avoid overlap with I/O devices or options. This requires, even in its most efficient implementation, a large increase in the number of logical circuits in the mapping device and additional control lines, so increasing the complexity of the device. The cost of this approach is therefore high.

This invention aims to optimise the architecture of personal computers which make use of an address translating device and 8 memory controller in order to map addresses into an expanded memory.

According to a first aspect of the invention, there is provided an address mapping arrangement for a computer with memory configurable as expanded memory comprising: an address bus for carrying untranslated addresses; a mapping device connected to the address bus for translating addresses it receives therefrom; bus device control means connected to receive untranslated addresses from the address bus for controlling access to bus devices and memory control means connected to the mapping device and to the bus device control means for receiving translated addresses from the mapping device, initiating memory cycles and providing a control signal to the bus device control means, the arrangement being such that on receiving a translated address, the memory control means is arranged either to initiate a memory cycle or to provide a control signal to enable the bus device control means to initiate a bus cycle depending whether the translated address falls within a given address space or outside that space.

According to a second aspect of the invention, there is provided an address mapping arrangement for a computer with a memory configurable as expanded memory comprising: an address bus for carrying untranslated addresses; bus device control means connected to receive untranslated addresses from the address bus for controlling access to bus devices and memory control means associated with an add-on memory location for receiving translated addresses, initiating memory cycles and providing a control signal to the bus device control means, in combination with a plug-in mapping device for translating addresses received from the address bus and providing translated addresses to the memory control means, the arrangement being such, when the mapping device and add-on memory are installed, the memory control means is arranged either to initiate a memory cycle or to provide a control signal to enable the bus device control means to initiate a bus cycle depending whether the translated address it receives falls within a given address space or outside that space.

Preferred features of the invention will be apparent from the following description and from the subsidiary claims of the specification.

The invention will now be further described, merely by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of the system architecture of a personal computer including an arrangement according to an embodiment of the invention; and Figure 2 is a diagram illustrating the address space as seen by components of the arrangement shown in Figure 1.

Figure 1 shops the layout of the functional parts of the system and the logical communication busses which interlink these to the central processor unit.

The system may, for example, be used in relation to two personal computer mainboards manufactured by Research Machines Limited: the PC-286 and the PC-386SX mainboard. In a typical application, a large package may require an expanded memory of 8 Megabytes (MB). In this case, the addresses generated by the processor will be in the range 0 - 1MB and need to be translated to addresses within an expanded space of 8MB.

Figure 1 shows a central processing unit (CPU) 1, a mapper chip 2, a memory controller 3 and a bus controller 4. The mapper chip 2 and the bus controller 4 are both connected to an untranslated address bus 5 to receive untranslated addresses from the CPU 1. The memory controller 3 is connected to a translated address bus 6 to receive translated addresses from the mapper chip 2. The memory controller 3 is also connected to the bus controller 4 by a control line 7.

I/O devices or other options 8 are connected to the bus controller 4 and an expanded memory 9 is connected to the memory controller 3. A direct memory access (DMA) controller 10 may also be connected to receive ortransmit untranslated addresses to and from the bus 5.

The illustrated system is arranged to operate with the CPU 1 providing accesses within the address space from 0 to 1 Megabyte (MB). Addresses within this address space are thus received by the mapper chip 2, the bus controller 4 and the DMA controller 10.

The mapper chip 2 is arranged to translate these addresses into an expanded address space from 0 to 16MB and the translated addresses are received by the memory controller 3.

The memory controller 3 is arranged so that addresses received within a given address space, for example 8 - 16MB, are understood to be intended for bus devices, is I/O devices and options. In this case, the memory controller 3, provides a control signal on line 7 to enable the bus controller 4 to act upon the corresponding untranslated address it receives directly from the bus 5. Addresses received outside the given address space, in this case 0 to 8MB (corresponding to the available memory), are understood to be intended for memory and thus passed to the appropriate memory location. In this way a clash between memory and bus devices at the same untranslated address is avoided.

For convenience, addresses for bus devices (between 640K and 1MB) are mapped to a given area of translated address space just beyond the 8MB level, this being referred to as the memory disable frame MD. However, it will be appreciated that the memory disable frame MD may be at any designated address within the translated address space.

Figure 2 shows the relationship between the address space seen by the CPU 1 and that seen by the memory controller 3. The mapper chip is responsible for translating between the two.

Operation of the device will now be further described in relation to two example accesses, one to a bus device at a given address XX and another to expanded memory at the same address XX.

Access to a bus device at address XX Consider an access to a device, for example a video-page VP, residing at an address XX (within the range 640K - 1MB) which is to be managed by the bus controller 4. The CPU 1 will generate this address on the address bus 5 and the signal will arrive both at the mapper chip 2 and the bus controller 4.

The mapper chip 2 is pre-programmed (eg by driver software) to convert the address XX to an address within the memory disable frame MD. This translated address is then passed to the memory controller 3.

The memory controller 3 receives the address, MD, which lies outside the range 0-8MB for the available memory. Thus, a signal (AF16-) is asserted on the control line 7. The translation of the address XX for the video-page VP to the memory disable frame MD is illustrated by line 11 in Figure 2.

The bus controller 4 thus receives the logical signal AF16- which causes it to initiate a bus cycle. The untranslated address XX is still present at its inputs which it then interprets to be an access to the intended device (in this case the video page VP) and the rest of the cycle proceeds in the usual way.

Access to expanded memory at address XX Consider now an access to the memory 9 which resides at the same numerical address XX as the said device. The CPU 1 again generates address XX on the address bus 5 which arrives both at the mapper chip 2 and at the bus controller 4.

The mapper chip 2 is pre-programmed (eg by the driver software) to convert the address XX in this case to an address YY in the expanded memory.

The memory controller 3 thus receives address W and recognises it as a valid memory address, and so initiates a memory cycle in the usual way but without asserting the logical signal AF16- on line 7. The translation of the address XX to the address YY in the expanded memory is illustrated by line 12 in Figure 2.

Since the signal AF16- does not arrive at the bus controller 4, it does not initiate a cycle and the address XX present at the inputs of the bus controller 4 is ignored. Hence a clash between memory at XX and the device with the same address is avoided.

The arrangement described thus involves the use of an area of address space, referred to as the memory disable frame, which when mapped into causes a bus cycle rather than an expanded memory cycle to occur so eliminating clashes between memory and I/O devices.

This is accomplished by: + A system of architecture whereby the mapper chip 2 is fitted on a spur of the address bus 5 which leads exclusively to the memory controller 3.

e The use of only those logical signals linking the mapper chip 2 to the memory controller 3 which are necessary for the normal operation of a mapping device (PA (14.23) and ADTL-); and f A logical signal generated by the memory controller 3 which is active during accesses to the memory disable frame MD. This signal is received by controlling circuitry 4 so that the appropriate state cycles may be initiated for accesses to the other devices.

The architecture, or relative layout of the system components on the information transfer busses, is significant in that the output of the mapper chip 2 is connected only to the memory controller 3 and none of the other system components.

The consequence of this is that untranslated processor addresses are supplied to the bus controller 4 so that, provided they are enabled in an appropriate way these devices will act in their intended way as if there were no mapper chip in the circuit, ie all of the bus devices will reside at their intended addresses.

As indicated above, the logical connections between the mapper chip 2 and the memory controller 3 are no more than those required for the mapping operation. More specifically, the translated address lines PA(14.23) and the control signal ADTL- (which informs the memory controller that address translations external to itself are taking place) are connected, there being no need for any further connections.

The function of the mapper chip 2 is to treat the untranslated address space and the translated address space as a series of contiguous 16KB blocks. The mapper chip 2 can be programmed to convert accesses to any 16KB block in the raw address space to a corresponding access to any of the 16KB blocks in the translated address space.

An example of a mapper chip that may be used is the 82C631 produced by Chips and Technologies, Inc.

The memory controller 3 receives only addresses which have been translated by the mapper chip 2. These translations cover 16MB of address space of which the memory controller 3 uses only the first 8MB.

If accesses outside the first 8MB of address space are made, then the logical signal AF16- is asserted.

An example of a memory controller that may be used is the 82C222 produced by Chips and Technologies, Inc.

The bus controller is connected directly to the untranslated address bus 5 from the CPU 1. Accesses to devices under its control can only be made when the appropriate cycle is initiated by the logical signal AF16- on line 7.

An example of a bus controller that may be used is the 82C22 1 produced by Chips and Technologies, Inc.

The CPU used may be an 80286 or the 80386SX produced by Intel Corporation.

The arrangement described above is conveniently implemented with the memory controller 3 fitted within the computer and associated with an add-on memory location provided for receiving additional memory. The arrangement can thus be completed by installing add-on memory and an optional mapper chip 2 into the system. The mapper chip 2 should then be enabled and driven by suitable software and any by-passing hardware (used to by-pass the connections for the mapper chip 2 when the mapper chip 2 is not fitted) is either removed or disabled.

As indicated, the mapping arrangement described can be provided using conventional components presently available on the market, ie in June 1989.

Claims

1. An address mapping arrangement for a computer with memory configurable as expanded memory comprising: an address bus for carrying untranslated addresses; a mapping device connected to the address bus for translating addresses it receives therefrom; bus device control means connected to receive untranslated addresses from the address bus for controlling access to bus devices and memory control means connected to the mapping device and to the bus device control means for receiving translated addresses from the mapping device, initiating memory cycles and providing a control signal to the bus device control means, the arrangement being such that on receiving a translated address, the memory control means is arranged either to initiate a memory cycle or to provide a control signal to enable the bus device control means to initiate a bus cycle depending whether the translated address falls within a given address space or outside that space.

2. An arrangement as claimed in claim 1 in which the mapping device is arranged to translate addresses for the available memory to addresses outside the given address space and to translate addresses for bus devices to addresses within the given address space.

3. An arrangement as claimed in claim 1 or 2 in which the bus device control means is arranged to initiate a bus cycle for an untranslated address received from the address bus only when the control signal is received from the memory control means.

4. An arrangement as claimed in claim 1, 2 or 3 in which the mapping device is connected to a spur of the address bus which leads exclusively to the memory control means.

5. An arrangement as claimed in any preceding claim in which the logical connections between the mapping device and the memory control means are no more than those required for a conventional mapping operation.

6. An arrangement as claimed in claim 2 or any claim dependent thereon with an expanded memory of 8MB in which the mapping device is arranged to translate addresses for the available memory to addresses within expanded memory in the range 0 to 8MB and to translate addresses for bus devices to addresses within the expanded memory beyond the 8MB level.

7. An arrangement as claimed in any preceding claim forming part of a computer with an expanded memory.

8. An arrangement as claimed in claim 7 in which the mapping device is enabled and driven by appropriate software and any by-passing hardware provided either removed or disabled.

9. An address mapping arrangement for a computer with a memory configurable as expanded memory comprising: an address bus for carrying untranslated addresses; bus device control means connected to receive untranslated addresses from the address bus for controlling access to bus devices and memory control means associated with an add-on memory location for receiving translated addresses, initiating memory cycles and providing a control signal to the bus device control means, in combination with a plug-in mapping device for translating addresses received from the address bus and providing translated addresses to the memory control means, the arrangement being such, when the mapping device and add-on memory are installed, the memory control means is arranged either to initiate a memory cycle or to qprovide a control signal to enable the bus device control means to initiate a bus cycle depending whether the translated address it receives falls within a given address space or outside that space.

10. An address mapping arrangement for a computer with an expanded memory substantially as hereinbefore described with reference to the accompanying drawings.