GB2233176A - Frequency synthesisers - Google Patents
Frequency synthesisers Download PDFInfo
- Publication number
- GB2233176A GB2233176A GB8913749A GB8913749A GB2233176A GB 2233176 A GB2233176 A GB 2233176A GB 8913749 A GB8913749 A GB 8913749A GB 8913749 A GB8913749 A GB 8913749A GB 2233176 A GB2233176 A GB 2233176A
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- output
- frequency
- phase
- signal
- input
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1972—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for reducing the locking time interval
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Abstract
In a frequency synthesiser, the frequency of a controlled signal source 1 is varied in a predetermined manner and the phase difference between its output and a reference signal is determined at 5 and the phase of the controlled signal and/or the reference signal is shifted such that the phase difference approaches a steady state value. The oscillator 1 is pretuned by an arrangement 10 including a sequential control circuit 11 incorporating a c.p.v. and then its output is varied in a predetermined manner. The circuit 11 adjusts the division ratio of 2 and the band-width of filler 6 during tuning and also synchronises the operation of a timing circuit 7. The relative phase difference of the controlled and reference signals is measured at 7 in a sampling manner and used to control the phase shift of 8 in between sampling. Increase in tuning is achieved in a stable manner. In a modification, the phase shifter 8 is dispensed with and the division ratio of 2 is further controlled by timing circuit 7. The frequency synthesisers may be used in telecommunication, measurement, broadcast reception etc. <IMAGE>
Description
METHOD AND CIRCUIT ARRANGEMENT FOR INCREASING THE TUNING RATE OF
FREQUENCY SYNTHESIZERS
The invention concerns a method and a circuit arrangement for increasing the tuning rate of frequency synthesizers.
The invention can be advantageously applied in areas of tele corninunication, measurement, broadcast reception, etc.The known indirect digital frequency-synthesizers consist of electroni- cally tuned oscillator, programmable frequencydivider,phase/ frequency comparator, loop-filter, reference signal source and possibly frequency change-over device. The state of art synthe- sizes with low phase noise, short tuning ti3le and and programme in fine frequency steps don't meet the user s needs in all respects. The known synthesizers, that have the above advantageous features, can be implemented in many ways.
Increasing the tuning rate of frequency is the object of patent specification DE 28 12 377. In the solution according to tioned patent specification the high slew-rate of the circuit with high time constant in the loop-filter of PLL -control cir- cuit is provided by an independent op-anp.
The main disadvantage of frequency-synthesizers is the indefini- te transient behaviour - in its duration and form - of known systems developing in a spontaneous way as a conséquense of an indefinite phase position at the initial time of the vector's operating, Therefore, it is difficult to provide for substantially shorter retuning time compared to the few 10 ms usual for the knomn frequency-synthesizer5, as well as it is need to apply substantially more complicated arrangements as theoretically required for given retuning rate /for example, multiple-loop smynthesizer mith high sampling frequency/.
The patent specification DE 27 35 642 introduces a solution for that, it is autonatically provided for changing the pit loop-filter. For tuning a high bandwith low-pass filter, in stable state - in turn - a small bandwith lor-pass filter is connected in the control circuit. The switching over isaccam lished by an independent circuit sensing the difference between instantaneous and mean value of tuning voltage of VOO/voltage controlled oscillator/.
The fractional division technique was a great step to producting a rapid frequency-synthesizer with low phase noise and high frequency resolution. It is known that, the sampling frequency limiting the achievanle bandwicth of control can be selected as higher than lowest frequancy step required to realize.
For the knox7n frequency synthesiners the low phase noise is provided bg optimal design of PLL loop-filter beyond other points of circuit. The frequency retuning is slowed down by the substantially lomer bandwith of control as theoretically achievable and the indefinite phase position spontaneous developing under the frequency transient.For experts it is known that, the control speed /tuning rate/ depends on bandwith of control .limited by sampling frequency for samplad systems
The controlled signal is tracking the changes in reference signal with an error according to degree of freedom of control and loop gain within the bandnith of control, and its attnuates the changes in reference signal according to frequency depen- dence of loop gain outside the bandnith of control.
In the last years on this area the primer object was to achieve a lovi phase noise among others - thereby filtering cut the noise voltage, coming from circuit elements, on the VCO control int.
The relative high tuning time having been developed in this eay was reduced using frequency pretuning circuit in the critical cases. An other solution of reducing the tuning time canoe got tokznown from HU patent specification No. 194454. The solu tion is to change - at the instant of tuning - the energy sto- ring element of loop filter increasing the tuning time with a new loop filter element, whose voltage is prepared by external voltage constraint according to frequency value in the new state and at the same time to change the division ratio of program- mable divider.A constant artificial signal is used for the proper work of phase detector. Tbe disadvantage of this solution is that, the preparing of nes7 loop filter needs time, undesirable switching transients are occured at the VCO control input during change over, as well as the phase position of VCO's attenuated~ signal is indefinite in consequence of delay uncertainty due to changing the division ratio of programmable divider.
In the invention in its preferred form, the tuning rate of frequency synthesizer can be increased and result in the lowest possible transient for using the sampling frequency theo reticallu necessary to achieve given tuning rate at any initial phase position, too.
The invention is based on the consideration that, there can be provo ded for a minimum phase difference surely not greater than characteristic system minimum as initial condition for phase detector instead of indefinite, spontaneous phase position.
Provided for this, the form Of transients would not be indéfi- nite, but close identical and would have minimum time demand.
A feature of the invention is to decrease the frequency of output signal and to measure the phase difference between the output signal and the reference Signal/spontaneous phase position occured at first phase comparing instant/ and to control - by phase shift - the phases of reference source
and/or output signal viith decreased frequency in order to get
signals with maximum or less phase difference to come to the inputs of phase detector in steady state of control circuit.
Thus, the phase difference between the reference signal and the output signal with decreased frequency in transient state would be stable and close to value in steady state.
Considering that, in such a way the dist beten the differences is allowed bit measuring accuracy, we recognized, the control rate can can be increased for the tine of cancelling the rained error, whereby the settling time can be reduced.
A further preferred feature of the invention is to switch the band with of phase locked loop from its operating value to a mazinum value allowed by sampling frequency during tuning time. Thus, the pretuning of the VCO producing the output signal uith an accuracy defined during design phase is accomplished in less time than sampling period.
An advantage of these features is the stability of control remains constant in spite of changing the control rate. Of course, after cancelling the remained error the fast control is not maintained and the rate of control loop is reseted according to default value.
This invention provides a method for increased ing the tuning rate of frequency synthesizers during that the phase of output signal, or its given part, of a signal source withoutput frequency controlled by electrical signal is compared to phase of a reference signal source in sampled may, the frequency and phase of signal source with output frequency controlled by electrical signal is modified through a negative feedback cont rol loop.The essence of method is the frequency of signal source with output frequency controlled by electrical signal is pretuned in a kno:wn may, the output frequency is decreased, the difference between the phases of output signal smith decreased frequency and reference signal source is measured and the phases of reference signal source and/or output signal with decreased frequency is controlled by phase shift in such a nay that, the difference approaches the value in steady state.
In a preferred version of the method, the pretuning is accomplished during tine interval between to comparing - sampling - period.
In a further preferred version of the method1 the control rate is increased in such a viay that, the bandvlith is increased within the stability range defined by sapling frequency, then the original control rate would be reset, if the difference approached the steady state value in desired degree.
The invention also provides a circuit arrangement fcr increasing the tuning rate of frequency synthesizers, which ha. signal source with output frequency controlled by electrical signal - VCO is preferred -, the output ofsignal source with controlled frequency is connected to a frequency divider with variable division ratio, those output is connected to a phase detector with its output feed back to control input of signal source with controlled frequency through a loop filter. The reference input of phase detector is connected to a reference signal source through a constant reference divider.The signal source with controlled frequency is equipped with a retuning circuit. The circuit arrangement contains a timing circuit, se signal input is connected to output of frequency divider with variable division ratio and its reference input is connected to the reference input of phase detector. The output of timing circuit is connected to the input of phase shifter and the phase shifter is inserted between the phase detector and the constant reference divider or between the frequency divider with variable division ratio and the phase detector.The pretuning circuit contains a sequential control unit, whose first data output is connected to other control input o the signal source with controlled frequency through a D/A converter, its second data output is connected to the inputs controlling the division ratio, of frequency divider uith variable division ratio. The synchron output of sequential control unit is connected to the synchron input of tiin circuit, its further synchron output is connected to the input of timer circuit. The bandwith of its loop filter is controllable and its control input is connected to the output of timer circuit.
In a preferred version Df the circuit arrangement the phase shifter is a shift-register.
The invention also provides a circuit arrangement for increasing the tuning rate of frequency synthesizers, which has signal source with output frequency controlled by electrical signal - VCO is preferred -, the output of signal source with controlled frequency is connected to a frequency divider with variable division ratio, whose output is connected to a phase detector with its output feed back to the control input of signal source wfth controlled frequenty through a loop filter.
The reference input of phase detector is connected to a reference signal source through a constant reference divider. The signal source with controlled frequency is equipped with a pretuning circuit. The circuit arrangenent contains atiiingcir- cuit, whose control input is connected to the output of frequency divider with variable division ratio and its reference input is connected to the reference input of pnse detector.
The output of timing circuit is connected to the input, controll ing the division ratio, of frequency divider smith variable division ratio. The retuning circuit contains a sequential control unit, whose first data output is connected to the control input of signal source with controlled frequency through a D/A con verter, its second data output is connected to the input, controlling the division ratio, of frequency divider TJith variable division ratio. The synchron output of seaue!ltial control unit is connected to the synchron input of timer circuit.
The bandwith of its loop filter is controllable, whose control input is connected to the output of timer circuit.
The circuit arrangenents according to this invention are used to realize the method according to this invention. There is proved during-our experinents, the phase shift can be realized in analog or digital vJay. The phase shift can be accomplished by side of reference signal source or signal source with controiled frequency, whose preferred solutions are realized by separate circuit arrangements. According to one of the circuit arrangements the phase shift is solved by temporary reprogram ming the frequency divider nith variable division ratio.
The invention is described further, by way of example, with reference to the accompanying drawings1 in which: figure 1 is the design of nopln frequency synthesizer, figure 2 is a preferred realization of the circuit arrange!rent according to this invention, figure 3 is a further preferred realization of the circuit
arrangement according to this invention, figure 4 is the schematic design of timing circuit, figure 5 is a forni of the sequential control unit, for illust
ration.
The figure 1 shows the known frequency synthesizer having 1 signal source with output frequency controlled by electrical signal - 'rCO is preferred. The output of 1 signal source is connected to 2 frequency divider, whose output is connected to 5 phase detqctor. The output of 5 phase detector is feed back to control input of 1 signal source with controlled frequency through 6 loop filter. The reference input of 5 phase detector is connected to 4 reference signal source through constant 3 reference divider. The 1 signal source with controlled frequency is equipped with 10 pretuning circuit.
The figure 2 shows a preferred realization of circuit arrange nent according to this invention. The circuit arrangement contains 7timingcircuit, whose signal input is connected to 2 frequency divider with variable division ratio, its reference input is connected to reference input of 5 phase detector, Accord to this figure the output of 7timingcircuit is connected to control input of 8 phase shifter.The 8 phase shifter is insert ed, as shown in this figure, between 5 phase detector and constant 3 reference divider. 9cause the phase shift can be accomplished on the side of reference signal source or 1 signal source with controlled frequency, therefore the 8 phase shifter can also be inserted also between 2 frequency divider with variable division ratio and 5 phase detector, which iS not shown.
The 10 pretuning circuit contains a sequential 11 control uni+ whose first data output is connected to the other control input of 1 signal source with controlled frequency through 12 D/.E converter. The sequential 11 control unit has a second data output, what is connected to the input, cotrolling the division ratio, of 2 frequency divider oith variable division ratio.
The syncrmising output of sequential 11 control unit is connected to synchronising input of 7 timing circuit, its other synchronising output is connected to-the input of 13 timer circuit. According to our invention the bandwith of 6 loop filter is controllable whose control input is connected to Kle output of 13 timer circuit.
The 8 phase shifter according to figure 2 can be realized by analog or digital device. For a preferred digital realization of 8 phase shifter is a shift register. This preferred realization allows very fine adjustement as for realization by shiftregister the step size of phase shift is function of clock frequency driving the shi" t-register. This can be selected according to desired step.
The figure 3 shots a further preferred realization of circuit arrangement. For this realization the output of 7timing circuit is connected to input of 2 frequency divider with variable division ratio. The phase shift is accomplished by temporary reprogransWe the 2 frequency divider with variable division ratio. This realization allows a less fine phase shift, because the lowest step size of phase shift is determined by cycle time of 1 signal source with controlled frequency.
The figure -4 shots the schenatic design of 7 timing circuit for illustration. According to this figure the 7 tiring circuit contains a 71 logic circuit, whose output is connected to the input of 75 memory element through the 72 counter. The output of 73 memory element forms - direct or indirect -, for e=anple, through the 74 adder/subtracter circuit, the output of 7 timing circuit. As figure 4 shows,the 71 logic circuit is connected to the signal input of 2 frequency divider with variable division ratio, its reference input is connected to the signal input of 5 phase detector, that is, tn the output of 3 reference divider.The synchronising output of n logic circuit is connected to synchrcarising iipl2t of sequential 11 control unit.
The 72 counter has a flock input and an enable input connected to the sequential 11 control unit. The sequential 17 control u unit provides for loading and clearing the 73 memory element.
The figure 5 shows the seheratic design of sequential 11 control unit, which contains a Ill CPU unit and 112 shift register.
One of the 11 CPU's outputs is the first data output of sequen- tial 11 control unit connected to 12 D/A converter. The other output of Ill CPU unit is the second data output of sequential 11 control unit connected to the input, controlling the division ratio, of 2" frequency divider with variable division ratio.
The further output of 111 CPU unit - the further synchronising output of sequential 11 control unit - is connected to the input of 15 tiger circuit. This further output of 111 CPU unit also connected to reset input of 112 shift-reister. The data input of 112 shift-register is set permanently to H-level. According to this figure the synchronising output of 71 logic circuit forms the clock: input for 112 shift register, this synchronising output - the synchron input of sequential 11 control unit - is also connected to 111 CPU unit.The individual outputs of 112 shift-regis- ter form together the synchroniswle output Of sequential 11 control unit connected to synchron input of 7 timing circuit and are connected to the enable input of 72 counter of 11 control unit and 79 memory element.
Tile described circuit arrangement operates as follows:
First, the operation o circuit arrangement containing shiftregister as 8 phase shifter inserted between the constant 3 re reference divider and 5 phase detector is described. The 111 CPU unit of circuit arrangement is given an external sisal trigger- ing the tuning, whereupon the 111 CPU unit takes off the reset signal of 172 shift-register on its further output and switches simultaneously on the 13 timer circuit. The 111 CPU unit of sequential 11 control unit determines the division ratio of 2 frequency divider with variable division ratio, the degree of pretuning.The high bandwith of loop filter is rJitched on for time interval determined by 13 timer circuit. The 13 timer circuit provides for disabling the output of 5 phase detector for predBtermined time - for the time of time measurement and correction carried out by us.
At the second synchronizing signal, when the division ratio of 2 frequency divider with variable division ratio and the frequency of 1 signal source with controlled frequency are constant the signal on output of 112 shift-register enables the operation of 72 counter of 7 timing circuit and the 71 logic circuit determines the sign of signals on its inputs - signals of 2 frequency divider and constant 3 reference divider - that is, the size of difference.
At the third synchronizing signal the 72 counter is disabled and the content of 72 counter is loaded in 73 memory element.
This means that, the phase difference between the phases of output signal and 4 reference signal source in the 73 memory ele:rnt.
This difference is added or subtracted to/froni value deteemining- the meal value of phase shift, for example, by means of 74 a adder/subtracter circuit, according to sien of error occured in 71 logic circuit, and this value is loaded in 8 phase shifter in our case in the shift register realizing the phase shift, at the fourth synchronizing signal. The fourth synchrorizing signal clears simultaneously the content of 75 memory element, From this time to new start of tuning the content of S phaseshifter, the shift-registerS remans constant.
If the output of 7 timing circuit vas connected to the input, controlling the division ratio, of 2 frequency divider with variable division ratio, the circuit arrangement would be operating as follows. The operation of sequential 11 control unit and further subunits of circuit arrangement is in agreement with above described opematinn fron start of tuning to fourth synch- ronizing si.crnal. After the third synchronizing signal the result o time measurement is in the 73 ,memory element.The value of 73 memory element is added or subtracted to/from original value o 2 requency divider, for example, by means of 74 adder/subtracter circuit according to sign of error occured in 71 logic circuit.
At the fourth synchwonizing signal this new value is loaded in 2 frequency divider with variable division ratio, simultaneously the content of 73 memory element is cleared by the suitable output of 112 shift-register.
At the fifth synchronizing signal the original value is loaded in 2 frequency divider with variable division ratio. In this case, the division ratio of 2 frequency divider with variable division ratio is changed during one cycle time. This solution allows a less fine settir, but t; design of circuit arranger.ent is zore simple.
In an other form of circuit arrangement the output of 7 tinning circuit can be connected to input, controlling the division ratio, of 2 frequency divider with variable division ratio and the 71 logic circuit of 7timingcircuit,do not form a sign. ror this form of circuit arrangement, it can be reclized an one-way phase shift - delay for addition, advance for subtraction.
Suppose that, a delay is realized, that is, the.value neasured by 7 timing circuit is added to original value of 2 frequency divider with variable division ratio. For this form ofcircuit arrangenent, the 111 CPU unit of sequential 11 control unit monitors the direction of tuning - increasing or decreasing the frequency - and provides for contstant phase advance, hich is conpensated with delay, throughloading order of division ratio in 2 frequency divider with variable division ratio according to the frequency pretuning.For tuning up the 111
CPU unit makes first frequency retuning through 12 D/A converter, then the suitable value is loaded in 2 frequency divider with variable division ratio. For tunis down the order is reversed. If the phase shift is acco=plished by 2 frequency divider with variable division ratio, it is preferred, the clock signal of 72 counter of 7 tining circuit would be the output signal of 1 signal source with controlled frequency. If the 8 phase shifter is a shift register, the clock signals of this shift register and 72 counter of 7 timmng circuit are selected the sane.
Su=t'.arized, it can be stated, the tuning rate of frequency synthesizers can be increased through solutions according to this invention. In our solution the control rate is caned tenporary in such a uay that, during this tile stability of control do not change.
In the annexed claims reference numbers have been used purely by
way of example in order to facilitate comprehension, but it is hereby
declared that absolutely no limitation of scope whatsoever is intended
thereby.
Claims (10)
1. method for increasing the tuning rate of frequency synthesi
zers during that, the phase of output signal, or its given
part, of a-signal source with output frequency controlre-d by electrical signal is compared to phase of a reference
signal source in sampled nay, the frequency and phase of
signal source lxith controlled frequency is modified through
a negative feedback control loop, characterized in that,
the frequency of signal source with output frequency cont
rolled by electrical signal is pretuned in known way, the
output frequency is decreased, the difference between the
phases of output signal with decreased frequency and refe
rence signal source is measured and the phase of reference
signal source and/or output signal with decreased frequency
is controlled bg phase shift in such a way that, the diffe
rence approaches the value in steady state.
2. Metktod according to claim 1, characterized in that, the pre
tuning is accomplished during time interval between two
paring - sampling - periods.
3. Method according to clain 1 or 2, characterized in that,
the control rate is increased in such a way that, the band
with is increased within the stability range defined by sanp ling frequency, then the original control rate mould be reset
if the difference approached the steady state value indesired
degree.
4. Circuit arranzement for increasing the tuning rate of frequ
ency synthesizers, which has a signal source with output
frequency controlled by electrical signal - vco is preferred -,
the output of signal source smith controlled frequency is
connected to a frequency divider with variable division ratio, whose output is connected to a phase detector with its output
feed back to control input of signal source ezith controlled
frequency through a loop filter, the reference input of pha
se detector is connected to a reference signal source through
a constant reference divider, the signal source with control
led frequency is equipped with a pretuning circuit, charac
terized in that, it contains atiming circuit /7/, whose sig
nal input is connected to the output of frequency divider /2/ with variable division ratio aDd its reference input is con
nected to the reference input of phase detector /5/, the
output of timinEcircuit /7/ is connected to the control in
put of phase shifter /8/ and the phase shifter /8/ is insert
ed betv::een the pliase detector /5/ and the constant reference
divider /3/ or between the frequency divider /2/ vjith variab
le division ratio and the phase detector /5/, the pretuning circuit /10/ contains a sequential control circuit /11/,
those first data output is connected to other control input
of the signal source /1/ nith controlled frequency through a D/A converter /12/, its second data output is connected
to the input, controlling the division ratio, of frequency
divider /2/ with variable division ratio, the synchron out
put sequential control unit /11/ is connected to' the synchron
input of timing circuit /7/ its further synchron output is
connected to the input of timer circuit /13/, the bandwith of its loop filter is controllable and its control input is
connected to the output of timer circuit /13/.
5. Circuit arrangement according to clain 4, characterized in
that, the phase shifter /8/ is a shift register.
6. Circuit arrangement for increasing the tuning rate of frequ
ency synthesizers, which has a signal source with output
frequency controlled by electrical signal -vco is preferred -,
the output of signal source . ' with controlled frequency
is connected to a frequency divider with variable division
ratio, whose output is connected to a phase detector with
its output feed back to the control input of signal source
with controlled frequency through a loop filter, the refe
rence input of phase detector is connected to a reference
signal source through a constant reference divider, the
signal source uith controlled frequency is equipped with
a pretuning circuit, characterized in that, X circuit arrangement contains a timing circuit /7/, whose signal
input is connected to the output of frequency divider /2/
with variable division ratio, its reference input is con
nected to the reference input of phase detector/5/, the
output of tinning circuit /7/ is connected to the reference
input of phase detector /5/, the output of timing circuit /7/
is connected to the input, controlling the division ratio,
of frequency divider /2/ with variable division ratio, the
pretuning circuit /10/ contains a sequentialcmtroJunt/ll/, whose first data output is connected to control input
signal source /1/ with controlled frequency through a D/A
converter /12/, its second data output is connected to input controlling the division ratio, of frequency divider /2/
with variable division ratio, the synchron output of control unit /11/ is connected to the snchron input of timing
circuit /7/, its further synchron output is connected to
the input of timer circuit /13/, the bandwith of its loop
filter is controllable, whose control input is connected to
the output of timer circuit /15/.
7 Circuit arrangenent according to claims 4 - 6, ctaracterized
in that, the timing circuit /7/ contains a logic circuit /71/,
whose output is connected to the input of memory element /75/ through a counter /72/, the output of memory element /73/
forms direct or indirect the output of timing circuit /7/.
circuit arrangement according to claim 7, characterized in- that, the sequential control unit /11/ has a cPu unit /111/
as well as shift register /112/, one of the CPU's /111/
outputs is the first data output of sequential control unit /ill/, its other output is the second data output of sequen
tial control unit , a further output of CPU unit /111/ is connected to the clear inputs of timer circuit /13/ and shift-register /112/, the logic circuit /71/ has a synchron output connected to the clock input of shift register /112/ and input of CPU unit. /111/, the individual outputs of shift register /112/ form together the syncllron output of sequential control unit /ill/, vihich are connected to the enable input of counter /72/ of sequential control unit t /11/ and to the meniory element /73/.
9.A method for increasing the tuning rate of a frequency synthesizer having a signal source for providing an output signal with a controlled
frequency, comprising varying the frequency of the output signal in a predetermined manner, composing the phase of the output signal when varied with the phase of a reference signal, and shifting the phase of
the output signal and/or reference signal such that any difference in phase
approaches a steady state value.
10. A circuit arrangement for increasing the tuning rate of a frequency synthesizer having a frequency controlled negative feedback loop including a signal source for providing an output signal with a controlled frequency, comprising means for varying the frequency of the output signal in a predetermined manner of connection with the transient of the frequency, means for generating a reference signal, comparison means for comparing the phase of the output signal with the phase of the reference signal, and means for shifting the phase of the output signal and/or the reference signal such that any difference in phase approaches a steady state value.
10. A circuit arrangement for increasing the tuning rate of a
frequency synthesizer hazing a signal source for providing an output
signal with a controlled frequency, comprising means for varying the frequency of the output signal in a predetermined manner, means for generating a reference signal, comparison means for comparing the phase
of the output signal with the phase of the reference signal, and means
for shifting the phase of the output signal and/or the reference signal
such that any difference in phase approaches a steady state value.
11. A method substantially as herein particularly described with reference to Figures 2, 4 and 5 or Figures 3, 4 and 5 of the
accompanying drawings.
12. A circuit arrangement substantially as herein particularly described with reference to and as illustrated in Figures 2, 4 and 5 or Figures 3, 4 and 5 of the accompanying drawings.
Amendments to the claims have been filed as follows
9. A method for increasing the tuning rate of a frequency synthesizer having a frequency controlled negative feedback loop including a signal source for providing an output signal with a controlled frequency, comprising varying the frequency of the output signal in a predetermined manner of connection with the transient of the frequency, composing the phase of the output signal when varied with the phase of a reference signal, and shifting the phase of the output signal and/or reference signal such that any difference in phase approaches a steady state value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8913749A GB2233176A (en) | 1989-06-15 | 1989-06-15 | Frequency synthesisers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8913749A GB2233176A (en) | 1989-06-15 | 1989-06-15 | Frequency synthesisers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8913749D0 GB8913749D0 (en) | 1989-08-02 |
| GB2233176A true GB2233176A (en) | 1991-01-02 |
Family
ID=10658477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8913749A Withdrawn GB2233176A (en) | 1989-06-15 | 1989-06-15 | Frequency synthesisers |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2233176A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2258096A (en) * | 1991-07-24 | 1993-01-27 | Matsushita Electric Ind Co Ltd | Clock changeover apparatus |
| FR2726724A1 (en) * | 1994-11-07 | 1996-05-10 | Motorola Inc | RF transceiver method e.g. for cellular radio telephone system |
| GB2339981A (en) * | 1998-07-17 | 2000-02-09 | Motorola Ltd | Frequency synthesisers |
| CN114019857A (en) * | 2021-10-28 | 2022-02-08 | 华中师范大学 | High-precision phase adjusting and measuring system and method based on phase interpolation |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2097206A (en) * | 1981-04-21 | 1982-10-27 | Marconi Co Ltd | Frequency synthesisers |
| US4434407A (en) * | 1981-04-06 | 1984-02-28 | Westinghouse Electric Corp. | Presetting circuit for the voltage-controlled oscillator of a phase lock loop |
| US4511858A (en) * | 1980-06-03 | 1985-04-16 | Thomson-Csf | Frequency prepositioning for an indirect frequency synthesizer |
| US4516083A (en) * | 1982-05-14 | 1985-05-07 | Motorola, Inc. | Fast lock PLL having out of lock detector control of loop filter and divider |
-
1989
- 1989-06-15 GB GB8913749A patent/GB2233176A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4511858A (en) * | 1980-06-03 | 1985-04-16 | Thomson-Csf | Frequency prepositioning for an indirect frequency synthesizer |
| US4434407A (en) * | 1981-04-06 | 1984-02-28 | Westinghouse Electric Corp. | Presetting circuit for the voltage-controlled oscillator of a phase lock loop |
| GB2097206A (en) * | 1981-04-21 | 1982-10-27 | Marconi Co Ltd | Frequency synthesisers |
| US4516083A (en) * | 1982-05-14 | 1985-05-07 | Motorola, Inc. | Fast lock PLL having out of lock detector control of loop filter and divider |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2258096A (en) * | 1991-07-24 | 1993-01-27 | Matsushita Electric Ind Co Ltd | Clock changeover apparatus |
| US5268654A (en) * | 1991-07-24 | 1993-12-07 | Matsushita Electric Industrial Co., Ltd. | Phase locked loop clock changeover apparatus in which the VCO is set to an initial value |
| GB2258096B (en) * | 1991-07-24 | 1995-04-26 | Matsushita Electric Ind Co Ltd | Clock changeover apparatus |
| FR2726724A1 (en) * | 1994-11-07 | 1996-05-10 | Motorola Inc | RF transceiver method e.g. for cellular radio telephone system |
| GB2339981A (en) * | 1998-07-17 | 2000-02-09 | Motorola Ltd | Frequency synthesisers |
| GB2339981B (en) * | 1998-07-17 | 2002-03-06 | Motorola Ltd | Phase corrected frequency synthesisers |
| US6396890B1 (en) | 1998-07-17 | 2002-05-28 | Motorola, Inc. | Phase corrected frequency synthesizers |
| CN114019857A (en) * | 2021-10-28 | 2022-02-08 | 华中师范大学 | High-precision phase adjusting and measuring system and method based on phase interpolation |
| CN114019857B (en) * | 2021-10-28 | 2024-03-22 | 华中师范大学 | High-precision phase adjustment and measurement system and method based on phase interpolation |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8913749D0 (en) | 1989-08-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |