GB2230136A - Method for manufacturing static induction type semiconductor device - Google Patents
Method for manufacturing static induction type semiconductor device Download PDFInfo
- Publication number
- GB2230136A GB2230136A GB9005988A GB9005988A GB2230136A GB 2230136 A GB2230136 A GB 2230136A GB 9005988 A GB9005988 A GB 9005988A GB 9005988 A GB9005988 A GB 9005988A GB 2230136 A GB2230136 A GB 2230136A
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- GB
- United Kingdom
- Prior art keywords
- zones
- gate
- impurity diffusion
- constituting
- cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 40
- 230000006698 induction Effects 0.000 title claims description 30
- 230000003068 static effect Effects 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000012535 impurity Substances 0.000 claims description 71
- 238000009792 diffusion process Methods 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66416—Static induction transistors [SIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
- H01L29/7392—Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
Description
1 - 1
PATENT SPECIFICATION
Title:
METHOD FOR MANUFACTURING STATIC INDUCTION 1 TYPE SEMICONDUCTOR DEVICE AND THEREBY MANUFACTURED SEMICONDUCTOR DEVICE.
2 This invention relates to a method for manufacturing static induction type semiconductor device and thereby manufactured semiconductor devices.
The static induction type semiconductor device of the kind referred to may be effectively utilized in a circuit which employs, for example, an enhancement type semiconductor device.
An example of the static induction type semiconductor device of the kind referred to has been disclosed in Japanese Patent Application LaidOpen Publication No. 54-92180 by S. Iwanai, according to which a mesa etching is carried out with a selective oxidation of a surface of semiconductor substrate to form therein gates, and conductive silicon crystals are made to adhere by means of CVD method or the like to surf ace parts to be made as drains. With this known device, however, there is a problem that the electric characteristics have been unstable due to that the depth of driiin zones or fluctuation in sheet resistance is too much. That is, such impurity profile as the impurity concentration and diffusion depth are likely to be made not stable nor uniform upon the adhesion of the conductive silicon ll - 3 Q, 5 crystal onto the surface of the semiconductor substrate and its thermal diffusion into the substrate.
In the foregoing static induction type semiconductor, the withstand voltage characteristics between the gate and drain are relying on the distance from drain forming position and the impurity concentration, in particular, of conjugated portion between heterogenous impurity zones, but there has been a problem that such distance and concentration are caused to fluctuate due to the unstable impurity profile so as to render the withstand voltage between the gate and drain unstable. Further in the foregoing static induction type semiconductor device, the gate threshold voltage relies on the channel width between the impurity diffusion zones as the gate zones so that, in the one of enhancement type, the channel width is desired to be made as small as possible, whereas the problem due to the unstable impurity profile is made remarkable as the channel width is made smaller.
Further static induction type semiconductor devices are disclosed in Japanese Patent Publication No. 60-955 of Y. Gyomoto, Japanese Patent Application Laid-open Publication No. 56-71979 of H. Ikoma and so on, but they are still not of a level beyond the foregoing device of S.
Iwanai, without solving the problem involved in the known art.
A primary aim of the present invention is to provide a method for manufacturing an enhancement type, t 4 - 1 r, static induction type semiconductor device and the thereby manufactured semiconductor device, in which device such impurity profile as the impurity concentration and diffusion depth can be made substantially uniform so that the withstand voltage characteristics between the gate and cahode can be stabilized and the channel width can be sufficiently made smaller to be utilized as the enhancement type so as to be able to optimumly set the gate threshold voltage.
According to the present invention, the above aim is realized by a method for manufacturing an enhancement type, static induction type semiconductor device in which impurity diffusion zones constituting gate zones are formed on a surface side of a semiconductor substrate, further impurity zones constituting chathode zones are formed also on the surface side of the semiconductor substrate, gate electrodes are formed on the impurity diffusion zones constituting the gate zones, cathode electrodes are formed on the impurity diffusion zones constituting the cathode zones, and an anode electrode is formed on an impurity diffusion zone formed on a reverse side of the substrate to constitute an anode zone, characterized in that the impurity diffusion zones constituting the cathode zones are formed in such that an oxide film is provided to cover the surface side of the substrate on which the impurity diffusion zones constituting the gate zones are formed, apertures for providing the impurity diffusion zones constituting the - 5 cathode zones are provided in the oxide film, the impurity diffusion zones constituting the cathode zones are formed by means of a thermal diffusion of an impurity as led through the apertures into the surface side so that the cathode zones will partly overlap the impurity diffusion zones constituting the gate zones, a thin oxide film is provided within the apertures, and the cathode electrodes are formed through an etching carried out to selectively remove the thin oxide film in the apertures.
According to the foregoing method for manufacturing the static induction type semiconductor device, the fluctuation in the impurity concentration or the depth of diffusion can be minimized by the impurity diffusion zones constituting the cathode zones are so formed as to partly overlap the impurity diffusion zones constituting the gate zones, whereby the impurity profile can be stabilized so that the electric characteristics can be effectively made stable even when the channel width between the respective impurity diffusion zones constituting the gate zones are made smaller.
The invention will now be described in detail, by way of example, with reference to the drawings, in which:- FIGURES la through lg are diagrams for explaining the sequence of basic steps forming the method for manufacturing the static induction type semiconductor k 1 device according to the present invention; FIGS. 2a to 2c are diagrams for explaining with a fragmental relevant part of the device the sequence of steps for rendering the static induction type semiconductor device to be of an enhancement type according to the method of the present invention; FIG. 3 shows more in detail the static induction type semiconductor device of the enhancement type as manufactured through the steps of FIG. 2; and FIG. 4 is a diagram showing the impurity profile at the respective impurity diffusion zones constituting the gate and cathode zones in the enhancement type, static induction type semiconductor device of FIG. 3.
While the present invention shall now be described with reference to embodiments shown in theaccompanying drawings, it should be appreciated that the intention is not to limit the invention only to such embodiments shown but to rather include all alterations, modifications and equivalent arrangements possible within the scope of appended claims.
Referring to FIGS. la through lg, there are shown here basic steps of the method for manufacturing a surface gate type static induction thyristor as the static induction type semiconductor device according to the present invention. In the present instance, as shown in FIG. la, an N - type silicon semiconductor substrate 11 is provided with a P-type impurity diffusion zone 12 constituting an 1 1 1 11 - 7 anode zone formed on a reverse side of the substrate, and with P -type impurity diffusion zones 13 constituting gate zones formed on the other surface side of the substrate 11, and an oxide film 14 is further formed to cover the surface side over the zones 13. Next, as in FIG. lb, ion- implanting apertures 15 are made through the oxide film 14 so that the apertures 15 will expose the surface of the substrate 11 between the adjacent P ±type impurity diffusion zones 13 while partly overlapping the zones 13, such N-type impurity as phosphor is introduced into the exposed surface of the substrate, and the introduced impurity is subjected to a thermal diffusion and activation within an atomosphere of N 2 gas. Consequently, as in FIG. lc, N ±type impurity diffusion zones 16 constituting cathode zones are formed so as to be provided with a reverse directional junction withstand voltage with respect to the P ±type impurity diffusion zones 13 constituting the gate zones, and thereafter the apertures 15 are closed by a thin oxide film 14a formed to be about 0 several hundred A to cover the zones 16. That is, in the event where the substrate is subjected to the thermal diffusion in the N 2 gas atmosphere, a very thin, natural oxide film is to be formed inside the apertures 15. In the present instance, the ion implantation is employed for leading the impurity into the apertures 15 for forming the cathode zones, but any other process, for example, a deposition process with P0C1 3 which is a liquid source may be employed.
1 8 - As shown in FIG. ld, next, contact apertures 17 for making gate electrodes are made through the oxide film 14 on the surface side of the silicon semiconductor substrate 11 to partly expose the P ±type impurity diffusion zones 13, preferably by means of an etching carried out with a photomasking provided on the film 14. Since the P ±type impurity diffusion zones 13 constituting the gate zones have been formed to be diffused to a relatively large depth into the N -type semiconductor substrate 11 and to have a relatively large widthwise dimension on the surface side of the substrate 11, the formation of the contact apertures 17 in the oxide film 14 above the respective zones 13 can be carried out very easily with a certain dimensional allowance. After such formation of the apertures 17, the thin oxide film 14a formed in the apertures 15 is removed at selective positions so as to form contact apertures 15a for making cathode electrodes.
In this case, it may be possible to f orm the contact apertures 15a only by means of a slight etching without carrying out the photomasking with respect to the thin oxide film 14a. It is possible to reach a state as shown in FIG. le where both of the contact apertures 17 f or providing the gate electrodes and the contact apertures 15a for providing the cathode electrodes to the semiconductor. substrate 11 are formed, with the slight etching performed, for example, for about 30 seconds with a solution of HF:H 2 0=1:10. The foregoing ion- implanting apertures 15 as well as the contact apertures 15a for t providing the cathode electrodes may be formed practically in the same manner.
Then, as shown in FIG. lf, cathode electrodes 20 and gate electrodes 21 respectively of aluminum are concurrently formed. Further, as shown in FIG. lg, an anode electrode 22 is formed on the P-type impurity zone 12 on the reverse side of the semiconductor substrate 11, and the surface gate type static induction thyristor can be thereby completed. Here, the oxide film 14 is to constitute an insulating layer. It will be readily appreciated that, in the static induction thyristor prepared through the foregoing manufacturing steps, the amount of electric current flowing through a high specific resistance zone, i.e., a base zone which the silicon semiconductor substrate 11 can be controlled by adjusting a voltage applied to the gate electrodes 21. Further, while the contact apertures 17 for providing the gate electrodes have been referred to as being formed prior to the contact apertures 15 for providing the cLthode electrodes in the foregoing manufacturing steps according to the present invention, these contact apertures 17 may of course be formed after the formation of the contact apertures 15a for providing the cathode electrodes.
Referring next to FIGS. 2a through 2c, there are shown main steps in a more concrete method for manufacturing the static induction thyristor of the enhancement type according to the present invention. In the enhancement type static induction thyristor, in particular, a frelatively large current capacity is demanded so that the ion-implanting apertures 15 for forming the cathode zones are required to be provided wider, whereas the channel width Cd. between adjacent ones of the impurity diffusion zones 13 constituting the gate zones is demanded to be of the minimum value, so that the arrangement will be such that the area of each aperture 15 for making the cathode zone overlaps partly adjacent ones of the impurity diffusion zones 13 constituting the gate zones. In this event, the manufacturing steps themselves may be the same as those of FIGS. la through lg, but the ion-implanting apertures 15 are to be made in obtaining the enhancement type thyristor, in practice, so that each ion-implanting aperture 15 is made to partly overlap the adjacent ones of the impurity diffusion zones 13 formed as the gate zones with the channel width Cd made relatively narrower so as to expose mutually opposing corner portions of the zones 13, as seen in FIG. 2a. The ion- implanting is then carried out through the apertures 15 with such N-type impurity as phosphor, the thermal diffusion of the implanted ions and their activation are carried out in the N 2 gas atmosphere, and the N ± type impurity diffusion zones 16 for forming the cathode zones are thereby formed, as shown in FIG. 2b, in which event the impurity diffusion zones 16 constituting the cathode zones are formed so as to partly overlap corner or edge portions of the impurity diffusion zones 13 constituting the gate zones. The impurity diffusion zones 16 constituting the cathodezones is 1 may be formed is by means of the foregoing deposition process.
Thereafter, the cathode elctrodes 20 and gate electrodes 21 are provided in the same steps as in FIG. 1 with respect to the impurity diffusion zones 16 constituting the cathode zones and the impurity diffusion zones 13 constituting the gate zones, respectively, with the oxide film 14 interposed, as shown in FIG. 2c, while the anode electrode 22 is provided with respect to the impurity diffusion zone 12 constituting the anode zone, and such enhancement type static induction thyristor as shown in FIG. 3 is thereby completed. In this enhancement type static induction thyristor of FIG. 3, the P-type and N-type impurities are made equal in the concentration at PN junction boundary between the impurity diffusion zones 13 constituting the gate zones and the impurity diffusion zones 16 constituting the cathode-zones. Referring to FIG. 4 showing the impurity profile measured adjacent a point A on the surface side of the substrate 11, it will be appreciated that an intersection of P ±type and N ±type impurity concentration curves in the diagraph of FIG. 4 corresponds to the PN junction boundary. In the case of known enhancement type static induction thyristor, the impurity diffusion zones constituting the cathode-zones show a remarkable fluctuation in the impurity profile so that, when the diffusion is shallow and the impurity concentration is low as shown in FIG. 3, the PN junction boundary will be at a position of B I, in which event the is - 12 boundary becomes insufficient in the distance from the contact aperture 15a for forming the cathode electrode, so as to cause a risk to arise in that the gate and cathode zones may involve a short-circuit or at least a deficiency in the withstand voltage. In the enhancement type static induction thyristor according to the present invention, on the other hand, the impurity diffusion zones 16 constituting the cathode zones show only a small and stable fluctuation in the impurity concentration and diffusion depth, so that the PN junction boundary on the surface of the substrate 11 will be stably disposed at a position B in FIG. 3 as sufficiently separated from the cathode-electrode forming contact aperture 15a. Even when the contact apertures 15a are so formed as to partly overlap the impurity diffusion zones 13 constituting the gate zones, therefore, the junction boundary of these zones 13 with the impurity diffusion zones 16 constituting the cathode zones will be at a position X in FIG. 3 so as to be stably disposed at a position remote from the contact aperture 15a, whereby the reverse directional junction withstand voltage is made sufficient between the gate zones and the cathode zones so as to effectively prevent any short-circuit from occurring between them.
I- 1
Claims (7)
13 CLAIMS
A method for manufacturing an enhancement type, static induction type semiconductor device, the method comprising the steps of preparing a semiconductor substrate having impurity diffusion zones constituting gate zones formed on a surface side of said substrate and an oxide film covering said surface side, providing apertures through said oxide film for forming impurity diffusion zones constituting cathode zones, forming said impurity diffusion zones constituting said cathode zones with an impurity led through said apertures and subjected to a thermal diffusion carried out to partly overlap said impurity diffusion zones constituting the gate zones, forming cathode electrodes on said impurity diffusion zones constituting the cathode zones with an etching carried out to selectively remove a thin oxide film produced within said apertures, forming gate electrodes on said impurity diffusion zones constituting the gate zones, and providing an anode electrode on an impurity diffusion zone constituting an anode zone formed on reverse side of the substrate.
2. The method according to claim 1 wherein said apertures for forming said impurity diffusion zones constituting said cathode zones are formed to partly ovelap said impurity diffusion zones constituting said gate zones.
3. An enhancement type, static induction type semiconductor device comprising a semiconductor substrate, 1 1 1.
- 14 gate zones formed on a surface side of said semiconductor substrate an-d each having a gate electrode provided thereon, cathode zones formed on said surface side of the semiconductor substrate to partly overlap said gate zones with a sufficient reverse directional junction withstand voltage maintained with respect to the gate zones and each having a cathode electrode provided thereon, and an anode zone formed on a reverse side of said semiconductor substrate and having an anode electrode formed thereon.
4. The device according to claim 3 wherein said gate zones are disposed to have a channel width made sufficiently small.
1 Z p p.
- is
5. A method of manufacturing an enhancement type, static induction type semiconductor device substantially as described herein with reference to the drawings.
6. An enhancement type, static induction type semiconductor device produced by the method claimed in any one of claims 1, 2 or 5.
7. An enhancement type, static induction type semiconductor device substantially as described herein with reference to the drawings.
X Published 1990 at The P-tent Office. State House.6672 High Holborn.London WC1 R 477. Purther copies be obtained from The Patent Office ZLL& Branch, St Mary Cray. OipiiirAn, Kent BR5 3RD. Printed by Multiplex tachwcauts ltd. St Mary Cray, Kent, Con. 1187
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1076009A JP2757962B2 (en) | 1989-01-26 | 1989-03-28 | Manufacturing method of electrostatic induction semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9005988D0 GB9005988D0 (en) | 1990-05-09 |
| GB2230136A true GB2230136A (en) | 1990-10-10 |
| GB2230136B GB2230136B (en) | 1993-02-10 |
Family
ID=13592818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9005988A Expired - Fee Related GB2230136B (en) | 1989-03-28 | 1990-03-16 | Method for manufacturing static induction type semiconductor device and semiconductor devices manufactured thereby |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE4009675C2 (en) |
| FR (1) | FR2645348B1 (en) |
| GB (1) | GB2230136B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4041517A (en) * | 1974-09-04 | 1977-08-09 | Tokyo Shibaura Electric Co., Ltd. | Vertical type junction field effect semiconductor device |
| US4326209A (en) * | 1977-04-13 | 1982-04-20 | Nippon Gakki Seizo Kabushiki Kaisha | Static induction transistor |
| EP0064561A1 (en) * | 1980-11-21 | 1982-11-17 | Zaidan Hozin Handotai Kenkyu Shinkokai | Static induction thyristor |
| US4403396A (en) * | 1981-12-24 | 1983-09-13 | Gte Laboratories Incorporated | Semiconductor device design and process |
| US4566172A (en) * | 1984-02-24 | 1986-01-28 | Gte Laboratories Incorporated | Method of fabricating a static induction type recessed junction field effect transistor |
| EP0194199A2 (en) * | 1985-02-28 | 1986-09-10 | Research Development Corporation of Japan | Double gate static induction thyristor and method for manufacturing the same |
| EP0194946A2 (en) * | 1985-03-13 | 1986-09-17 | Research Development Corporation of Japan | Pressurized contact type double gate static induction thyristor |
| US4713358A (en) * | 1986-05-02 | 1987-12-15 | Gte Laboratories Incorporated | Method of fabricating recessed gate static induction transistors |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4060821A (en) * | 1976-06-21 | 1977-11-29 | General Electric Co. | Field controlled thyristor with buried grid |
| JPS5492180A (en) * | 1977-12-29 | 1979-07-21 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| JPS6046551B2 (en) * | 1978-08-07 | 1985-10-16 | 株式会社日立製作所 | Semiconductor switching device and its manufacturing method |
| JPS6016753B2 (en) * | 1979-01-19 | 1985-04-27 | 株式会社日立製作所 | Semiconductor switching device and its control method |
| JPS5671979A (en) * | 1979-11-19 | 1981-06-15 | Toshiba Corp | Static induction transistor and preparation method thereof |
| US4571815A (en) * | 1981-11-23 | 1986-02-25 | General Electric Company | Method of making vertical channel field controlled device employing a recessed gate structure |
| JPS58131771A (en) * | 1982-02-01 | 1983-08-05 | Hitachi Ltd | Electrostatic induction type semiconductor switching device |
| JPS60955A (en) * | 1983-06-18 | 1985-01-07 | 泉株式会社 | Anti-contamination processing method of protective sheet-shaped article for construction work |
| US4551909A (en) * | 1984-03-29 | 1985-11-12 | Gte Laboratories Incorporated | Method of fabricating junction field effect transistors |
| DE3586735D1 (en) * | 1984-10-19 | 1992-11-12 | Bbc Brown Boveri & Cie | DISABLED POWER SEMICONDUCTOR COMPONENT. |
| IT1202313B (en) * | 1985-09-26 | 1989-02-02 | Sgs Microelettronica Spa | SEMICONDUCTOR POWER DEVICE, NORMALLY INTERDICTED FOR HIGH VOLTAGES AND WITH MODULATED RON |
| JPS634680A (en) * | 1986-06-24 | 1988-01-09 | Matsushita Electric Works Ltd | Electrostatic induction type semiconductor device |
-
1990
- 1990-03-16 GB GB9005988A patent/GB2230136B/en not_active Expired - Fee Related
- 1990-03-26 DE DE4009675A patent/DE4009675C2/en not_active Expired - Fee Related
- 1990-03-27 FR FR9003885A patent/FR2645348B1/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4041517A (en) * | 1974-09-04 | 1977-08-09 | Tokyo Shibaura Electric Co., Ltd. | Vertical type junction field effect semiconductor device |
| US4326209A (en) * | 1977-04-13 | 1982-04-20 | Nippon Gakki Seizo Kabushiki Kaisha | Static induction transistor |
| EP0064561A1 (en) * | 1980-11-21 | 1982-11-17 | Zaidan Hozin Handotai Kenkyu Shinkokai | Static induction thyristor |
| US4403396A (en) * | 1981-12-24 | 1983-09-13 | Gte Laboratories Incorporated | Semiconductor device design and process |
| US4566172A (en) * | 1984-02-24 | 1986-01-28 | Gte Laboratories Incorporated | Method of fabricating a static induction type recessed junction field effect transistor |
| EP0194199A2 (en) * | 1985-02-28 | 1986-09-10 | Research Development Corporation of Japan | Double gate static induction thyristor and method for manufacturing the same |
| EP0194946A2 (en) * | 1985-03-13 | 1986-09-17 | Research Development Corporation of Japan | Pressurized contact type double gate static induction thyristor |
| US4713358A (en) * | 1986-05-02 | 1987-12-15 | Gte Laboratories Incorporated | Method of fabricating recessed gate static induction transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2645348A1 (en) | 1990-10-05 |
| DE4009675A1 (en) | 1990-10-04 |
| FR2645348B1 (en) | 1997-01-17 |
| GB2230136B (en) | 1993-02-10 |
| GB9005988D0 (en) | 1990-05-09 |
| DE4009675C2 (en) | 1995-04-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 19990428 |
|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030316 |