GB2228348A - Memory interface integrated circuit - Google Patents

Abstract

An integrated circuit 1 includes a plurality of functional modules 12-14, 16 interconnected by an internal bus system 17-20 to a memory interface 15 enabling the one of the modules which is using the internal bus system at the time to transmit data to or read data from read/write or read only memory 8-11 of a plurality of different types external to the integrated circuit. The address space of the external memory may be sub-divided between the different types of memory in a predetermined way so that the address selected determines the mode of the memory interface. The memory interface may also control the use of the internal bus system and the access to the external memory. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUITS This invention relates to integrated circuits, and in particular to very large scale integration (VLSI) integrated circuits.

The size and complexity of integrated circuits have increased to such levels that it is now possible to include in a single integrated circuit what whould have been in several integrated circuits, only a few years ago. For example, an integrated circuit may now contain the different functional modules required to form an adapter for connecting a computer to the ring of a local area network.

It is an object of the present invention to enable different functional modules to be accommodated more efficiently on the same integrated circuit.

According to the present invention there is provided an integrated circuit having a plurality of functional modules, an internal bus system having at least data and address buses interconnecting the modules and a memory interface connected to the bus system and to terminals of the integrated circuit for connection to the memory means, the memory interface enabling the one of the modules which is using the internal bus system at the time to transmit data to or receive data from read/write or read-only memory means of a plurality of different types external to the integrated circuit.

The address space of the external memory means may be sub-divided between the different types of memory means in a predetermined way so that the memory interface may be responsive to the address information on the address bus of the internal bus system to select the correct form of data, address and control signals for the type of external memory means including the particular address.

The memory interface may include address mapping registers to enable a module with a limited address range to reach a greater range of addresses.

The memory interface may include means for controlling the allocation of the use of the internal bus system to a particular one of the functional modules in response to requests from the modules and according to a priority system. The memory interface may include means responsive to the identity of the module having use of the internal bus system at the time to block access to certain addresses or groups of addresses of the external memory means. The memory interface may be arranged to produce an output indication of the identity of the one of the functional modules which has use of the internal bus system at the time.

Certain of the functional modules may employ parity for data checking. The memory interface may be arranged to perform parity checks on data which includes parity bits and it may add parity bits to data it receives which do not include parity bits. These operations may be performed on all data transfers using the internal bus system. The memory interface may store indications of which modules require parity with data received and which modules provide parity with data transmitted.

The memory interface may be arranged to provide master or slave operation in the allocation of the use of the internal bus system, so that two or more integrated circuits each including such an interface can operate together, one acting as master and the other acting as slave. To achieve this, the integrated circuits may have "request" and "grant" connections brought out to terminals from the means controlling the allocation -of the use of the internal bus system. The "master" or "slave" status of an integrated circuit may be determined by a signal applied to a terminal of the circuit.

In a particular example the integrated circuit i-s an adapter for connecting a computer to a local area network, and includes, in addition to the memory interface, a protocol handler, a communications processor and a system interface as the modules interconnected by the internal bus system. The integrated circuit may also include a support module for performing various housekeeping functions of the integrated circuit such as controlling through the memory interface the refreshing of the dynamic RAM connected to the memory interface.

An example of an integrated circuit will now be described with reference to the accompanying drawings, of which: Figure 1 is a block diagram of the example of the integrated circuit showing its connections to a host computer, four different types of memory and a local area network; Figures 2a and 2b together form a diagram of the memory interface of the integrated circuit showing its different functional parts and the internal and external signals; Figures 3, 4, 5 and 6 show the connections between the memory interface and four different types of memory; Figure 7 is a block diagram of the bus arbitration circuit for controlling access to the internal bus system; Figure 8 is a block diagram of a modification to the bus arbitration circuits of two integrated circuits for operating in a master/slave mode;; Figures 9(a) and 9(b) show the signal waveforms for writing to a specific type of memory; and Figures 10(a) and 10(b) show the signal waveforms for reading from the specific type of memory.

The example of an integrated circuit to be described is an adapter for connecting a computer based system to a local area network. As shown in Figure 1, the integrated circuit 1 has three external ports 2, 3 and 4 respectively for connection to a host computer 5, via a so-called frontend chip 6 to the network, and to external memory. Four different types of memory are shown: a dynamic RAM 8, a static RAM 9, a PROM 10 and an EPROM 11. The integrated circuit may be arranged to work with more, fewer or different types of memory.

The integrated circuit 1 includes five sub-units or modules: a communications processor 12, a protocol handler 13, a system interface 14, a memory interface 15 and an adapter support function unit 16. These five modules are interconnected by an internal bus system including a data bus 17, an address bus 18, a parity bus 19 and a read/write bus 20. The data bus 17 and the address bus 18 may have several parallel conductors, but the parity bus 19 and the read/write bus 20 will probably have only a single conductor each.

The communications processor 12 contains a cached workspace register CPU. It controls adapter operation, runs diagnostic tests and responds to interrupts. The code running in the communications processor implements the framelevel media access control protocols.

The protocol handler 13 implements the bit and subframe-level media access control protocols. When receiving, the protocol handler deserialises data coming from the ring and transfers it to the external memory 8,9 as a linked list of buffers. When transmitting, it takes data from the external memory 8-11 and sends it in serial form to the ring by way of the front-end chip 6. Besides receiving and transmitting data the protocol handler carries out sundry ring management and monitoring functions and performs extensive error checking.

The system interface 14 interfaces the bus of the host system 5 to the internal bus of the integrated circuit. It controls DMA operations between the host system 5 and the external memory and enables the host system 5 to gain direct access (DID) to the external memory space.

The memory interface 15 contains the controller for the internal bus system and for the external memory. It contains a parity checker and generator, memory mapping registers, bus arbitration logic and clock generators.

The adaptor support function unit 16 contains the remaining features of the integrated circuit. It is separated from the other blocks to make testing easier. It contains a general purpose timer, an interrupt prioritiser and a multiplexer, a DRAM refresh controller and certain registers for controlling the integrated circuit.

The CPU in the communications processor 12 runs tasks for ring control, host computer interfacing, background diagnostics and users. The host computer initialises the adapter by sending it the system command block and the system status block. These tell the adapter where in the external memory to put received frames and where to find ones that are to be sent.

If the host computer needs to send a frame it sends an interrupt to the adpater. From then on the adapter controls transmission of the frame to the ring.

The blocks of the adapter 1 will now be described in more detail.

The System Interface block 14 consists of two separate controllers: 1) Direct 1/0 (DI0) , which manages host system references to the DIO registers presented by the adapter, and 2) System DMA (SDMA), which performs DMA (direct memory access) transfers between the host system bus and the adapter's data bus.

These mechanisms enable the host and the adapter to communicate with each other. The terms "DIO" and "SDMA" refer to the data transfer mechanisms as seen from the host system side. The "DIO" registers appearing on the system bus should not be confused with the registers appearing in the adapter memory map.

For DIO, the adapter appears to the system as a set of 16 consecutive byte addresses aligned on a 16-byte boundary. The DIO registers give the host system access to adapter memory for down loading code, make adapter status information available to the host and allow the host to control the adapter.

During system reads or writes to adapter memory (DIO), the communications processor 12 is locked out of the adapter RAM. With this approach, command and status task blocks may be written by the host and asynchronously examined by the communications processor 12. The DIO unit also places a programmable interrupt vector on the system bus during system bus interrupt acknowledge cycles.

The system interface also allows for the communications processor 12 to initiate direct memory access between the local adapter memory and the system memory, for frame data or command/status interchange. Note that DMA is completely under adapter program control.

The communications processor 12 includes a Central Processing Unit which is based on the Texas Instruments TMS 38010 microprocessor, and with two exceptions provides a superset of its instructions (the signed multiply and divide instructions have been removed). The use of a cached workspace register file improves its performance, the simplest instructions now requiring only one memory cycle if their operands are in cache.

The memory interface 15 acts as the adapter bus controller and arbiter. It provides a flexible bus interface allowing a 2M byte memory of DRAM, SRAM, PROM and/or EPROM to be configured with a low chip count at low cost.

The memory interface 15 contains the code, data, stack and buffer mapping registers which are used to increase the logical address space of the communications processor 12 to 2M bytes.

The memory interface block will be described in detail later.

The Protocol Handler 13 provides the bit-speed functions of the protocol, including deserialisation of data between the communications processor 12 and the front-end chip 6. It provides for control and status lines to/from the front-end chip 6 for monitoring and controlling ring and adapter status. The protocol handler 13 provides for code violation detection/correction, start/end delimiter generation, checking of sent/received frames, address recognition, as well as four DMA channels for transferring data to and from adapter memory.

The protocol handler includes intelligent DMA controllers for automatically chaining between buffers for consecutive DMA operations. Four DMA channels are maintained, the receive and transmit sides each having a channel for data DMA and buffer manager channel DMA. The buffer manager channels re-initialise the data DMA channels for reception or transmission and automatically step down chains of such buffers as each is filled. This is done fast enough to guarantee availability of a channel even if frames appear back-to-back on the ring. The protocol handler 13 interupts the communications processor 12 at the end of frame, end of buffer, or when it reaches the end of a buffer chain.

The adapter support function block 16 contains the various functions that do not fit neatly into the other blocks. It is separated from the other blocks to make testing easier. It contains the general purpose timer, the interrupt prioritiser and multiplexer, the DRAM refresh controller and the ASFCTL, CPSTS, GPTLATCH, AINSTS, RCYLATCH and RCYDATA registers for adapter control and status.

The following table lists all the signals which are input into the adapter or output from it. For brevity the different blocks concerned are indicated by their initial letters as follows: system interface - SIF memory interface - MIF adapter support functions - ASF communications processor CP protocol handler - PH The invention is particularly concerned with the memory interface 15. Only those signals which are associated with it will be discussed in the following description.

+ + + + t SIGNAL NAME I/O 1 DESCRIPTION I BLOCK + + + F + SI/H- IN System Intel/Motorola Mode SIF Select S8/SHALT- IN System 8/16 Bit Bus Select SIF /Motorola Mode Bus Retry SRESET- IN System Reset SIF SCS- IN System Chip Select SIF SRSX IN System Register Select SIF SRS(O-1) IN System Register Select SIF SRS(2)/SBERR- IN System Register Select(2) SIF or Bus Error SBHE-/SRNl4 I/O System Byte High Enable or SIF Read/Not Write SWR-/SLDS- I/O System Write Strobe or SIF Lower Data Strobe SRD-/SUDS- I/O System Read Strobe or SIF Upper Data Strobe SRAS/SAS- I/O System Register Add.Strobe SIF or Memory Add.Strobe SRDY-/SDTACK- I/O System Bus Ready or Data SIF Transfer Acknowledge SALE OUT System Add. Latch Enable SIF +

SIGNAL NAME j I/O DESCRIPTION I BLOCK I SXAL OUT System Extended Add. Latch SIF SODIR OUT System Data Direction SIF SDBEN- OUT System Data Bus Enable SIF SOWtl- OUT System Bus Owned SIF SBCLK Ill System Bus Clock SIF SHRQ/SBRQ- OUT System Hold Request or Bus SIF Request SHLDA/SBGR- IN System Hold Acknowledge or SIF Bus Grant SBBSY- IN System Bus Busy and Scan SIF Input SBRLS- IN System Bus Release SIF SINTR/SIRQ- OUT System Interrupt Request SIF SIACK- IN System Int. Acknowledge SIF SADHtO-7) I70 System Add /Data Bus High SIF Byte SADL(0-7) I/O System Add./Data Bus Low SIF Byte SPH I/O System Parity High SIF SPL I/O System Parity Low SIF MBCLK1 OUT Adapter Bus Clock 1 MIF MBCLK2 OUT Adapter Bus Clock 2 IF MADH(O-7) I/O Adapter Memory Address, MIF Data and Status ~ ~ +

t + + t t SIGNAL NAME l I/O DESCRIPTION BLOCK MADL(0-7) I/O Adapter Memory Address and MIF Data MAXPH I/O Adapter Memory Extended MIF Address and Parity MAXPL I/O Adapter Memory Extended MIF Address and Parity MAXO OUT Extended Address Bit Mux'd MIF with Address Bit A12 MAX2 OUT Extended Address Bit Mux'd IF with Address Bit A14 MRAS- OUT DRAM Row Add. Strobe , IF MCAS- OUT DRAM Column Add. Strobe MIF MW- OUT MIF Write Cycle Indicator MIF MAL- OUT Address Output Transparent MIF Latch Strobe MDDIR ISO Direction Control for MIF Bidirectional Buffers MBEN- OUT Bidirectional Buffer MIF Output Enable MROMEN- OUT Chip Seiect for EPROM's MIF Mux'd with Address Bit A13 MBIAEN- OUT Memory Burnt-In Address MIF Enable MOE- OUT DRAM Output Enable MIF MACS- IN Adapter Chip Select MIF RESET OUT RESET- Outputted via MIF MIF t + + +

+ + + SIGNAL NAME j I/O I DESCRIPTION l - - BLOCK g t + t EXTINT(0-3)- I/O External Interrupt Request ASF Pins MBRQ- i/O Adapter Memory Bus Request MIF MBGR- ISO Memory Bus Grant MIF VDDL (2 Pins) IN Logic Power Supply All Blocks VSSL (2 Pins) IN Logic Ground Connections All Blocks VDDO (6 Pins) IN Output Buffer Power Supply Buffers VSSO C6 Pins) IN Output Buffer Ground Con'n. Buffers VDDI (1 Pin) IN Input Buffer Power Supply Buffers VSSI (2 Pins) IN Input Buffer Ground Conntn. Buffers VSSC (2 Pins) IN Clean Power for D/P Buffs Buffers NMI- IN Non-Maskable Int. Request CP CLKDIV IN Clock Divider Select CP and NIF OSCIN IN External Oscillator Input MIF TESTt0-5) IN Test Control and SIF/PH MIF, SIF and Only Mode Select ASF(O-2 Only) PH(3 & Only) FEDRVR OUT FEC Txmitter Driver Data + PH FEDRVR- OUT FEC Txmitter Driver Data - PH FEFRAQ OUT FEC Frequency Acquisition PH Select FENSRT- OUT FEC Insert Control and Pit Scan-path Output FERCLK IN FEC Received Clock PH FERCVR IN FEC Received Data PH FEREDY- IN FEC Ready PH FEWFLT IN FEC Wire Fault Detect PH . + +

SIGNAL NAME I/O DESCRIPTiON I BLOCK + + + + FEWRAP OUT FEC Internal Wrap Select PH and Scan-path Output.

PXTALIN IN Freq. used by PH to Clock PH Data out of Elastic Buffer.

FEOSC OUT 8 MHz Oscillator Output. MIF Goes to PXTALIN in 4 MBps Adapter.

FEGOSC OUT PXTALIN gated by FEFRAQ and MIF supplied to FEC.

PRTYEN IN Parity Enable SIF BTSTRP IN Bootstrap. RAM/RON Select SIF for Chapters 0 and 31 XMATCH IN Input Signal from an PH External Address Checker.

XFAIL IN Input Signal from an PH External Address Checker.

INPUT(O) IN General Purpose Input to SIF ACTL Register and Scan Path Input.

SYNCIN- IN Input for synchronization MIF pulse from external logic in a tnulti-Eagle system.

ROMDIS- IN Default value for ROM Bit SIF in ACTL register.

MREF OUT Indicates MIF is performing MIF a refresh cycle.

It is a feature of the integrated circuit shown in Figure 1 that the memory interface 15 provides the signals required for the different types of memory, DRAM, SRAM, PROM and EPROM, to which it is connected. The interface 15 interfaces between the memories and the internal bus system of the integrated circuit so that the other modules of the circuit need only provide the signals required by the internal bus system of the circuit. Figures 2(a) and 2 (b) together show the functional blocks of which the memory interface 15 is composed together with the internal bus signals which each block receives and the pins for the input/output signals to the different types of external memory.

The memory interface 15 has five main functions: 1. To generate all the internal clocks, including the test clocks), required throughout the adapter (with the exception of the system clocks of the system interface 14, and the serial clocks of the protocol handler 13), from an external clock input.

2. To arbitrate between all devices requiring access to the internal address and data buses 17,18 and the external memory bus. These devices are the DRAM refresh control in the adapter support functions block 16, an external bus master, the four machines of the protocol handler 13 (RX DMA, TX DMA, RX buffer manager, TX buffer manager), the two machines of the system interface 14 (DMA and DIO), and the communications processor 12.

3. To perform an address mapping function for access to external adapter memory when the communications processor 12 performs a memory access through the 32 byte code "window" in chapter 0, the 16K byte data "window" in chapter 1, two other data windows one of 8K bytes and the other of 4K bytes in chapter 1, a 2K byte stack "window" in chapter 1 and the two 1K byte buffer "windows" in chapter 1.

4. To act as an external memory bus controller by providing all necessary signals to easily interface to memory, whether it be DRAM, SRAM, EPROM or PROM, with a minimum amount of additional logic, and to access on-chip ROM if provided; and 5. To#check parity on internal data transfers or to/from memory if required to do so, to generate parity (if not already generated) for writes to memory, and add parity to internal data transfers (if not already generated).

Since the main function of this block is to interface to the adapters memory it is referred to as the Memory InterFace.

The operation of the memory interface 15 will be described by breaking down the overall function into a number of functional blocks each of which controls a specific part of the operation.

The generation of the internal clocks is straightforward and will not be described in detail. This is performed by the block 30.

The arbitration block 31 determines which device within the adapter system has the highest priority bus request pending, and allows that device to have bus ownership during the next cycle. (Since memory bus cycles and internal bus cycles are equal in length, they will be referred to simply as cycles).

The order of priority assigned to the devices for which arbitration is used is shown in the following table: Priority Level Device 0 (Highest) DRAM refresh controller 1 External bus master 2 PH TX DMA Protocol handler DMA transmitter 3 PH RX DMA Protocol handler DMA receiver 4 Protocol handler transmitter buffer manager 5 Protocol handler receiver buffer manager 6 System interface DIO 7 System interface DMA 8 (Lowest) Communications processor With the exception of the communications processor each device intefaces to the arbitration logic with two signals, a bus request- and a bus grant-. The arbitration logic uses these to select the highest priority device requesting bus access and drives the corresponding bus grant- signal low, negating all other bus grants inactive high.The communications processor is granted bus access whenever none of the other devices request it, so does not supply a bus request signal.

In adapter without CP code in EPROM, it is necessary to prevent the communications processor gaining access to its code until it has been down loaded into adapter RAM from the host system through the system interface DIO. The CPHALT bit in the ACTL register of the system interface is effectively passed directly to the arbitration logic to inhibit the bus grant signal to the communications processor. When the CPHALT bit is set to zero, bus access to the communications processor will be granted whenever no higher priority devices require it. The adapter has a mode in which the communications processor is never granted bus access, thus effectively disabling it.

The adapter has two modes, these are normal mode and CP-less mode. The modes are selected by an external pin of the circuit. In normal mode all functions are available, and the device acts as memory bus arbiter and adapter interrupt handler. The other mode is CP-less mode, which maintains all functionality except that the CP is disabled, and it behaves as a slave to another adapter. In this mode it must request the bus from an external arbitrator, (e.g.

in a master (normal mode) adapter), and outputs prioritised interrupt requests to an external interrupt handler, (e.g.

in the master (normal mode) adapter).

The adapter also has various test modes controlled by block 32 in response to signals on pins TESTO - TESTS. The test modes will not be described.

The memory interface provides through blocks 33, 34 and 35 the capability to interface to 2 megabytes of memory which can be comprised of a mixture of PROM, EPROM, SRAM and DRAM. by outputting a 20-bit word address in a manner suitable for these memory types.

The address is provided on the MADL(07), MADH(07), MAXPL, MAXPH, MAX2, MAXO and MROMEN- pins. The memory interface multiplexes address, status information and data on the MADH and MADL buses, and address and parity on the MAXPH and MAXPL pins. MAX2 carries two multiplexed address signals; AX2 and A14. MAXO carries two multiplexed address signals; AXO and A12. MROMEN- carries the EPROM enablesignal multiplexed with A13.

The full 20-bit address is made available on MADL(07), MADH(0-7), MAXPL, MAXPH, MAX2, MAXO during the first quarter of each memory cycle for latching for EPROM and SRAM addressing, and multiplexed on MADL(0-7), MADH(0-7), MAXPL and MAXPH during the first half of the cycle for direct interfacing to DRAMs.

The availability of A12, A13 and A14 on MAXO, MROMEN and MAX2 respectively, during three quarters of the cycle, makes possible an interface requiring no additional logic to a PROM containing the adapter's Burnt-In-Address (BIA).

The communications processor 12 is limited by its architecture to generating a 16-bit word address, which can address 128K bytes of memory which is split into two 64K chapters, one of which is addressed during code fetches, (opcodes and immediate operands); the other is addressed during data reads or writes. These are chapters 0 and 1 respectively. (Their byte addresses are written as 00.XXXX and 01.XXXX respectively). Note that although the communications processor outputs a 20-bit word address the four most significant bits are always 0000, since it can only address a 64K word range of addresses.

In the adapter however, provision is made to allow the communications processor to access indirectly the full 2 megabytes of address space, by performing an address mapping function on a specific address range within chapter 0, referred to as the code window, and six separate address ranges within chapter 1, that is, the three data windows, a stack window and two buffer windows. When a memory access is performed at an address within one of the windows the most significant address bits output by the communications processor are substituted by the memory interface by the same number of bits from a memory interface register to create a new 20-bit address; the least significant bits being provided by the communications processor and the most significant bits being provided by the memory interface register. This address is then used to perform the memory access.The register containing the new most significant bits of address used in this address mapping function is referred to as a mapper register. One is provided for chapter 0 code window accesses, called the CODEMAP register, a second for chapter 1 data window accesses, called the DATAlMAP register, a third for chapter 1 data window accesses, called the DATA2MAP register, a fourth for chapter 1 data window accesses, called the DATA3MAP register, a fifth for chapter 1 stack window accesses called the STACKMAP register, a sixth for chapter 1 buffer window accesses, called the BUFlMAP register, and a seventh for chapter 1 buffer window accesses, called the BUF2MAP register. On communications processor accesses to addresses other than to one of the windows, the address output by the communications processor is not altered by the memory interface but is used directly for the memory access.

The code window is designated as a 32K byte range of addresses between 00.0000 and 00.7FFF. Wh-en the communications processor performs a code fetch within this address range the memory interface recognises this and will substitute the six most significant bits of the address output by the communications processor with six bits from the CODEMAP register. The CODEMAP register is a 16-bit register existing in the memory interface at addresses 01.0160 in normal mode. The six least significant bits used in the address translation are contained in bits 5 to 10 of this register. The resultant 20-bit address is then output on the memory bus for the code fetch from memory.

The CODEMAP register will return the value written to bits 5 to 10 when it is read. The other bits will always read as 0 and writing to them has no effect. The CODEMAP register will be set to 0000 by reset so that the address translation function will have no effect upon the resultant address until the CODEMAP register value is changed.

The data window is designated as a 16K byte range of addresses between 01.8000 and 01.BFFF. When the communications processor performs a data transfer within this address range the memory interface recognises this and will substitute the seven most significant bits of the address output by the communications processor with seven bits from the DATAMAP register. The DATAMAP register is a 16-bit register existing in the interface memory at address 01.0162 in normal mode. The seven bits used in the address translation are contained in bits 5 to 11 of this register.

The resultant 20-bit address is then output on the memory bus for the data transfer to or from memory.

The DATAMAP register will return the value written to bits 5 to 11 when it is read. The other bits will always read as 0 and writing to them has no effect. The DATAMAP register will be set to 0060 by reset so that the address translation function will have no effect upon the resultant address until the DATAMAP register value is changed.

The data 2 window is designated as an 8K byte range of addresses between 01.C000 and 01.DFFF. When the communications processor performs a data transfer within this address range the memory interface recognises this and will substitute the eight most significant bits of the address output by the communications processor with eight bits from the DATA2MAP register. The DATA2MAP register is a 16-bit register existing in the memory interface at address 01.0164 in normal mode. The eight bits used in the address translation are contained in bits 5 to 12 of this register.

The resultant 20-bit address is then output on the memory bus for the data transfer to or from memory.

The DATA2MAP register will return the value written to bits 5 to 12 when it is read. The other bits will always read as 0 and writing to them has no effect. The DATA2MAP register will be set to 0070 by reset so that the address translation function will have no effect upon the resultant address until the DATA2MAP register value is changed.

The data window 3 is designated as a 4K byte range of addresses between 01.BOOT and 01.EFFF. When the communications processor performs a data transfer within this address range the memory interface recognises this and will substitute the nine most significant bits of the address output by the communications processor with nine bits from the DATA3MAP register. The DATA3MAP register is a 16-bit register existing in the memory interface at address 01.0166 in normal mode. The nine bits used in the address translation are contained in bits 5 to 13 of this register.

The resultant 20-bit address is then output on the memory bus for the data transfer to or from memory.

The DATA3MAP register will return the value written to bits 5 to 13 when it is read. The other bits will always read as 0 and writing to them has no effect. The DATA3MAP register will be set to 0078 by reset so that the address translation function will have no effect upon the resultant address until the DATA3MAP register value is changed.

The stack window is designated ås a 2K byte range of addresses between 01.FOOT and 01.F7FF. When the communications processor performs a data transfer within this address range the memory interface recognises this and will substitute the ten most significant bits of the address output by the communications processor with ten bits from the STACKMAP register. The STACKMAP register is a 16-bit register existing in the memory interface at address 01.0168 in normal mode. The ten bits used in the address translation are contained in bits 5 to 14 of this register.

The resultant 20-bit address is then output on the memory bus for the data transfer to or from memory.

The STACKMAP register will return the value written to bits 5 to 14 when it is read. The other bits will always read as 0 and writing to them has no effect. The STACKMAP register will be set to 007C by reset so that the address translation function will have no effect upon the resultant address until the STACKMAP register value is changed.

The buffer window 1 is designated as a 1K byte range of addresses between 01. F800 and 01. FBFF. When the communications processor performs a data transfer within this address range the memory interface recognises this and will substitute the eleven most significant bits of the address output by the communications processor with eleven bits from the BUFlMAP register. The BUFlMAP register is a 16-bit register existing in the memory interface at address 01.016A in normal mode. The eleven bits used in the address translation are contained in bits 5 to 15 of this register. The resultant 20-bit address is then output on the memory bus for the data transfer to or from memory.

The BUFlMAP register will return the value written to bits 5 to 15 when it is read. The other bits will always read as 0 and writing to them has no effect. The BUFlMAP register will be set to 007E by reset so that the address translation function will have no effect upon the resultant address until the BUFlMAP register value is changed.

The buffer window 2 is designated as a 1K byte range of addresses between bl.FC00 and 01.FFFF. When the communications processor performs a data transfer within this address range the memory interface recognises this and will substitute the eleven most significant bits of the address output by the communications processor with eleven bits from the BUF2MAP register. The BUF2MAP register is a 16-bit register existing in the memory interface at address 01.016C in normal mode. The eleven bits used in the address translation are contained in bits 5 to 15 of this register. The resultant 20-bit address is then output on the memory bus for the data transfer to or from memory.

The BUF2MAP register will return the value written to bits 5 to 15 when it is read. The other bits will always read as 0 and writing to them has no effect. The BUF2MAP register will be set to 007F by reset so that the address translation function will have no effect upon the resultant address until the BUF2MAP register value is changed.

The window mapping function is only available for use by the communications processor. The window mapping functions are not available to the system interface, protocol handler or any external bus master. When any of these devices accesses an address within the range of a window the address will not be translated, but passed directly onto the memory bus.

The memory interface 15 provides all of the control signals required to interface directly with DRAM, EPROM, PROM and SRAM, and also provides several internal control signals. its function is best described by explaining the signals entering and leaving it as shown in Figures 2(a) and 2(b). The signals are as follows: MRAS- This signal output by the MIF is the row address strobe for DRAMs. It is taken low whilst the row address is valid on MADL(0-7), MAXPH and MAXPL. It is also taken low during refresh cycles when the refresh address is valid on MADL (0-7). When the arbitration logic grants access to an external bus master this pin will become high impedance to allow the external device to control the signal.

MCAS- This signal output by the MIF is the column address strobe for DRAMs. It is taken low during every cycle whilst the column address is valid on MADL(0-7), MAXPH, except when one of the following conditions occurs: ...When the address is reserved for BIA ROM.

00.0000 - 00.000F) When the address is assigned to be on-chip ROM (i.e. when the ROM bit in the SIF's ACTL register is one and an access to an address in the range 00.C000 - 00.FFFF is made with MACS- asserted low).

When the address is assigned to be EPROM (i.e. when the BOOT bit in the SIF's ACTL register is zero and an access is made to 00.XXXX or lF.XXXX).

When the address is one of the on-chip registers. ( 01.0100 - 01.01FF in normal mode, or 01.0100 - 01.07FF in CP-less mode, when MACS- is asserted. (MCAS- will be issued if MACS- is not asserted)).

...The cycle is a refresh cycle, in which case MCAS- is driven out at the start of the cycle before MRAS-, or The cycle is under the control of an external bus master. In this case the output will be tristated to allow the external device to control the signal.

- MW- This signal output by the MIF indicates that the cycle is a read if it remains high, or a write if it is driven low. The data on MADH(0-7) and MADL(0-7) buses and the parity on MAXPH and MAXPL are valid on the falling edge of MW-during a write cycle. When the arbitration logic grants access to an external bus master this pin will become high impedance to allow the external device to control the signal.

-MAL- This signal output by the MIF is a strobe signal for transparent latches used to sample the address output at the start of the cycle in order to create a static address for address decode, SRAM address or EPROM address. At the falling edge of this signal the full 20-bit word address is valid on MAXO, MAXPH, MAX2, MAXPL, MADH(0-7) and MADL(0-7), and the EPROM enable-signal is valid on MROMEN-.

Three 8 bit transparent latches can therefore by used to retain a 20-bit static address and EPROM enable-signal throughout the cycle.

When the arbitration logic grants access to an external bus master this pin will become high impedance to allow the external device to control the signal.

-MDDIR- This signal is an output when an internal device has bus mastership and an input when an external device is bus master.

It is used as a direction control signal for bidirectional buffers used to reduce loading on the MADH and MADL buses. When it is low the cycle is a bus master read, when high the cycle is a bus master write. When an external device has bus mastership the MIF looks at this signal rather than MW- to determine if it is a read or write cycle.

- MBEN- This signal output by the MIF is used in conjunction with MDDIR, and enables the outputs of bidirectional buffers on the MADH and MADL buses in the direction selected by MDDIR. This signal will not be issued during DRAM refreshes or on-chip address accesses, (registers or ROM). When the arbitration logic grants access to an external bus master this pin will become high impedance to allow the external device to control the signal.

- MROMEN- This signal output by the MIF is used to provide an active low chip select signal for EPROMs during the first quarter of a memory cycle, if the BOOT bit of the SIF's ACTL register is zero and a READ from an address in the range 00.0010 - 00.BFFF, lF.0000 - 1F.FFFF, or 00.C000 - 00.FFFF (when the ROM bit in th SIF's ACTL register is zero), performed. It will remain inactive high during the first quarter of the cycle for writes to these addresses, or access of any address when BOOT is one. During the final three-quarters of the memory cycle this pin will output the A13 address signal which can be used in conjunction with A12 and A14, output on MAXO and MAX2 respectively, to address a BIA PROM.When the arbitration logic grants access to an external bus master this pin wil become high impedance to allow external device to control the signal.

MBIAEN- This signal output by the MIF is used to provide a chip select-signal for a POM containing the adapter's Burnt-In-Address (BIA). The signal will be taken low for any READ from addresses in the range 00.0000 00.000F. The signal will remain inactive high for writes to these addresses, or access of any other address. When the arbitration logic grants access to an external bus master this pin will become high impedance to allow the external device to control the signal.

- MOE- This signal output by the MIF is used to enable the outputs of DRAMs during a read cycle. On DRAMs which have a "xl" orienta tion, (e.g. TMS4256s; 256K x 1), MOE is used to drive the output enable signal on the buffer, (a 244 type circuit), on the 0 outputs which isolates the 0 outputs from the data bus. This is required as the DRAM's Q outputs output rubbish during the write cycles. On "x4" DRAMs, (e.g. TMS4464s; 64K x 4), MOE connects directly to the DRAM's output enable pin. MOE- is taken low during read cycles under the same conditions that MCAS- is taken low, though during write cycles and refresh cycles it will remain inactive high. When the arbitration logic grants access to an external bus master this pin will become high impedance to allow the external device to control the signal.

- MBCLK1, MBCLK2 These two signals are always outputs, even when bus access is granted to an external bus master. They are the internal clocks corresponding to the CP's H1 and H2 phases respectively.

- MACS- This signal is always an input, and is used as an adapter chip select-signal when an address corresponding to on-chip registers or on-chip ROM is accessed. The access (read or write) to on-chip registers ( 0i.0100 01.01FF in normal mode, 01.0100 - 01.07FF in CP-less mode), will take place only if the MACS- pin is low, regardless of whether an internal device or external bus master is performing the access. If an internal device is performing a read and MACS- remains high the MIF will instead look off-chip for the data. (From an external adapter circuit).

Similarly the on-chip ROM will only be accessed if MACS- is taken low when the ROM bit in the SIF is a one and a read is performed from an address in the range 00.C000 - 00.FFFF. If MACS- is not asserted the data will be read from external memory of the type determined by the BOOT bit in the SIF. When external chip selecting is not required the MACS- pin can be wired low to allow internal accesses of registers, and on chip ROM (if enabled). A signal signifying an on-chip access is supplied by the MIF to the SIF, PH, ASF and CP to indicate that a valid on-chip register access is to be performed.

The MIF will prevent writes to on-chip registers by either the SIF DMA or the PH, even when MACS- is low by retaining the on chip access signal at the inactive value. The CP and the external bus master are the only devices allowed to perform on-chip writes, however SIF DIO can perform writes to on-chip registers providing that the IOWREN bit in SIFCTL is a one, but even under this condition it cannot write to any of the PH registers.

Any bus master can read from any on-chip register at any time, (providing that MACS- is zero).

MREF- This signal which is an output at all times is an indication that the cycle occurring on the memory bus is a DRAM refresh cycle, if operating in normal mode. It has two uses:- 1) To disable MCAS- to DRAMS which do not support CAS-before-RAS refresh. This is simply achieved by DRing together MCAS- and MREF and using the result as the CAS-signal for the DRAMs; and 2) to enable MCAS- to all DRAMs which use CAS-before-RAS refreshing when bank decoding on MCAS- is being used. If operating in a CP-less mode it indicates that the refresh controller is asking for the bus, to allow a refresh bus request on a slave adapter to be distinguished from any other bus request. This output is not tristated when bus ownership is given to an external device.

-MRESET- This signal which is output at all times is simply the internal reset signal passed through an output buffer. It enables external glue logic, external peripherals or external adapters to be reset as required. It is driven low during reset, and high at all other times. It does not tristate when the memory bus ownership is given to an external device.

All the following signals have chip-on pullups which operate in all modes except CP-less mode. MAXO, MAX2, MAXPH, MAXPL, MADH(0-7), MADL(0-7), MRAS-, MCAS-, MW-, MDDIR, MAL-, MOE-, MBEN-, MROMEN-, MBIAEN- and MBRQ-. MBGRhas a pullup which operates only in CP-less mode. MCAS- has a pullup which operates in all modes. These prevent spurious events from occurring during bus handover between the MIF and an external bus master, and also during reset.

Figures 3, 4,5 and 6 show the connections of the output signals from the memory interface 15 to DRAM, PROM, EPROM and SRAM respectively. The connections are made directly to the memory chip or chips in the case of DRAM and PROM, but 21 and 20 latches respectively are required for the EPROM and SRAM chips. The purpose of the latches is to sustain the address inputs to the chips. Note also that an OR-gate is required to produce the output enable signal for the EPROM.

The memory interface 15 includes parity logic which is responsible for parity checking of all internal data transfers and generating parity on some internal data transfers, as well as checking or generating parity for memory bus data transfers.

The parity checker, which may be the type described in British Patent Application No. 88.26655 (TIL-12375), verifies the parity of every data transfer on the internal data bus. It also checks parity of every data transfer on the memory bus. In both cases it achieves this by checking each byte for the correct odd parity.

The parity checker can be disabled for test purposes.

The parity generator also provides parity for all data transfers from the internal bus to the memory bus that do not already have parity provided. Additionally it provides parity for all internal transfers which do not already have parity. Since the memory interface contains the bus arbitration logic, it is always aware of which subblock of the integrated circuit is bus master, and can thus determine whether or not it needs to provide parity for the current data transfer.

In a system with parity enabled all data stored in memory must have parity. Thus when data is passed to the memory interface from memory it does not need to be generated by the memory interface.

However when it is necessary for the MIF to provide parity on internal data transfers there is an eighth of a cycle delay between data bits and parity bits.

The protocol handler 13 has both a parity generator and checker. These are both located in the logic interfacing the serial and parallel sides of the protocol handler 13. They are used only for data transfers to and from the ring.

Other than in frame-data transfers to and from the ring, all parity on data transfers to and from the protocol handler are handled by the memory interface.

Frame data on the ring or in the serial form in the front end chip 6 or protocol handler 13 is protected by CRC coding. When the frame data is put into parallel form inside the protocol handler, the protection continues in the form of parity. The protocol handler parity generator provides the necessary two parity bits for each data word as it passes the frame data to the parallel side of the protocol handler and onto the internal data bus.

Parity generated by the protocol handler has the same timing as its associated data.

The parity checker in the protocol handler is used to check the parity of data as it is passed from the parallel side to the serial side and thus to the front end chip and the ring.

The communications processor 12 does not have any parity checking or generation facilities of its own; all parity functions related to data transfers to or from it are performed by the memory interface.

The adapter support functions 16 does not have any parity checking or generation facilities; it relies on the memory interface.

The system interface 14 has two parity generators and two parity checkers. One generator/checker pair is used for data transfers to the host system and the other pair for data transfers from the host.

Unless parity has been disabled, the system interface always checks the internal bus parity of data being transferred to the host.

Irrespective of whether parity is disabled or not, the system interface generates parity for the data to be transferred to the host. Thus if parity had been provided to the system interface from the external data#bus, it would check that parity and then regenerate it for the system interface bus 2. The system interface also checks the parity of data supplied to the integrated circuit from the host computer.

The memory interface 15 includes the arbitration logic which determines which of the blocks 12, 13, 14, 15 and 16 shall have the use of the internal bus system comprising the data, address, parity and read/write buses 17, 18, 19 and 20 (Figure 1). Figure 7 shows the arbitration logic as a block 35 connected to receive requests for the use of the bus system from several modules 30, 31, 32, (representing the blocks 12 to 16 but possibly including other blocks if such are included). When the block 35 has determined which of the modules shall have the use of the bus system it sends a grant signal to that module. The request and grant signals are carried by individual conductors 34. The internal buses have the same reference numbers in Figure 7 as in Figure 1.

The arbitration logic 35 can also take into account a request for access to the internal bus system from outside the integrated circuit. The external request signal and the grant signal to the unit making the external request are carried by conductors 36. In order that the external unit can feed signals to and derive signals from the internal bus system interface logic 37 is provided.

Figure 8 is a diagram of the interconnections of two adapters, one in master mode and the other in slave mode.

The arbitration logic 50 of the master adapter is connected to the arbitration logic 52 of the slave adapter by external request and external grant conductors 55. Both adapters include interface logic 51, 53 connecting an external bus system 54 respectively to the internal bus systems of the adapters. An external device, which may for example be memory of some kind, is represented by the block 56 which is connected to the external bus system 54 so as to be usable by either adapter. The use of the signals described above to establish the master and slave modes of operation of the two adapters is described above with reference to the signals involved.

To illustrate the forms of the signals supplied by the memory interface to the external memory chips examples of some of the signals are shown in Figures 9(a), 9(b), 10(a) and 10(b) which show the waveforms of the signal involved in writing to and reading from a ROM which does not have the address of the adapter burnt-in (non-BIA), is not an EPROM and does not have an on-chip address. It is not proposed to describe these figures in detail because the signals themselves are fully described above. The purpose of these figures is to aid the visualisation of the signals.

Although the invention has been described with reference to a specific embodiment, it is not limited to that embodiment but it can be applied to any integrated circuit having several modules needing access to external memory of different kinds.

Claims (13)

CL#i#S:

1. An integrated circuit having a plurality of functional modules, an internal bus system having at least data and address buses interconnecting the modules and a memory interface connected to the bus system and to terminals of the integrated circuit for connection to the memory means, the memory interface enabling the one of the modules which is using the internal bus system at the time to transmit data to or receive data from read/write or readonly memory means of a plurality of different types external to the integrated circuit.

2. A circuit according to claim 1, wherein the address space of the external memory means is sub-divided between different types of memory means in a predetermined way, and the memory interface includes means responsive to address information on the address bus to select the correct form of data, address and control signals for the type of external memory means including the particular address.

3. A circuit according to claim 1 or 2, wherein the memory interface includes at least one address mapping register to enable a module having a limited address range to reach a greater range of addresses.

4. A circuit according to any preceding claim, wherein the memory interface includes means for allocating the use of the internal bus system to a particular one of the functional modules in response to requests for such use from the functional modules and according to a priority system.

5. A circuit according to claim 4, wherein the memory interface includes meons responsive to the identity of the functional module to which the use of the internal bus system is allocated at the time to block access to certain addresses or groups of addresses of the external memory means.

6. A circuit according to claim 4 or 5 including means responsive to the memory interface to provide an output indication of the identity of the functional module to which the use of the internal bus system is allocated at the time.

7. A circuit according to any one of claims 4, 5 and 6, wherein the circuit includes means for refreshing dynamic RAM external to the circuit and that means has the highest priority in the priority system.

8. A circuit according to any one of the prece ing claims in which certain of the functional modules employ parity for data checking and others of the functional modules do not provide parity bits, wherein the memory interface includes means for performing parity checks on data which includes parity bits and for adding parity bits to data it receives which do not include parity bits.

9. A circuit according to any one of claims 4 to 7, wherein the means for allocating the use of the internal bus system includes means enabling the memory interface to be connected directly to the memory interface of a similar integrated circuit so that two or more such integrated circuits can operate together, one integrated circuit acting as master and each other integrated circuit acting as slave to the one integrated circuit in control of the use of the internal bus system of the particular integrated circuit.

10. A circuit according to claim 9, wherein the means for allocating the use of the internal bus system has "request1 and "rant" connections relating to the control of allocation of the use of the internal bus system brought to external terminals of the circuit.

11. A circuit according to claim 9 or 10, including an external terminal for a signal to determine the master or slave status of the circuit.

12. A circuit according to any one of the preceding claims which is constructed as an adapter for connecting a computer to a local network and which includes in addition to the memory interface, a protocol handler, a communications processor and a computer system interface as the functional modules interconnected by the internal bus system.

13. An integrated circuit substantially as described herein and as illustrated by the accompanying drawings.