GB2218548A

GB2218548A - Digital signal processor

Info

Publication number: GB2218548A
Application number: GB8907982A
Authority: GB
Inventors: Peter Richard Dent; Rajpal Singh Bharya
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1988-04-12
Filing date: 1989-04-10
Publication date: 1989-11-15
Anticipated expiration: 2009-04-10
Also published as: JPH02119318A; GB2218548B; JP2930320B2; GB8907982D0; GB8808569D0; US5005150A

Description

1 1 IMPROVEMENTS IN OR RELATING TO DIGITAL SIGNAL PROCESSORS This

invention relates to a dicital signal processor constructed as all or part of an integrated circui.t.

Cordless telephones have been produced which enable a user to make telephone calls without having to go to a fixed installation. This enables, for example, business discussions to take place between, say, one person travelling on a train and another travelling in a car. The cordless telephone instrument itself is similar in size and shape to a conventional telephone hand-set and includes a radio transmitter and receiver for communicatina with a local telephone network station and some kind of manually operated switch arrangement such as a keyboard for entering the telephone number to be selected.

The first forms of such teleohones have used analocue signal transmission to convey the speech information, but it has been found that that form of communication is orone to interference from external noise. In order to overcome this problem the conversion of the voice signal to digital form has been proposed, but difficulties have been encountered in providing a sufficiently high bit rate for good quality voice reproduction. It has, for example, been iDror)osed to sample the voice siqnal at a rate of 8 kHz and to convert each sample to an 8-bit pulse code modulated (PCM) siqnal. This gives a bit rate of 64K bits per second which has proved to be inconveniently high for radio transmission. A reduction in the bit rate to 32K bits per second ccn be M signal to adaptive achieved by converting the PC differential pulse code modulation (ADPCM) encoded form. It has been found that this encoding of the voice signal does not detrimentally affect its quality and the resulting reduction in the bit rate renders the use of digital transmission of the voice signal possible without making excessive demands on the radio transmission from the cordless telephone to the network station.

Q 2 A general purpose microprocessor or microcomputer could be used for implementing the algorithm for converting the PCM signal into the ADPCM encoded form and back again, but cordless telephones have to be batterypowered if they are to be mobile and the use of a general purpose microprocessor or microcomputer requires too great a power consumption from it to operate satisfactory from batteries. In addition, such general purpose microprocessors and microcomputers are relatively expensive.

It- is an object of the Dresent invention to provide a digital signal processor-in which the power consummtion.and the complexity of the circuitry are significantly less than those of a general purpose microprocessor or microcomputer but of which its performance in a cordless telephone or any other similar applications is no less satisfactory.

According to the present invention there is provided a digital signal processor incorr)orated in an integrated circuit and including first and second sources of binary numbers, a parallel binarv multiplier having a first input port with a firgt plurality of conductors for receiving in parallel a first plurality of bits defining a first number, a second input port with a second plurality of conductors for receiving in parallel a second plurality of bits defining a second number, and an output port with a third plurality of conductors for transmitting in oarallel a third plurality of bits representing the product of the first and second numbers, the first plurality being substantially larger than the second pluralitv, a first data selecor connected from the first and second sources to the first input port of the multiplier, a second data selector connected from the first and second sources to the second input port of the multiplier, and means for controlling the operation of the first and second data selectors accordinc to the numbers of bits in the numbers from the first and second sources.

The first and/or second data selector may be arranged to be able to select two or more different first and/or 1 v 3 second pluralities of bits from the first or second source, thereby enabling the multiplier to multiply numbers having more bits than the first and/or second pluralities.

The first and/or second data selector may include latch means for storing the selected bits, thereby enabling the multiplier to multiply together two numbers from the same source.

A third data selector may be provided connected from the output port to a data bus of the processor to enable the bits representing the product produced by the multiplier to be shifted relative to the conductors of the bus so as to produce the effect of multit)lication or division by a power of two.

The first and second sources may be a random access memory (RAM) and a read-only memory (ROM) resiDectively. A vipe-line register may be included in a connection from the random access memory to a data selector, so as to enable a data item read from the random access memory to be apolied to the data selector at the same time as another data item is being applied to the random access memory for storage therein.

The output port of the multiplier may be connected to adding/subtracting means to enable the rapid execution of an algorithm for deriving an ADPCM encoded signal from a PCM signal or for deriving a PCM signal from an ADPICM encoded signal.

In the drawinqs:- FIGURE 1 is a block diacram of the circuitry of a cordless telephone; FIGURE 2 is a flow diaqram of an algorithm for encoding a PCM signal into ADPCM form; FIGURE 3 is a flow diagram of a algorithm for decoding a signal in ADPCM form into a PCM signal; FIGURE 4 is a block diagram of those parts of a digital signal processor which implement the algorithms shown in Figures 2 and 3; 4 FIGURE 5 is a block diagram of a circuit for converting a linearly coded PCM signal into a PCM signal compressed according to the A-law; FI-GURE 6 is a block diaaram of a circuit for expanding an A-law coded PCM signal into a linearly coded PCM signal; FIGURE 7 is a system diaqram for the ADPCM transcoder shown in Figure 1; and FIGURE 8 illustrates one possible lay-out for an integrated circuit form of a digital signal processor constructed using standard cells.

In Figure 1, the circuit of the cordless telephone is shown as a microphone 1 connected through an analogue to digital converter 2 to an encodina circuit 3 which encodes the PCM output from the converter 2 into ADPCM form. The converter 2 is arranged to compress the signal according to the A-Law when it converts it to digital form. The ADPCM signals from the encoder 3 are assembled in a oredetermined standard format by the circuit 4 and applied to the transmitter 5 which emits a frequency modulated RF signal which is broadcast via an antenna 6.

RF signals are also received via the antenna 6 and demodulated in a receiver 7 to produce formatted ADPCM encoded signals. A circuit 8 separates the ADPCM signals from synchronising and other signals and applies ADPCM signals to a decoder 9 which regenerates PCM signal from the ADPCM encoded signals received. A diqital to analogue converter 10 converts the PCM signals to analogue form and applies them to an earphone for reproduction to the. user. The frequency of the RF signal emitted by the transmitter 5 and received by the receiver 7 is controlled by a phaselocked loop circuit 12 controlled by a microcomputer 13. The microcomputer also controls the formatting of the ADPCM signals to be transmitted and the ser)aration of the ADPCM signals from the received signals after demodulation. A keyboard 14 is provided to enable the user to enter the telephone numbers with which the user wishes to communicate, the keyboard being connected to the microcomputer 13 which Z1 also causes the emission of apiDronriate calling signals and numerical signals from the transmitter 5 for establishing the required telephone connection. The analogue to digital converter 2 and the digital to analogue converter 10 are included in a single integrated circuit. The encoder 3 and the decoder 9 are included in a second integrated circuit. The two integrated circuits together form an ADPCM transcoder 15.

As the invention is concerned with the construction of the encoder 3 and the decoder 9, it is not proposed to describe the formatting, transmission and reception of signals. These processes may be carried out in any suitable manner.

The function of the encoder 3 is to receive the samples from the analogue to digital converter 2 and encode them into ADPCM form. In the example being described, the analogue to digital converter 2 samules the soeech signals received from the micronhone 1 at a rate of 8000 sam-ples -Per second, each sample beinq converted to an 8-bit digital PC-M signal. The encoder 3 receives the 8-bit PCM signal and using the algorithm illustrated in Ficure 2 encodes it as a 4-bit ADPCM signal. The algorithm shown in Figure 2 reauires as a first step the generation of an estimate of the next PCM signal to be received on the basis of one or more)revious PCM siqnals. The current PCM sicnal is then taken in and the difference between that and the estimated signal determined. The value of the error is then quantised and an appropriate digital signal generated which is. then output to the formatting circuit as the ADPI'M signal. The error is also used to update the prediction and assist in the formation of the estimate for the next PCM signal to be received. Various mathematical techniaues may be used to generate the signal estimate from the received PCM signals and many suitable technigues will be well-known to those skilled in the art.

The decoder 9 performs the reverse operation to the encoder 3, and a flow diagram of its algorithm is shown in Figure 3. As shown in Figure 3, a received ADPCM signal is 6 compared with an estimate based on the preceding ADPCM signals and the resulting error is dequantised using the same quantising law as was used in the encoder. The estimate is corrected using the dequantised error and the corrected PCM signal resulting is fed out to the digital to analogue converter 10. The error is also used to update the prediction and assist the formation of the next signal estimate ready for the next ADPCM signal.

Figure 4 is a block diagram of a digital signal processor used to implement the encoding and decoding functions just decribed. The instructions for performing the algorithms for the encoding and decoding operations are stored in microcode in a pROM 100 from which they are transferred to a latch 101 and a microcode control unit 102 which in turn addresses the ROM 100. A program counter 103 Drovides overall control of the unit 102 and the addressing of the ROM 100. Certain of the microcode instructions require data such as intermediate results into or read from a RAM 106. The 'RAM 106 data in the latch 101 via a conductor 104 via a bank selector 105. A 16-line wide 107 conveys data to be stored in the RAM it. The bus 107 is bonnected directly to to be entered is addressed by either directlv or input/outDut bus 106 or read from an inr)ut port of data selector 1, having the reference 108, and through a pipe-line register 128 to data selector 2, having the reference 109. These data selectors have second input ports which are connected bv 16-line buses to the output of a ROM 101 addressed by the output of a data selector 6, rekerence number 110, which also receives data from the latch 101. The data selector 108 has a 16-line output bus which is connected to a latch 112. The data selector 109 has an 8line output bus which is connected to a latch 113. The latches 112 and 113 are connected to respective input ports of a multiplier 114 via a 16-line and an 8-line bus respectively. The multiplier 114 is a parallel or simultaneous twos-complement multiplier and produces a product output on 23-line bus on receiving 16-bit and 8-bit parallel inputs from the latches 112 and 113 respectively.

Q 7 The data selector 5, reference number 115, receives the product output of the multiplier 114 and is able to shift it by up to 7 bits relative to a 30-line bus whih connects the selector 115 to an input port of an arithmetic logic unit 116.

An 8-bit PCM word is received at 117 and applied to an A-Law expander 118. A 13-bit output from the expander 118 is applied via a data selector 4, reference 119, to a 30line bus connected to a second input port of the ALU 116. A 4-bit ADPCM word can be entered at 120 and applied to a second port of the data selector 119. The ALU 116 has a 30bit output port which is connected to a 30-line bus The bus 121 Is connected to an accumulator register reference number 122, and an accumulator register 2, reference number 123. The out-puts of the registers 123 are connected to rest)ective input -ports of data selectors 110 and 119. A 4-bit ADPCM outDut word is obtained from the bus 121 and appears at 124. Thirteen lines of the bus 121 are connected to the input Dort of an ALaw compressor 125 having an 8-bit output forming a PCM output word at 126. The bus 121 is also connected to the input port of a data selector 3, reference number 127, having a 16-line output connected to the bus 107.

121. 1 ' 122 and Data Selector 1 + Latch 1 (components 108 and 112) These 1Derform a data select function between the data read from the RAM 106 and the ROM 111 for the wide, 16-bit, input path of the multiplier 114.

Data Selector 2 + Latch 2 (components 109 and 113)^ These select data from one of the sources listed below for the narrow, 8- bit, input path of the multiplier 114.

1) Bits 6-0 2) Bits 6-0 of the data read from the ROM 111 with output bit 7 zero. of the data read from the RAM 106 with output bit 7 zero.

3) Bits 14-7 4) Bits 14-8 8 of the data read from the RAM 106. of the data read from the P-AM 106 with output bit 7 equal to bit 6, i.e. sign-extended.

Options 1 and 2 are used when performing the lower accuracy 16-bit signed by 7-bit unsigned multiply operations. While options 2 and 3 are used to perform the 16 x 15 signed multiply operations. option 4 is used to provide a divide by 256 function. This configuration is used as in the majority of cases it is only necessary to perform a 16 x 7 multiplyoperation.

Data Selector 3 (component 127) This data selector is used for selecting the part of the output of the accumulator which is required for storing in the RAM 106. It is a three- way selector capable of selecting between:Input bits 1) Bits 15-0 2) Bits 27-12 3) Bits 29-15 OutDut bits Bits 15-0 Bits 15-0 Bits 14-0 with outiDut bit 15 eaual to bit 14, i.e. sign extended.

Data Selector 4 (component 119) This is used to select which of the two accumulator registers 122 and 123 and the two input ports is to be used for one of the ALU 116 inputs. The PCM input via 117 and 118 is zero-extended to produce a 30-bit input while.the ADPCM input via 120 is sign-extended to nroduce a 30-bit input.

Data Selector 5 (component 115) This data selector is used to shift selectively the output of the multiplier 114 to increase its dynamic range. It can select between the normal output of the multiplier 114 and that of the multiplier 114 multiplied by 32 or 128. The output is always siqn-extended to the left (more significant bits) and zero-filled to the right (less t 9 significant bits) to produce a 30-bit output value.

Data Selector 6 (component 110) This is used to select the address for the ROM 111 from one of the accumulator registers 122, 123 or from the microcode stored in the pROM 100. The outputs of the accumulator registers 122 and 123 are truncated to bits (60).

Pipe-lin"e Register 128 This is a 16-bit register which can provide temporary storage of data outiDut from the RAM 106. ft has three modes of operation determined by two control bits.

a) In the TRANSPARENT mode, the register does not store the incoming data but transmits them directly to the output with only a small delay between input and output. Any data stored in the register are not affected by the data transmitted.

b) In the READ-ONLY mode, data stored in the register are output from it to the data selector 2. The register does not store the data applied to its input.

c) In the READ-WRITE mode, the register stores the data incoming to it and outputs the stored data to the data selector 2 at the same time or at a later time.

Multiplier 114 This is a 16 x 8 2's complement full parallel multiplier producing a 23 bit 2's complement output.

Arithmetic Logic Unit (ALU) 116 This is an arithmetic unit capable of performing the arithmetic operations + and -, along with the logic operations AND, XOR, pass A and pass B. Bank Selector This block of logic divides the RAM 106 into three sections, and provides for bank selection between two of these sections while leaving the third section permanently available. The two bank switched sections are used to store separately in the RAM 106 values to be encoded and those to be decoded, enabling the same microcode subroutines to be used for both encoding and decoding operations, selection being by the bank select switch.

RAM 106 This is a block of 16-bit wide RAM used for storing the ADPCM encoder/decoder variables and for temporary storage purposes.

ROM 111 This is a block of 16-bit wide ROM used foi: storing the ADPCM encoder/decoder constants.

Accumulator Registers 1 and 2 (components 12 and 123) These are two 30-bit registers used to store temporary values during arithmetic operations. They can be used to address the ROM 111 directly in place of the microcode from pROM 100. There are two registers so that one register can be used.for storage of partially calculated coefficients while the other can simultaneously be used to address calculated addresses in the memory, and so that two Previous1v calculated memory addresses can be accessed-for a calculation.

A-Law compressor A circuit for converting a linearly coded digital signal in sign magnitude format into a digital signal compressed according to the A-Law. This is shown in Figure 5.

11 This circuit consists of a Priority detectOr/encoder and a series of four data selectors. The priority detector/ encoder receives the six bits of greatest significance of a linearly digitised signal and drives the data selector to perform a four from ten funnel shift, selecting the four sequential bits of the linearly digitised signal to be output as the four bits of least significance of the output compressed signal. The fifth, sixth and seventh bits of least significance selected are from those received by the priority detector by the prioity encoder. The sign bits is a direct copy of the sign.bit in the input. The circuitry can also handle linear signals in the range 0-31 (for ll-bit linear+sign bit).

Input Priority Detector Priority Encoder Funnel shifter output Output Output labcdxxxxxx 1000000 ill abcd Olabcdxxxxx 0100000 110 abcd 001abcdxxxx 0010000 101 abcd 0001abcdxxx 0001000 100 abcd 00001abcdxx 0000100 011 abcd 000001abcdx 0000010 010 abcd 000000abcde 0000001 00a bcde A-Law expander 118 A circuit for converting an A-Law coded digital signal into a linearlv coded digital siqnal in sian magnitude format. This is shown in Figure 6.

This circuit consists of a three-to-seven binary decoder to find the ALaw segment followed by a series of multiplexers of various widths to map the four sub-segment bits onto the relevant bits of the linear data. To improve data quality the circuitry fills an assumed '1' into the linear bit below that for which data is contained in the ALaw samiDle.

12 Input Priority Decoder Output Data Selector - output lllabcd 1000000 labcd1000000 110abcd 0100000 Olabcd100000 101abcd 0010000 001abcd10000 100abcd 0001000 0001abcd1000 Ollabcd 0000100 00001abcd100 010abcd 0000010 000001abcd10 00abcde 0000001 000000abcdel A sample, either PCM incoming at 117 or ADPCM incoming at 120, is used to calculate the error in the prediction by subtraction in the ALU 116 and the error is transferred to the RAM 106 to correct the prediction for the next sample. The calculations involved in the prediction are performed by multiplications in the multiplier 114 and additions or subtractions in the ALU 116. The multiplier alone can multiply a 16-bit (15 bits+sign) number by an 8 bit (7 bits+sign) number to give a 23-bit (22 bits+sign) product. By using the data selectors 108, 109, and 115 in conjunction with the multiplier two 16-bit numbers can be multiplied together, one 16- bit number being divided into two 8-bit parts by the data selector 109 and applied in turn to the multiplier, the two separate products being added together by the ALU 114 using an accumulator register and the data selector 119, one product havina a leftward shift of 8-bits Droduced by the data selector 115. It will e understood that the architecture of the processor enables it to operate in a pipelined manner for most calculations (i.e. those that require no 16x16-bit multiplications), so that they can be executed very quickly without the need to recycle partial results, and that even the product of two 16bit numbers can be produced in about twice the time required for two 16x8-bit multiplications. The pipe-line register 128 is controlled by the program to store selectively the data output by the RAM 106. The register 128 enables data 13 to be written into the RAM 106 and also applied to the multiplier 114 at the same time, thereby providing a useful saving of time in the execution of the program. The output of the ALU can be recycled through the data selector 127 alone or via the RAM 106.

On the other hand# the provision of a 16x8-bit multiplier with some data selectors in place of a 16xl6-bit multiplier saves a substantial area of silicon (or other semiconductor) chip.

The data selectors are numbered 1 to 6 for the purpose of identifying them in the program stored in the pROM 100. The listing of the program in microcode forms an appendix to this specification. They implement the encoding and decoding algorithms outlined above with reference to Figures 2 and 3. It will be appreciated that the programs executed by the processor will either convert an 8-bit PCM word entered at 117 into a 4bit ADPCM word output at 124, or will convert a 4-bit ADPCM word entered at 120 into an 8bit PCM word output at 126.

The converter 2 is arranqed to compress according to the A-Law the siqnal from the micronhone 1 as it converts it from analogue to PCM form and the converter 10 is arranged to expand the signals accordinq to the A-Law as it converts them from PCM to analogue form. The converters 2 and 10 are standard items for telecommunications use. Since the algorithms for encoding and decoding the digital Siqnals have to onerate on linearly coded digital signals, it is necessary to expand the PCM signals received from the converter 2 before performing the encoding algorithm and to compress the PCM signals resulting from the decoding algorithm before applying them to the converter 10.

Figure 7 is a block diagram of the whole of the integrated circuit 15 shown in Figure 1 except for the analogue to digital converter 2 and the digital to analogue converter 10. The components of Figure 7 which correspond to those shown in Figure 4 have the same references as in that Figure. The whole of Figure 4 except for the expander 14 118 and compressor 125 is included in the rectangle 300. The compressed PCM signal enters on the left of a CODEC shift register 301 and is transferred from that register to the expander 118. Compressed PCM Siqnals are received from the compressor 125 and are output on the right of the register 301. An interface 302 handles the input and output of ADPCM 4-bit words. A timing control circuit 303 supplies clock signals for synchronising the operations of all the components of the integrated circuit.

The integrated circuit itself is constructed from 1-PM CMOS Standard Cells. Details of such standard cells are published in a databook produced by Texas Instruments Incorporated and obtainable from them. If desired, the circuit could be constructed from other types of standard cell, one such type being 2-pM CMOS Standard Cells, a databook describing which is z)roduced by Texas Instruments IncorDorated.

Figure 8 shows in diagrammatic form one way in which the standard cells could be assembled on a surface of a silicon chip. This r)articular form of construction is termed strip assembly and shows four standard cells, 401, 402, 403 and 404, having input data buses 405 and interconnecting buses 406-, 407 and 408 with the cell 404 driving output buses 409. Each standard cell consists of the data handling part of the cell D and a housekeeping loart including input circuits for control signals, buffers, decoders, etc. The housekeeping part of the cell is indicated by the block C. A system control unit 410-is constructed alongside the strip of four standard cells and is connected to each cell through a plurality of conductors represented at 411, 412, 413 and 414 respectively. Each cell also has scan-in and scan-out connections which are connected together from each cell to the adjacent ones. These connections are shown at references 415, 416, 417, 418 and 419.

Although the invention has been described with reference to a specific example of a digital signal processor, it will be understood that many modifications can be made to the example described without departing from the invention. For example, the number of parallel conductors interconnecting components of the processor can differ from those recited with appropriate changes to the complexity of the components. In addition, the multiplier may have input ports with numbers of conductors related by a factor other than 2 with corresponding changes to the numerical shifts which the data selectors can produce.

AP?6^j3)IX 16 Aff. ######f##ffff##########f##f#fff######ff##########################f##I##### # #fff## # DEFINITION FILE FOR THE ADPCM MACRO # # # Reduced G721 Grey Book" Microcode ######################################I#####f############################# ## ############ DEFINITION FILE FOR THE ADPCM MACRO system ADPCM 00000000000000 format GLOBAL width 120 4-TrtSE_ DESc021F Ow atsell sell apap -ro atsell-se12 1 Nr76 _ f-lli atsell_se13 atsell se14 atse12 sell atse12 se12 atse12 se13 atse12 se14 atse13 low atse13 mi d atse13 - hgh atsel3- tic atse14 sell atse14 se12 atse14 se13 atse14 se14 rite-accl rite acc2 lumux accl lumu2_acc2 Jp=inp =ninp am-sel air_rw am-bank - low am-bank - hgh m addr Dm-addr:)m- sel Ll:_rom 1X ram rite latl rite_lat2:)muc addr Lu clr Lu,._xmy Lu_,xpy Lu_pasx Lu_pasy Lu-xeoy Lu xory Lu_xany lu X1ty lu.-xgty Lu-xeqy ap-con np-ucon 131-PC >p_pc ix-selr ix-seln lx-selz f ixed fixed fixed fixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed variable variable f ixed f ixed f ixed f ixed f ixed variable f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed f ixed fixed f ixed f ixed -i,o pti -1 C-^;r F(& A4- 3 M11 SCLEC-r 00000000000000,c000000000000C 40000000000000,c0000000000000 80000000000000,c0000000000000 COOOOOOOOOOOOO, C0000000000000-j 00000000000000,30000000000000 10000000000000,30000000000000 20000000000000,30000000000000 30000000000000,30000000000000-.; 00000000000000,0c000000000000_ 04000000000000,0c000000000000 r, 08000000000000,0C0000000000000c000000000000,0C000000000000-; 00000000000000,03000000000000' 01000000000000,03000000000000 02000000000000,03000000000000 03000000000000,0300000000000000800000000000, 00800000000000-? 00040000000000,0004000000000000000000000000, 00600000000000! 00200000000000,00600000000000 00400000000000, 00600000000000 00600000000000,00600000000000-' 00100000000000, 00100000000000_ 00080000000000,00080000000000, 00020000000000, 00020000000000 00010000000000 0000fCO0000000 000000000000fe 00000000000400 00000000000000 00000200000000 00000100000000 00000080000000 0000007fCO0000 00000000040000 00000000080000 000000000CO000 00000000100000 00000000140000 00000000180000 000000001CO000 00000000000000 00000000080000, 000000001c0000 00000000080000, 000000001CO0001 -19 V 00000000080000, 000000001c0000i X 1 1 - -" 2_ ) P.-r A - 'S 'E L' C, 0 12 MUX Se-tECI 0 ,S v- t c--, p r_ M p A c---1 _ 1E C E C J, 00010000000000; (c - -12 ' 1,z - 64.. 0000fCO00000003 Rrm AD,:,L,000000000000fe3,crv\ (4 -1 000000000004001,00000200000000-,,00000200000000j 00000100000000.:

-1 r, X. - c 7,' 00000080000000,0000007fcOO0007 '000000001c0000,,000000001c0000 '000000001c0000 X Ex g) tz)( 0 Z Y v P -40 i -, c - z _pc 000000001c0000,,000000001c0000,000000001c0000,000000001c0000, 00000000lc0000 A ij Z c ' 1tC Z, -r 00000000020000,00000000020000:rumf> 00000000010000,00000000010000:TUC-.p 00000000008000,00000000008000 -S-rcc, 00000000004000,00000000004000 úe ( k 7 13 12 - -45 It h uj L, A 00000000000000,00000000003800 1 cojTf:xo_ LOG1c Mux TO 00000000000800,00000000003800t 00000000001000P00000000003800j Mux- lc mux-selp mux-selle ir-.x-sel_sgnmag i. c-iel-sidetone pcnLout edpcm out lat3 else goto jmpz jmpn impp jmple jmp-agmmag jmp-3idetone jmp- aub return jmp_rx while_not_sync set-Sync men_ramr mem-rama mem-ramw mem-rawa mem-romr me-m-roma mem-romb load latch2 load_12<<rambus load_12<<ram load_12<<rom f ixed f ixed f ixed f ixed f ixed f ixed fixed f ixed f ixed macro Macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro 17 r', 'f 00000000001800,00000000003800] 00000000002000,000000000038001 00000000002800,00000000003800 00000000003000,00000000003800 00000000003800,00000000003800J Tw' 00000000000200,00000000000200-;,1c--^,.c,,.7' -,) P-t"-0.

00000000000100,000000000001005 CL, 7 ---;,A!-4 RDP---PA, 00000000000001,00000000000001 JC 00000000000000,00000000000000 irnp_ucon romuc-addr mux-selz Imp_con romuc_addr mux-seln jmp_con romuc-addr mux-selp jmp_con romuc_addr mux-selle jmp_con romuc-addr mux - sel-agnmag imp_con romuc-addr mux_sel_sidetone imp_con romuc addr imp__ucon push_pc romuc-addr imp_ucon pop_pc mux-.gelr -imp__con romuc_addr mux - sync jmp_con romuc_addr datsell se14 ram_sel rar__rw ram-addr ram - sel ram rw datsel4_sel4 raiT_sel ran_addr ram - sel datsel4_se14 rom - sel rom addr datsel4_sell rom sel datse14 se12 rom_sel datsel4_se13 mux-ram write - lat2 macro mux_ram write - lat2 ram-se'L ram_addr ra.T,- rw macro mux-rom write-lat2 rom-sel rom-addr These are the more readable indexed memory mnemonics load - 12<<rom{al} macro mux - rom write - lat2 rom - sel datsel4_se13 load_12<<rom(a2) macro mux - rom write_lat2 rom_sel datsel4_se12 load_12<<ram(al) macro mux_rom write - lat2 mem. - rama load - ll_s4<<rom{al} macro datse12 - se14 write_latl rom - sel datse14 - se13 load_ll_s4<<rom{a2} macro datse12 - se14 write - latl rom - sel datsel4_se12 store_O>>ram{al) macro alu - clr datsell-se13 mem_rawa store_x>>ram{al} macro datsel3_1ow alu_pasx datsell-se13 mem-rawa These are no longer used after SFG5, but are kept for compiling older versions load_12<<rom{a} macro mux - rom write_lat2 rom_sel datsel4_se12 load_12<<rom{b} macro mux_rom write - lat2 rom - sel datsel4_sel3 lload_12<<ram{a} macro mux - rom write - lat2 mert__rama load - 11 s4<<rom(a} macro datsel2_se14 write - latl rom - sel datse14 se12 lload_ll_s4<<rom{b) macro datse12 - se14 write - latl rom - sel datsel4_se13 tstore_O>>ram(a) macro alu - clr datsell-se13 mem-rawa Istore_x>>ram(a} macro datsel3_low alu_pas:c datsell-se13 mem-rawa load latchl load 11 sl<<rambus load_ll_s2<<rambus Ioad_1l_s3<<rambus load 11 sl<<ram load_ll_s2<<ram load 11 s3<<ram 1 oad-ll-s4<<rom load_ll_sl<<pipe_reg load_ll_s2<<pipe_reg load_ll_s3<<pipe_reg load,. _pipe_reg<<ram load ace 1 macro datse12 sell write latl macro datse12 se12 write latl macro datse12 se13 write latl macro datse12 sell write latl ram sel ram addr ram rw macro datse12 - se12 write - latl ram - sel rain addr ram_rw macro datse12 - se13 write - latl raiR_sel ram - addr ram-rw macro datse12 - se14 write latl rom-sel rom-addr macro datse12 sell write latl macro datse12 se12 write latl macro datse12 se13 write latl macro lat3 rair_sel ram-addr ram-rw oae ->al macro dat3e13 - low alu,_pasx write - accl oad_j2x>>al macro datse13 mid alupasx write_accl oad - 128x>>al macro datsel3_hgh alu_pasx write accl -Rd_x-al>>al macro datse13-1ow alumux-accl write-accl alu-2any d_32x-al>>al macro datse13 mid alumux_accl write_accl alu-.=y oad - 128x-al>>al macro datse13 hgh alumux - accl write - accl alu - xmy oad - x+al>>al macro datse13 low alumux-accl write_accl alu_xpy oad_32x+al>>al macro datse13 mid alumux - accl write - accl alu xPY oad - 128x+al>>al macro datse13 hgh alumux-accl write accl alu - xpy oad x_eo_al>>al macro datsel37low alumux-accl write-accl alu xeoy oad 0>>al macro datse13 - tie write-accl ali_pasx oad 0-al>>al macro datse13 tie alumux_accl write - accl alu - xmy oajx-a2>>al macro datse13 - low alumux_acc2 write_accl alu_xmy oad_x+a2>>al macro datse13-1ow alumux-acc2 alu,_xpy write_accl oac_pcn,Linp>>al macro pcminp alu,._pasy write - accl oad x - and - al>>al macro datse13 - low alumux-accl alu-xany write_accl oacl:c-pcnLinp>>al macro datsel3_low pcminp alu,._xmy write-accl load acc2 oad_x>>a2 macro datse13 - low alu,_pasx write - acc2 oad - 32x>>a2 macro datse13 - mid alu_pasx write_acc2 oad_128x>>a2 macro datsel3_hgh alu,,_pasx write - acc2 oad_x-a2>>a2 macro datse13 - low alumux_acc2 write - acc2 alu - XMY oad - 32x-a2>>a2 macro datse13---midalumux_acc2 write_acc2 alu-xmy oad_128x-a2>>a2 macro datsel3_hgh alumux - acc2 write acc2 alu - xmy oad_x+a2>>a2 macro datse13 - low alumu2._acc2 write_acc2 alu-xPy oad 32x+a2>>a2 macro datae13 id alumux acc2 write acc2 alu xpy oad7128x+a2>>a2 macro datse13 - hgh alumux-acc2 write_acc2 a.lu-Xpy oad_128x-al>>a2 macro datsel3_hgh alumux - accl write - acc2 alu - XMY oad - 128x+al>>a2 macro datse13 - hgh alumuz _accl write_acc2 alu - xiDY oad_x_eo_a2>>a2 macro datse13 - low alumux - acc2 write - acc2 alu-xe-oy oad_O>>a2 macro datse13 - tie alu_pasx write_acc22 oad - 0-a2>>a2 macro datse13 - tie alumux - acc2 write - acc2 alixmy oad_x-al>>a2 macro datse13 - low alumuX-accl write_acc2 alu__cmy oad_x+al>>a2 macro datse13-1ow alumux_accl alu-xPy write_acc2 store to ram tore_O>>ram tore_x>>ram_1 tore_x>>ram_m tore_x>>ram---h tore 32x>>ram. 1 tore-32x>>rarr__m tore_32x>>ram-h tore 128x>>ram, 1 tore_128x> >ram m tore_128x>>ram-h tore al>>ram h tore_a2>>rarr_m tore a2>>ram h tore 0-al>>ram h tore_O-a2>>rai-h tore_x+al>>ram-1 tore x+al>>ram m tore- X+al>>ram-h tore_128x+al>>ram-m tore 128x+a2>>ram, m tore_128x+a2>>ram-h tore_adpcminp>>ram-m tore X and al>>ram h tore_128>__and_al>>ram-m tore_x_eo_adpcminp>>ram h load accl and acc2 Dad_x>>al_a2:)ad_128x+al>>al-a2 alu - clr datsell-se13 datsel3_low alu_pasx datse13 - low alu,._pasx datse13-1ow alu_pasx datse13 - mid alu__pasx datse13 Mild alu_pasx datse13 mid alu._pasx datsel3_hgh alu-pasx datse13 - hgh alu,.-pasx datsel3_hgh alu.._pasx alumux-accl alu,._pasy alumux-acc2 alu_pasy alumux - acc2 alu,_pasy datse13 tie datsel3_tie datse13 low macro macro datsell-sell memramw macro datsell se12 mem. ramw macro datsell-se13 mem-ramw macro datsell sell mem, ramw macro datsell-se12 mem_ramw macro datsell-se13 mem-ramw macro datsell sell mem ramw macro datsell-se12 merr_ramw macro datsell-se13 mem, ramw macro datsell-se13 mem-ramw macro datsell_sel"c mem-zamw macro datsell-se13 mem-ramw macro alumux - accl alu-=ny datsell-se13 mem-ramw macro alumux_acc2 alu_=y datsell-se13 mem-ramw macro - alumux-accl alu-xPy datsell-sell mem-ramw macro datse13 - low alumux - accl alu-xPy datsell-se12 mem-ramw macro datse13-1ow alumux_accl alu-xpy datsell-se13 mem-ramw macro datsel3_hgh alumux-accl alu-xPy datsell-se12 mem-ramw macro datse13 - hgh alumux - acc2 alu - xPY datsell-se12 mem-ramw macro datsel3_hgh alumux-acc2 alu-xpy datsell-se13 mem-ramw macro adpcminp alt_pasy datsell - se12 mem-ramw macro datsel3_low alumux_accl alu_xany datsell_se13 mem-ram,,, macro datse13-hgh alumux-accl alu-xany datsell_se12 mem. ramw macro datsel3_low adpcminp alu_xeoy datsell_se13 mem-ramw macro datsel3_low alu,_pasx write_accl write_acc2 macro datsel3_hgh alu_xpy alumux-acel write_accl write_acc2 19 store to ram and accl store_O>>al_ram at-nre_O-al>>al-ram-1 re_O-al>> al_ram-h macro datsel3_tie alu_clr write_accl datsell-se13 mem-ramw macro datsel3_tie alumux_accl alu_.-=y write_accl datsell-sell macro dateel3_tie alumux_accl alu_=ny write_accl datsell-se13 Store_x>>al_ram-m macro datsel3_low ali_pasx write_accl datsell-se12 mem- ramw store-x>>al-ram-h macro datse13-1ow alu_pasx write-accl datsell-se13 mem- ramw store-x>>a2_ram-h macro datse13-1ow alu_pasx write_acc2 datsell-se13 me-m- ramw store-128x>>al-ram-m macro datsel3_hgh ali_pasx write_accl datsell-se12 mem-ramw store-x+al>>al-ram-1 macro datse13-1ow alumux-accl alu-xpy write_accl datsell-sell store_x+al>>al_ram_m macro datse13-1ow alumux-accl. alu-xpy write_accl datsell-se12 store_x+al>>al-ram-h macro datse13-1ow alumux-accl alu__xpy write_:accl datsell-se13 store_x+al>>a2_ram-h macro datse13-1ow alumux-accl alu-xPy write-acc2 datsell-se13 store_x>>al_a2_ram_h macro datsel3_low alu_paax write_accl write_acc2 datzell_iel3 store_32x+al>>al-ram-m store_128x+al>>al-ram 1 store_128x+al>>al-ram m store_128x+al>>al-ram-h store_128x-al>>al_ram_l store_128x-al>>al-ram m store_128x-al>>al-ram-h store_128x_and_al>>al_ram-1 store_128x-and-al>>al-rain-m macro datse13---midalumux-accl macro datsel3_hgh alumux-accl macro datsel3_hgh alumux-accl macro datsel3_hgh alumux_accl macro datsel3_hgh alumux_accl macro datsel3_hgh alumux_accl nuacro datsel3_hgh alumux-accl macro datse13-hah alumux-accl macro datsel3_hgh alumux-accl alu_xpy write_accl datsell_sel.2 alu-xPy write_accl datsell_sell alu_xpy write_accl.datsell_sel2 alu_xpy write_accl datsell_se13 alu xmy write accl datsell sell alu__,mny write_accl datsell_se12 alu_.-cmy write_accl datsell_se13 alu-xany write_accl datsell-sell alu-xany write_accl datsellse12 if statements if-x-LT_O_then-jmp macro datse13-1ow alu_pasx jmpn if_x_GE_O_then_3mp macro datsel3_low alu_pasx jmpp if - 128x - LT - 0 then - jmp macro datsel3_hgh alt_pasx jmpn if-128X-GE_O_then-3mp macro datsel3_hgh alu_pasx jmpp if-128x+al-LT_O_then-jmp macro datsel3_hgh alu_xpy)mpn if - 128x+al - GE - 0 - then-jmp macro datsel3-hgh alu_xpy jmpp if-x+al-LT_O_then-jmp macro datse13 - low alumux - accl alu-xpy jmpn if-x+al-GE_O_then_jmp macro datse13-1ow alumux_accl alu-xpy jmpp if - x+a2 - LT - 0 - then-jmp macro datse13-1ow alumux-acc2 alu-xpy jmpn if-X+a2 GE - 0 - then - jmp macro datse13-1ow alumux-acc2 alu-xpy jmpp if-x-al_LT_O_then-jmp macro datse13 - low alumux - accl alu-xmy jmpn if x-al - GE - 0 - then-3mp macro datse13-1ow alumux_accl alu-xmy jmpp if--X-a2 - LT - 0 - then - jMP macro datse13-1ow alumux-acc2 alu-xmy jmpn if - x-a2 - GE - 0 - then_jmp macro datsel3_low alumux-acc2 alu-2cmy jmpp if - X - LT - al - then_3mp macro datse13-1ow alumux-accl alu-xmy jmpn if_x_GE_al_then_jmp macro datse13-1ow alumux-accl alu-.cmy jmpp if-x-LT_a2_then-3mp macro datse13-1ow alumux-acc2 alu-xmy jmpn if-x-GE_a2_then-jmp macro datse13-1ow alumux-acc2 alu-xmy jmpp if x=a2_then-jmp if - x=althen-jmp if_x_Ll_paminp-_then-jmp if-xpcminp_then-jmp if - X - eo al=0 then - JMP if-x+a2=0_then-jmp if-128xLT_al_then-jmp if - al-0-then-jmp if_x=O_then-jmp if - al - GT - 0 then_jmp if_a2_GT_O_tlTen_]mp if_al_LT_O_then_)mp if-a2_LT_O_then-3mp if al - LE - 0 - then-jmp if_al_GE_O_then_jmp if-a2_GE_O_then-3mp if-RXMUTE-then-jmp rtest flag only i f ir T..r n then imDt macro datse13-1ow alumux-acc2 alu-xeqy macro datsel3_low alumux-accl alu - xeqy macro datsel3_low pcminp alu,_=ny Dmpn macro datse13-1ow pcminp alu-.-cmy jmpz macro datsel3_low alumux-accl alu-xecy jmpz macro datsel3_low alumux-acc2 alu-xpy jmpz macro datse13-hgh alumux-accl alu-xmy jmpn macro alumux-accl alu__pasy impz macro alu_pasx jmpz macro macro macro macro macro macro macro macro jnip z iiilpz datsel3_tie alumux_accl alu-=ny jmpn datsel3_tie alumux_acc2 alu-xmy jmpn alumw. - accl ali_pasy jmpn alumux_acc2 alu-pasy jmpn alumux-accl alu_pasy jmple alumux-accl alu_pasy jmPP alumw.-acc2 alu_pasy jmpp jmp-rx macro imi:m f_x_ _0_then_jmpt f - 12ox - LT - 0 then - impt.f-128x - GE - 0 - then_jmpt.,r- x+ al_LT_O_then-jmpt.-_x+al_GE-0-then-jmpt.f - x+a2 - LT - 0 - then-jmpt:.fx+a2_GE_O_then-jmpt A-x-al-LT_O_then_jmpt A - x-al - GE - 0 - then-jmpt A - x-a2 - LT - 0 - then-jmpt -f-x-a2_G5_0_then-jmpt -f-X-LT - al - thenjmpt -f_x_GE_al---then-jmpt - f-x-LT---a2 "then-impt.f-x - GE - a2 then_jmpt.f:Ja2 - then-jmpt f-a2_1t_O_then-jmpt.f - x-al - then - impt -i x-LT_pcminp__jthen-jmpt._x-pcninp__:then - jmpt f -X - eo al-O ther_jmpt.:i 2jA+a2;;0-then-jmpt f_128x_LT_al_then_jmpt.f-al=O-then_jmpt f-x-0-then_jmpt f_al_GT_O_then_jmpt.f-a2_GT_O_then_jmpt.'f-al-LT_O_then_jmpt)Utput-pcrt-out<<x )Utput-pcm - 6ut<<al utput_pcm - out<<x-al Ldpert__out<<al Ldpcrr__out<<x end "Cro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro macro Impp jmpn impp jmpn jinpp jmpn impp jmpn impp jmpn impp jmpn impp jmpn impp jmpz jmpn jmpz jmpn jmpz jmpz jmpz jmpn jmpz jmpz jmpn jmpn jmpn datse13 low alu,._pasx pcir_out alumux-accl alu_pasy pci__out datsel3_low aluinux_accl alu_xmy p---,i_out alum=.-accl ali_pasy adpcrr__out adpcrr__out f 21 1t#f 4####I##. ######t####################################t###I############ 1# # 1# ######## SOURCE FILE FOR THE ADPCM SYSTEM ######## # # # 1# - MEGAMODULES GROUP. # !# f 14 - ASIC DESIGN CENTRE, BEDFORD (TIL). # I # # Ff Reduced G721 "Grey Book" Microcode # #f#########f################################f############################ ROM Declaration EQU dl 0 EQU d2 1 EQU d4 2 EQU d8 3 EQU d16 4 EQU d32 5 EQU d64 6 EQU d128 7 EQU d256 8 EQU d512 9 EQU d1024 10 EQU d2048 11 EQU d4096 12 EQU d8192 13 EQU d63488 14 EQU d65524 15 EQU dO 16 EQU d4a 17 EQU d18 18 EQU dOa 19 EQU d135 20 EQU d41 21 EQU dOb 22 EQU d213 23 EQU d64a 24 EQU d16a 25 EQU d273 26 EQU d112 27 EQU d16b 28 EQU d323 29 EQU d198 30 EQU d16c 31 EQU d373 32 EQU d355 33 EQU d48 34 EQU d425 35 EQU d1122 36 EQU d112a 37 EQU d65 38 EQU d68 39 EQU d71 40 EQU d74 41 EQU d78 42 EQU d81 43 EQU d85 44 EQU d89 45 EQU d92 46 EQU d97 47 EQU d101 48 EQU d105 49 EQU d110 50 EQU d115 51 EQU d120 52 EQU d125 53 22 EQU dg 54 EQU dll 55 EQU d13 56 EQU d502 57 EQU d605 58 EQU d3 59 EQU d656 60 EQU d336 61 EQU d5 62 EQU d6 63 EQU d7 64 EQU d124 65 EQU d544 66 EQU d5120 67 EQU d126 68 EQU d63 69 EQU d4095 70 EQU d127 71 EQU d12 72 EQU d12288 73 EQU d15 74 EQU d65535 75 EQU d434 76 EQU d65534 77 EQU d10 78 EQU d65504 79 EQU d14 80 EQU d38 81 EQU d53 82 EQU d132 83 EQU d53760 84 EQU d21845 85 EQU d79 86 EQU d95 87 EQU d31 88 EQU d11776 89 EQU d1536 90 EQU d3968 91 EQU d4064 92 EQU d3840 93 EQU d204 94 EQU d556 95 END ROM Declaration RAM Declaration SDQ6 SDQ5 SDQ4 SDQ3 WQ2 WQ1 YU YLH PKO PK1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU YLL DQ DQ1 DQ2 DQ3 DQ4 DQ5 SR1 SR APP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU Z EQU R32 EQU R1024 47 END RAM Declaration B1 B2 B3 B4 B5 B 6 A2 Al DMS DMI, TDPP TR YN YX TEMP 1 TEMP 4 SE SEZ A.L 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 42 42 43 44 r 23 y YOVER4 SIGNC-Im O-SDQ 0-PK2 1 TEMP2 46 START CODING PROCEDURE INITIALISE RAM VARIABLES FOR CODE( PCM) PROCEDURE SET MEMORY BANK LOCATION - LOW (0 - 29 LOW xref org 0 MEM-LOW: ram-bank_low load_12<<rom(d31) jmp_sub(SETUP); MEM-HGH: alu-clr pcrr__out set_sync ram-barik_hah load_12<<rom(d63) jmp_sub(SETUP); WAIT: while_not_sync(WAIT); BEGIN MAIN PROGRAM MEM-SET: ram-bank_low load,_pipe_reg<<ram(DQS) jmp-sub(PREDICT); GET REAL PCMIN SAMPLE PCM-IN: load_12<<rom(d4096) load_ll_sl<<ram(I); CHECK NEG STATUS FLAG FOR IF CONDITION PRE_IF:10adjl_s4<<rom(d65534) load_12<<ram(SE) load-x-pcminp>>al if_x_L7_pcminp_then_jmpt (ER-SIG); PRE-ESL: else load_pcminp>>al; .CALCULATE QUANTISED ERROR SIGNAL ERJIG:1oad_1l_s4<<rom(d1) store_x+al>> al_ram_l(SIGN) if_x+al_LT_O_then_jmpt(CK_IF); load_12<<rom(dl) store_al>> ram-h(O-IM) goto(LMO); CHECK FOR CONDITION - N= Z= ZERO CK_IF: load_12<<rom(dl) store_O-al>>al-ram h(O-IM); LMO:

load x+al>>al load 12<<rom(d128); load_12<<rom(d8) if_xal_LT_O_then_jmp(A2048); load_12<<rom(d2) if-x-al - LT - 0 - then jmp(A32); load_12<<rom(dl) if_x-al GE 0 then jmp(ED1); A:

0:

k,n:

0: k64:

0:

2048:

k9: k1024:

L11: L4096:

k13: W2:

24 load 12<<rom(d4); load - 12<<rom(d2) if_x-al_GE - 0 - then_jmp(EDI); load - 12<<rom(d3) goto(ED1); load_12<<rom(d32); load_12<<rom(d16) lf_x-al_LT_O__then_jmp(A64); load - 12<<rom(d4) if x-al-GE-0-then_jmp(ED1); load - 12<<rom(d5) goto(ED1); load_12<<rom(d64); load - 12<<rom(d6) if-x-al-GE-0-then_jmp(ED1); load_12<<rom(d7), store-x>>al - ram h(TFAQ1) load_12<<rom(d8); load - x-al>>a2 load 12<<ram(O-IM); load_ll_s4<<rom{a2}, store_x>>ram h(O_IM) load_12<<rambus load_ll_s4<<rom(dl) goto(ED3); load 12<<rom(d2048); load12<<r=(d512) if_x-al_LT_O_then_jmp(A4096); load_12<<rom(d256) if_x-al_LT_0 then_jmp(A1024); load - 12<<rom(d8) if - X-al - GE - 0 - then_jmp(ED2); load - 12<<rom(dg) goto(ED2); load_12<<rom(d1024); load_12<<rom(d10) if_x-al_GE_O_then_jmp(ED2); load - 12<<rom(d11) goto(ED2); load 12<<rom(d4096); load_12<<rom(d12) if_x-al_GE_O_then_jmp(ED2); load_12<<rom(d13); store_x>>al - ram-h(TEMP1) load_12<<rom(d13); load_x-al>>a2 load_12<<ram(O-IM); load_ll_s4<<rom{a2}; store_128x>>ram_m(O_IM) load_12<<rambus load_ll_s4<<rom(dl); CONTINUE MAIN PROGRAM M3; [E3: [El:

1ES: LE2:

LE6: LE4:

LE7:

load - 12<<ram(TE1.1P1) loald_x>>al; load_12<<ram(YOVER4) load_ll_s4<<rom(d65535) load_128x+al>>al; load_12<<rom(d502) load_ll_s3<<ram(Z) load_x+al>>al; load_12<<rom(d605) if_x+al_LT_O_then-jmp(ME1); load_12<<rom(d656) if_x+al_LT_O_then_jmp(ME2); load_12<<rom(d7) load_ll_sl<<ram(l) if_x+al - GE - 0 - then_jmp(ADPCM); load - 12<<rom(d6) load_ll_sl<<ram(I) goto(AD2CM); load 12<<rom(d336); 1 load,._12<<rom(d434) if-x+al-LT_O_then_jmp(ME4); load_12<<rom(d3) load_ll_sl<<ram(l) if_x+al_GE_O_then_jrip(ADPCM); load_12<<rom(d2) load_ll_sl<<ram(I) goto(ADPCM); load_12<<rom(d556); load_12<<rom(d5) load-ll-sl<<ram(I) if-x+al - GE - 0 - thenjmp(ADPCM); load - 12<<rom(d4) load - 11 sl<<ram(l) goto(ADPCM); load,._12<<rom(d132); load - 12<<rom(d1) load - 11 sl<<ram(I) if_x+al_GE_O_then_jmp(ADPCM); load_ll_s4<<rom(dO); DPCM:1oad_x>>al_a2 load_12<<ram(SIGN) load_ll_s4<<rom(dl); IN.B. a2 used at QNT1 ADPCM DATA OUT - 4 BIT ENCODED DATA INVERSE QUANTISE TO PRODUCE EFFECTIVE INPUT/ DECODER OUTPUT UB_QAN:load_1l_s4<<rom(d65535) load_12<<ram(I) load_x_eo_al>>al if-x-eo-al=O-then_jmpt(SGN_CHN); adpam out<<al load_ll_s4<<rom(dl) goto(QNT1); GN - CHN: store - x>>al - ram h(SIGN) load - 11 - s4<<rom(dl) adpcri__out<<x; NT1: store_a2>>ram_i(O_IM) load_12<<rom(d14) jmp-sub(quantize); UPDATE PREDICTOR - ADAPTIVE PREDICTOR ATA-RX: load_ll_s4<<rom(dl) load_12<<ram(DQ) jmp-sub(update); ENCODE STAGE COMPLETE j 1 1##### START DECODING PROCEDURE 1##### p START PROCEDURE PREDICT SUB_PRD: set_sync ram-bank_hgh load_pipe_reg<<ram(DQ5) jmp_sub(predict); GET QUANTISED ERROR SIGNAL - GET ADPCM INPUT SIGNAL load_ll_s4<<rom(dl) load_12<<rambus store - adpcminp>>ram-m(SIGN) if_RX_MUTE_then_jmp(memhgh); else store_x_eo_adpcminp>>ram-h(O-IM); INVERSE QUANTISE TO PRODUCE DECODER OUTPUT SUB_QNT: load_ll_sl<<ram(l) load_12<<rom(d14) jmp_sub(QUANTIZE); OUTPUT DEQUANTISED PREDICTOR PLUS ERROR CHECK FOR IF CONDITION - ZERO QNT_IFI: load_ll_sl<<ram(I) load_12<<rom(d4095) if_al_LT_O_then_jmp(QNT_TH); QNT-ES1: load_x-al>>a2 if_x-al_GE_O_then_jmpt(PCM_OUT1); QNT_THN: store_x>>al_ram-h(SR) goto(PCM-OUT1); QNT_TH: load_x+al>>a2 if_x+al_LT_O_then_jmpt(QNT - TH1); load_ll_sl<<ram(I) load_12<<rom(d4096) goto(pcn_out3); QNT_TH1: load_ll_sl<<ram(I) load_12<<rom(d4096) load_x>>al; store_O-al>>al_ram_h(SR) goto(PCM-OUT3); GENERATE PCM OUTPUT SIGNAL 'UPDATE PREDICTOR PCM-OUT1: output_pcm,_out<<al load_ll_s4<<rom(dl) load_12<<ram(DQ) jmp_sub(UPDATE); goto(WAIT); PCM. OUT3: output_pcrr__out<<x-a1 1oad_l1_s4<<rom(d1) load_12<<ram(DQ) jmp_sub(UPDATE); SYNC - RE: goto(WAIT); END OF MAIN PROGRAM ###I############# PROCEDURE INITIALISATION SETUP: load_ll_s4<<rom(dl); load_x>>al load_12<<rorn(dll) LP:

load 11 s4<<rom(d2); load_x>>a2 load_12<<rom(d65535); load_ll_s4<<rom(dl); store 0>>ramal}; load_x+al>>al; load_x+a2>>a2; if-a2_GT_O_then-jmp(LP); store_x>>ram_h(Z) load_12<<rom(dl); store_x>>al_ram_h(l) load_12<<rom(d32); store x>>ram h(R32) load 12<<rom(d1024); store_x>>al_ram-h(SDQ6); store_al>>ram_h(SDQ5); store al>>ram h(SDQ4); store_al>>ram_h(SDQ3); store al>>ram h(SDQ2); store_al>>ram-h(R1024); store - al>>ram - h(SDQ1) load_12<<rom(d544); store__,x>>al_ram - h(YU); store al>>ram h(YLH) load 12<<rom(d512); store_x>>al_r,am_h(PKO); store_al>>ram_h(PKI) return; END OF PROCEDURE INITIALISATION PROCEDURE PREDICT - ENCODE/ DECODE 'procedure 16 x 15 multiplication 26 load_12<<ram(B6) load_ll_s2<<pipe_reg; procedure 16 x 15a multiplication Y- -PRED: load,_púpie_reg<<ram(D04) load_ll_sl<<pipe_reg load_128x>>al; load_12<<ram(B5) load_ll_s2<<pipe_reg load_x+al>>al; procedure 16 x 15a multiplication load_pipie_reg<<ram(DQ3) load_ll_sl<<pipe_reg load_128x+al>>al; load_12<<ram(B4) load - ll_s2<<pipe_reg load_x+al>>al; procedure 16 x 15a multiplication load_pipe_reg<<ram(DQ2) load_ll_sl<<pipe_reg load_128x+al>>al; load_12<<ram(B3) load_ll_s2<<pipe_reg load_x+al>>al; procedure 16 x 15a multiplication load_pipe_reg<<ram(DQ1) load_llsl<<pipi_reg load - 128x+al>>al; load_12<<ram(B2) load_ll_e2<<pipe_reg load x+al>>al; procedure 16 x 15a multiplication load_pipe_reg<<ram(DQ) load-11 - sl<<pipe_reg load_128x+al>>al; load 12<<ram(B1) load - ll-s2<<pipe - reg load x+al>>al; loacC:pipe_reg<<ram(Si1) load_ll_sl<<pipe_reg load_128x+al>>al; store_x+al>>al_ram_l(SEZ SIGNAL ESTIMATE procedure 16 x 15a multiplication load_12<<ram(A2) load - 11 - s2<<pipe_reg; procedure 16 x 15a multiplication load,._pipe_reg<<ram(SR) load - 11 - sl<<pipe_reg load_128x+al>>al; load - 12<<ram(A1) load_ll_s2<<pipe_reg load_x+al>>al; load_ll_sl<<pipe_reg load_128x+al>>al; store_x+al>>al_ram-l(SE); load ll s4<<rom(di) load_12<<ram(DQ4); store_x>>ram_h(DQ5), load 12<<ram(DQ3); store_x>>ram_h(DQ4); load 12<<ram(DQ2); store-x>>ram-h(DQ3); load 12<<ram(DQ1); store_x>>ram h(DQ2); load 12<<ram(DQ); store_x>>ram_h(DQ1); load 12<<ram(SR); store_x>>ram_h(SR1); LIMIT SPEED CONTROL, FORM LINEAR COMBINATION OF FAST AND SLOW SCALE FACTORS BELOW ROUTINE EFFECTIVELY DOES IF APP<<256 IF/ THEN CONDITION - CHECK FOR ZERO FLAG R-IF: load_1l_s3<<ram(APP) load_12<<rom(dl) load_O>>a2; load_ll_s3<<ram(Z) load_12<<rom(d64) if_x--a2_then_jmp(AN_TH); N-ES:

N TH:

load-12<<ram(YU) load_ll-s4<<rom(dl); store - x>>ram - h(Y) load_12<<rambus load_ll_s4<<rom(d8) goto(PR---ES); load_128x>>al load_12<<ram(APP) load_ll_s4<<rom(d16); store 128x and al>>ram---m(AL) load_ll_sl<<rambus; load '12<<ram(YLH); load 32x>>al load 12<<ram(YU); load_32x-al>>al load_12<<ram(YLH) load_ll_s4<<rom(d32); 27 itor!e-128x+al>>ram-m(Y) load_12<<rambue load_ll_e4<<rom(d8); PR-r.b. store_128x>>al_ram_m(YOVúR4) return; tEND OF SUB-ROUTINE PREDICT - ENCODE/ DECODE 11 iCEDURE QUANTIZER - ENCODE/ DECODE QUANTIZE: load 11 s4<<rom(d3) load 12<<ram(O IM) load x>>al; store_iC+al>>a2_ram_h(TEMP4) load_ll_s4<<rom(d32); load 12<<rom(a2); load - 12<<ram(YOVER4) load_x>>al; store - x+al>>al_ram - m(TEMPl) load - 12<<rambus load_ll_s4<<rom(dl); load_x>>a2 load_12<<rom(d4O95) if_x_LT_O_then_jmpt(QN_IFl); load x and al>>al load l2<<rom(d4096); store - x+al>>ram_h(TEMPl) load_12<<rom(a2) load_ll_s2<<rambus; load_ll_al<<ram(TEKPl) load_128x>>al; store_x+al>>al_ram m(DQ) load_ll_s4<<rom(dl) goto(QN_IF2); store_O>>al_ram(DQ); CHECK IF CONDITION - NEGATIVE ON-IF2: load -12<<ram(SIGN); load 12<<rom(d1024) if_x_LT_O_then_jmp(QN_TH1); QN-ES: store-x>>ram h(O-SDQ) gato(ADP-Cl); QN_TH1: load - 11 - s4<<rom(d65535) load - 12<<ram(DQ); store_x>>ram_h(DQ) load_12<<rom(d1024) goto(QN-ES); QUANTIZER SCALE FACTOR ADAPTATION ADP-Cl., load - 11 - s4<<rom(dl) load_12<<ram(TEMP4); load_12<<rom(d1) load_x>>a2; load 11 s4<<rom(d124) load 12<<ram(Y) load x+a2>>a2; load 11 sl<<ram(R32) load 12<<rom{a2} load 32x>>al; ADA_IF: load_12<<rom(d544) store_128x+al>>al_ram-m7(yu); load 11 s4<<rom(d65504); CHECK FOR IF CONDITION - ZERO load_128x+al>>a2 load_ll_s4<<ram(d32) if_128x_LT_al_then_jmpt(AEiA_THN); CHECK FOR IF CONDITION - NEGATIVE ADA-ES: load_12<<rom(d5120); load - 128x-al>>a2 if 128x - LT - al - then_jmpt(ADA_THN); load - 11 - s4<<rom(d126) load 12<<ram(YLH) goto(ADA_CN1); ADA_THN: store_128x>>ram_m(YU) goto(ADA_W); NOTE THE ABOVE COMPARE CONDITION HAS BEEN CHANGED TO ' > ' FROM ' '<' IN THE PASCAL PROGRAM. THIS CHANGE WAS DUE TO 'IF/THEN' CONDITION ADA - CN:

ADA_W1:

load 11 s4<<rom(d126) load 12<<ram(YLH); load_ll_s4<<rom(d63) load_12<<ram(YLL) load_32x>>al; load - 11 - s4<<rom(d64) load_12<<ram(YU) load_x+al>>al; load - 11 - s4<<rom(dl) store_x+al>>al-ram-m(YLH); load 12<<rom(d4095); load - 11 - s4<<rom(d64) load_12<<rambus store_x_and_al>> ram-h(TEMP1); store_x>>al_ram-m(YLL); ADAPTATION SPEED CONTROL AbAPT_ST: load_ll_s4<<rom(dl) load_12<<ram(TF.MP4); load 12<<rom(d2) load x>>al; load - x+al>>al load - 11 - sl<<ram(DMS) load_12<<rom(d3968); load x>>a2 load 11 s2<<ram(DE1S); loaJl28x+a2>>a' load - 11 - sl<<ram(R32) 1.oad_12<<rom{al); store - 128x+a2>>ram_m(DMS) load_12<<rom(d4064); load 11 sl<<ram(DML); load - x>>a2 load_ll_s2<<ram(DEL); load 128x+a2>>a2 load 11 sl<<ram(R32) load 12<<romJa1}; store_128x+a2>>ram_m(DEL)load_12<<rom(d3840); 28 load 11 sl<<ram(APP); load7x>_>a2 load 11 32<<ram(APP); store-128x+a2>> ram_m(APP); 5-''ED CONTROL PARAMETER load 11 s4<<rom(d8) load i2<<ram(DML); load x>>al load 11 s4<<rom(d32) load 12<<ram(DMS); load_ll_s4<<rom(d17 load.12<<ram(DML) load_x-al>>a11 if-x-GE-al- then_jmpt(ABS1); BS: BSI:

R-I:

R_2:

load 0-al>>al; load - x-al>>al load_ll_s4<<rom(dl) load_12<<ram(APP); if al LE 0 thenjmp(CNTL-ES); load_12<-<rom(d1536); load - 12<<ram(Y) load-x> >al; load_12<<ram(APP) if_x_LT_al_then_jmp(CNTL-ES); load_12<<rom(d53760); load 12<<ram(A2) load x>>al; load_12<<ram(APP) if;jal_GE_O_then_jmp(SCP_END); NTL-ES: load_12<<rom(d32) load_x>>al; store x+al>>ram h(APP); CP-END: load_ll_s4<<rom(d2) load_12<<ram(SE); load - 11 - s4<<rom(dl) load - 12<<ram(DQ) load_x>>al; store_x+al>>al-ram-h(SR) return; END OF ROUTINE QUANTIZER - ENCODE PROCEDURE UPDATE - ENCODE PDATE: load_ll_s4<<rom(dl) load_12<<ram(C_SDQ) if__,x=O_then_jmp(CHE_TH); store_x>>ram_h(TFI4P1) goto(UPDAT); HE TH: store_O>>ram(TEMP1); PDAT: load_ll_s4<<rom(d16) load_12<<ram(B6); -HANGED UPDATE MACRO:- BN = TE1.1P1(34), BEFORE IT WAS 0 WQ(42) load - 11 - s4<<rom(d32) load - x>>al load,_pipe_reg<<ram(TEbIP1); load - 12<<ram(SDQ6) load_128x-al>>al load_ll_s3<<pipe_reg; store_128x+al>>al_ram m(B6); P-DAT2:

2_DAT3:

?-DAT4:

? DATS:

> DAT 6:

load 11 s4<<rom(d16) load_12<<ram(B5); load 11 s4<<rom(d32) load x>>al; load - 12<<ram(SDQ5) load_128x-al>>al load_ll_s4<<rom(dl); store X>>ram h(SDQ6) load 11 s3<<pipe_reg load 12<<rambus; store_128x+al>>al_ram m(B5); load_ll_s4<<rom(d16) load_12<<ram(B4); load - 11 - s4<<rom(d32) load_x>> al; load - 12<<ram(SDQ4) load_128x-al>>al load_ll_s4<<rom(dl); store - x>> ram h(SDQ5) load - 11 - s3<<pipe_reg load_12<<rambus; store_128x+al>> al_ram m(B4); load_ll_s4<<rom(d16) load_12<<ram(B3); load - 11 s4<<rom(d32) load_x>> al; load - 12<<ram(SDQ3) load_128x-al>>al load_ll_s4<<rom(dl); store - x>> ram h(SDQ4) load - 11 - s3<<pipe_reg load_12<<rambus; store_128x+al>>al- ram m(B3); load_ll_s4<<rom(d16) load_12<<ram(B2); load 11 s4<<rom(d32) load x>>al; load - 12<<ram(SDQ2) load_128x-al>>al load_ll_s4<<rom(dl); store - x>>ram - h(SDQ3) load-11 s3<<pipe_reg load_12<<ranibus; store_128x+al>>al_ram m(B2); load_ll_s4<<rom(d16) load_12<<ram(B1); 29 load - 11 - a4<<rom(d32) load-x>>al; load - 12<<ram(SDQ1) load_128x-al>> al load_ll_e4<<rom(dl); store - x>>rwn - h(SDQ2) load 11 s3<<pipe_reg load_12<<rambus; store_128x+al>>al_ram_rn(-1);- UP-CON1: load_ll_s4<<rom(dl) load_12<<ram(O-SDQ); store x>>al ram h(SDQ1); UP-CON2: load_12<<ram(PK1); store X>>al ram h(O SDQ); UP-CON3: load_12<<ram(PKO); store_x>>al_ram_h(PKI) load_ll_z4<<rom(dl); load 11 s4<<rom(d2) load 12<<ram(SEZ); UP-1F1: load_ll_a4<<rom(dl) load_12<<ram(DQ) load_x>>al; fCRECK FOR IF CONDITION - NEGATIVE OLD CODE DELETED - 'new code ADDED load_12<<rorn(d512) load_ll_s3<<ram(Z) load- x+al>>al if-x+al-LT_O_then_jmpt(UP_TH); UP-TH:

load 11 e4<<rom(dl); store_x>>a2_ram_h(PKO) load_12<<rambusload_ll_s4<<rom(dl); store - al>>ram -- h(TEMP2) load - 12<<rambus if al=0-then_jmpt(UP_CN) store_a2>>ram,._h(TFI4P2) load_12<<rambus, END OF 'new code - CONTINUATION OF OLD CODE PLUS MINOR ADDITION UP-CN: load_ll_s3<<ram(PK1); UP-W1: store_x>>al_a2_ram_h(TEMP1) if_x=O_then_jmpt(UD_TH); CHECK FOR IF CONDITION NEGATIVE UD_IF: load_ll_s4<<rom(dl) load_12<<ram(A1) if_al_GE_O_then_jmp(UD_TH); load 11 s4<<rom(d65535); UD_TH: load_x>>a2 load_ll_sl<<ram(I) load_12<<rom(d8192) if-x- GE_O_then_jmpt(UT_ES); CHECK FOR IF CONDITION - NEGATIVE UT_TH. load_ll_s4<<rom(d65535) if_x+a2_LT_O_then_jmp(UA_TH); load_ll_s4<<rom(d16) load_12<<ram(A1) goto(UP-CAN); UT_ES: load_ll_s4<<rom(dl) if_x-a2_GE_O_then_jmp(UP_CON); UA TH: load x>>a2; UP-CON: load_ll_s4<<rom(d16) load_12<<ram(A1); UP-CAN: load_ll_s4<<rom(d32) load_12<<ram(A1) load_x>>al; load - 11 - s4<<rom(d6) load_12<<ram(TEMP1) load_128x-al>>al; store - 128x+al>>al-ram-m(A1); load - 11 - s4<<rom(d4) load 12<<rambus store-a2>>ram-h(TEMP4); load 11 s4<<rom(d127) load 12<<ram(A2) load_32x>>al; load - 11 - s2<<ram(O-PK2) load_32x-al>>al; load 12<<ram(TEMP2); load_128x+al>>al; LIMIT A2 CHECK FOR IF CONDITION NEGATIVE ST-IF:

ST-ES:

LI-A2:

ST_TH:

load_128x+al>>al_a2 load_ll_sl<<ram(R32) load_12<<rom(d12288) if-128x-LT_O_then_jmpt(ST_TH); f ', N.B. a2 used to load RAM and 12 later load_12<<rom(d3) if_128x_LT_al_then_jmp(LI_A2); load - 11 - s4<<rom(d1) store_a2>>xam_m(A2) load_12<<rambus goto(SP-CON1); store_128x>>ram_h(A2) load_ll_s4<<rom(dl) load_12<<rambus goto(SP-CON1); load_12<<rom(d3) if_128x+al_LT_O_then_jmp(ST_TRA): load_ll_s4<<rom(dl) store_a2>>rain_m(A2) load_12<<-rarnbus goto(SP - CON1); 3T - load_128x>>al; store-0-al>>ram h(A2) load_ll_s4<<rom(dl) load_12<<rambus; load_12<<rom(d120) load_x>>al; load_ll_e4<<rom(dl) load_12<<rain(A1) load_128x-al>>al; CHECK FOR IF CONDITION - NEGATIVE "R IF:

> - load_ll_14<<rom(d65535) if_x_LT_O_then-jmp(SR-TH); 3R-ES.

3V ES:

3R - TH:

1 >U-CNT:

rRAN:

BAN TH:

RAN 1:

RAN-ELS:

0-N:

O-Nl:

RN-TH2:

NT_END:

if-x+al-GE-0-then_jmp(TRAN); store_al>>ram_h(A1) goto(TRAN); if-x+al-GE-0-then_jmp(TRAN); store-0-al>>ram h(A1); load 12<<ram(A2) load 11 s4<<rom(dl); loajx>>al load 12<<rom(-d11776); load_ll_s4<<rom(d8) load_12<<ram(YLH) load_x+al>>al if-x+al-LT_O_then_jmpt(TRAN_TH); else return; store_x>>ram_m(YN); load - 128x>>al load 11 sl<<ram(l) load 12<<rom(d3840); load - 11 - s4<<rom(dl) store_128x_and_al>>al-ram-l(YX); load 12<<ram(YN); load 12<<rom(d8) load x>>al; load -- 12<<rom(d38) if x-al - LT - 0 - then - jmp(TRAN-1); load x>>al load_12<<ram(YX); load x+ al>>al; load 12<<rom{al}; store_x>>ram_h(TEMP1); load 12<<ram(YN); load_x> >a2 load_12<<ram(DQ) load_ll_s4<<rom(d8) goto(TRAN_ELS); load_ll_s4<<rom(d31) load_12<<ram(R1024); load_x>>a2 load---12<<ram(DQ) load_ll_s4<<rom(d8); load_x>>al load_ll_sl<<ram(TEMPI) load_12<<rom{a2j; if al - LE 0 - then jmp(D0-N1); lod_O-al>>al; load-x+al>>al; load x+al>>al; load - x+al>>al if x_LT_O_then_jmpt(TRN_TH2),, else return; store-O>>ram(A1); store 0>> ram(A2); storiE_0>>ram (B1); store 0>>ram(B2); store 0>>ram(B3); store 0>> ram(B4); store 0>>ram(B5) load 11 s4<<rom(dl); store_O>>ram(B6) load_12<<rom(d256); store_x>>ram_h(APP) return; END OF ROUTINE ADAPT - PREDICTOR UPDATE THE REMAINING CODE IS USED FOR DEVICE TEST PURPOSES k :ODEC INTERFACE TEST ROUTINE CC A:

CODC2:

CODC3:

CODC4:

CODC5: ERROR:

r 31 load 12<<rom(d1) load 11 el<<ram(I); store - x>>a2 - ram-h(YN) load_ll_sl<<rambus pcr_out; load 11 - s4<<rom(d63) if_x"cminp_then_jmp(CODC1); goti(ERROR); load - 11 - 94<<rom(d8192) load_x>>al; store_x+al>>ram_h(YN) load_ll_sl<<rambus pcrr_out; load 12<<rom{a2) if-x-pcminp__then_jmp(CODC2); goto(ERROR); load 11 s4<<rom(d32); load - 11 s4<<rom(dl) load_x>>al; store_x+al>>ram_h(YN) load_12<<rambus p=-out; load - 11 - s4<<rom(d63) if-xpcminp_then_jmp(CODC3); goto(ERROR); load 12<<romfa21; store - x>>ram h(YN) load_ll_s4<<rom(dl) pcm-out; load_ll_s4<<-rom(dl) load_12<<ram(I) if_x-pcminp__hen_jmp(CODC4); goto(ERROR); load - 11 - a4<<rom(d7) load_x+ a2>>a2; if - x-a2_then_jmp(CODC5); load_12<<rom(a2) goto(CODC2); outputpam-out<<x; goto (MEM-LOW); PARAMETER ROM TEST ROUTINE 'ADD ROM CONTENTS J1 ROM-TS:

DAT-JP:

END:

r load 11 s4<<rom(dl); load_12<<rom(d95) load_O>>a2; load_x>>al; load 12<<rom{a1}; load_x+a2>>a2 load_12<<rom(d65535); load_x+al>>al if_x+ al_LT_O_then_jmpt(MEM_LOW); got o (DAT-JP); PARAMETER RAM TEST ROUTINE f WRITE ZEROES p RAM-TS:

CON1:

J1 p READ ZEROES NEXT-1:

CON2:

PROC-1:

01 load_ll_s4<<rom(dl); load_12<<rom(d79); load_x>>al load_12<<rom(d65535); store 0>>ram{al}; load_x+al>>al if_x+al_GE_O_then_jmpt(CON1); AND WRITE ONES load_12<<rom(d79); load x>>al; load_12<<ram{al} load_0>>a2; if-x=a2_then_jmp(PRC)C_1) load_12<<rom(d65535) goto (BAD-1); store_x>>ram{al}; Change in Sfg1 load_x+al>>al if_x+al_GE_O_then_jmpt(CON2); READ ONES TWICE AND WRITE ZEROES NEXT_2:

CON3:

PROC R..

READA: CONR:

: 11 = 1, 12 = -1 load_12<<rom(d79); load x>>al load 12<<rom(d65535); load__x>>a2 load_12<<ramlal}; r Change in Sf91: 11 = 1, 12 = -1 ifx=a2_then_jmp(PROC_R) load_12<<rom(d65535); goto(BAD - 1); load_x+al>>al load_12<<rom(d79) f_x+al_LT_O_then_jrnpt (READA) goto(CON3) load 12<<rom(d65535); load x>>al load 12<<rom(d65535); load - x>>a2 load_12<<ram{al); f Change in Sfg1: 14 = 1, 12 = -1 if_x=a2_then_jmp(PROC_2); ROC:

goto (BAD-1); 32 store-O>>ram(al}; load_x+al>>al if_x+al_LT_O_then_jmpt(CONR); READ ZEROES WRITE ONE-ZEROES EXT_3:

ON4:

ROC-3:

load_12<<rom(d79); load x>>al; load - 12<<ram{all load_O>>a2; load 12<<rom(d21845) if-x-a2_then jmp(PROC-3); goti(BAp_l); store-x>>ram(all; load_12<<rom(d65535); load_x+al>>al if_x+al_GE_O_thenjmpt(CON4); READ ONE-ZEROES - END OF TEST EXT_4:

ON5:

ROC 4:

load_12<<rom (d7 9); load - x>>al load_12<<rom(d21845); load_x>>a2; load 12<<ram{a1}; load - 12<<rom(d65535) if-x--a2_then jmp(PROC-4); goto (BAD1); load_x+al>>al if_x+al-GE_O-then-jmpt(MEM-LOW); !!!! Unnecessary removed GOOD-1:

WAIT LOOP FOR FAILED TEST kD-1:

DOP:

kD:

goto (MEM-LOW); load_ll_s4<<rom(dl); load 12<<rom(d204); load x>>a2 load 12<<rom(d65535); load - x+a2>>a2 lf_x+a2_LT_O_then_jmpt(MEM LOW); goto(LOOP); goto(MF,M- LOW); r

Claims

CLAIM:

1. A digital signal processor incorporated in an integrated circuit and including first and second sources of binary numbers, a parallel binary multiplier having a first input port with a first plurality of conductors for receiving in parallel a first plurality of bits defining a. first number, a second input port with a second plurality of conductors for receiving in parallel a second plurality of bits defining a second number, and an output port with a third plurality of conductors for transmitting in parallel a third plurality of bits representing the product of the first and second numbers, the first plurality being substantially larger than the second plurality, a first data selector connected from the first and second sources to the first input port of the multiplier, a second data selector connected from the first and second sources to the second input port of the multiplier, and means for controlling the operation of the first and second data selectors according to the numbers of bits in the numbers from the first and second sources.

2. A processor according to claim 1, wherein the first data selector is arranged to be able to select two or more different 'oluralities of bits from the first source or the second source.

3. A processor according to claim 1 or 2, wherein the second data selector is arranged to be able to select two or more different Dluralities of bits from the first source or the second source.

4. A r)rocessor according to any one of claims 1 to 3, wherein at least one of the first and second data selectors includes latch means for storing input data for later output.

34

5. A processor according to any one of claims 1 to 4, further including a third data selector connected from the output pott of the multiplier to a data bus, the third data selector being arranged to be able to shift the bits representing the product output by the multiplier relative to the conductors of the data bus.

6. A processor according to any one of the preceding claims, wherein the first and second sources are a randomaccess memory and a read-only memory respectively.

7. A -processor according to claim 6, further including a register connected between the first source and the second data selector, the register having a number of stages corresponding to number of conductors in the second plurality of conductors.

8. -A processor according to claim 7, wherein the register has more than one mode of operation, and in one mode of oDeration the inputs of the register are applied directly to the outputs of the register and the stages of the register do not store the data conveyed from the inputs tothe outputs.

9. A processor according to any one of the preceding claims further including a parallel adding/subtractincr means having a first input port connected to the output port of the multiplier.

10. A processor according to claim 9, including a further data selector connected to apnly data to a second input port of the adding/subtracting means.

11. A processor according to claim 10, wherein the output port of the adding/sUbtracting means is connected to the first source.

f

12. A processor according to claim 11, including an input port for data to be processed connected to the furth-er data selector and an output port for processed data connected to the output port of the adding/subtracting means.

13. A processor according to any one of the preceding claims arranged to convert an ADKM encoded signal into a PCM signal and to convert a PCM signal into an ADPCM encoded signal.

14. A digital signal processor substantially as described herein and as illustrated by the accompanying drawings.

15. Telephone apparatus including digital signal processor according to any preceding claim.

Published 1989 at The Patent Office, State House, 66'71 High Holborn, London WCIR4TP. Further copies maybe obtained from The Patent OfEice. Sales Branch, St Mary Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques ltd, St Mary Cray, Kent, Con. 1/87 Sales Branch, St Mary Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques ltd, St Mary Cray, iient, Con. 1/87