GB2214334A

GB2214334A - Integrated circuit

Info

Publication number: GB2214334A
Application number: GB8800097A
Authority: GB
Inventors: Keith Balmer
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1988-01-05
Filing date: 1988-01-05
Publication date: 1989-08-31
Anticipated expiration: 2008-01-05
Also published as: GB2214334B; GB8800097D0; US5603049A; US5504911A

Abstract

An integrated circuit having a plurality of modules 1-8 and an internal communication bus 9,10 interconnecting the modules is arranged to produce an output signal indicating which module is granted access to the bus at the time. A bus arbitration logic circuit 11 grants to a module access to the bus in response to a request from the module on the basis of the priority of its request amongst any other requests for access. The logic circuit produces the output indication on a bus 12 in digital form which is multiplexed with other data from the bus at an output port 14 of the integrated circuit. <IMAGE>

Description

INTEGRATED CIRCUIT This invention relates to an integrated circuit and in particular to such a circuit as includes at least one internal bus for conveying signals between parts of the circuit or between a part of the circuit and input or output terminals.

As integrated circuits become more complex many of them contain modules connected to a common internal communication bus. In the operation of the circuit each module makes a request for access to the bus to a controller when it wants it and the controller allocates the use of the bus to the module having the highest priority. This method of operation is satisfactory in practice, but it suffers from the disadvantage that a user observing the operation of the circuit by monitoring the signals on its contact pins does not know which module is using the bus at the time. For example, if the bus is brought out at contact pins of the circuit and through them is connected to access external memory, it will not be clear which module is making a memory access, as a memory access appears the same regardless of the module making it.This information would clearly be useful in debugging software or otherwise looking for the cause of a failure of a system to work correctly.

It is an object of the present invention to provide a solution to this problem.

According to the present invention there is provided an integrated circuit including a plurality of circuit modules, an internal communication bus common to the circuit modules, and the access control means responsive to requests from the circuit for selectively granting to the modules making the requests to modules for access to the bus one at a time, wherein the circuit includes means for producing an output indication as to which circuit module is granted access to the bus at the time.

The control means may be arranged to produce the output indicating to which module it has granted access to the bus.

The output indication may be in digital form and multiplexed with the other data on the bus.

One example of an integrated circuit according to the invention includes eight circuit modules each connected to a 16-line parallel data bus and a 20-line parallel address bus.

A multiplexer in the circuit is connected to four conductors from each of the data and address buses and multiplexes the signals on them on to a 4-line parallel output bus together with a 4-bit parallel output from the control means indicating which of the eight modules is granted access to the bus by it. As there are only eight circuit modules and there are sixteen possible 4-bit groups it follows that some of the possible 4-bit groups are not required and may be used for other purposes.

In order that the invention may be fully understood and readily carried into effect an example of the invention will now be described with reference to the accompanying drawings, of which: FIGURE 1 is a block diagram of an integrated circuit according to the example of the invention, FIGURE 2 shows the timing of a 4-bit output indication of which module has been granted access to the buses when multiplexed with 4-bit groups from the address and data buses of the example of the invention; and FIGURE 3 is a table showing the 4-bit groups allocated to the different modules in the example of Figure 1.

The integrated circuit shown in Figure 1 has eight modules 1, 2, ..., 8, each connected to an address bus 9 and a data bus 10. The address bus 9 has twenty conductors and the data bus 10 has sixteen conductors. A bus arbitration logic circuit 11 is connected to each module 1, 2, ..., 8 to receive from it a request for access to the buses 9 and 10 and to send to it either a signal indicating that it has been granted access to the buses or a signal indicating that it has been refused access to them. The circuit 11 has a four conductor output bus 12 to which it applies a 4-bit binary code representing which of the modules 1, 2, ..., 8 has been granted access to the buses 9 and 10 at the time.

A 4-bit multiplexer 13 has three sets of four conductor inputs/outputs, the bus 12, four conductors of the address bus 9 and four conductors of the data bus 10. The multiplexer 13 has a 4-bit output/input which is applied to the four pins 14 of the integrated circuit.

The sixteen conductors of the address bus 9 and the twelve conductors of the data bus 10 which are not connected to the multiplexer 13 are connected as two separate groups of inputs/outputs of a 16-bit multiplexer 16. The multiplexer 16 has a 16-bit output/input which is applied to sixteen pins 17 of the integrated circuit. Both multiplexers 13 and 16 are bidirectional and can convey both input and output signals between the pins 14 and 17 and the buses 9, 10 and 12.

Clock means not shown in Figure 1 is used to operate the multiplexers 13 and 16 so that the outgoing signals are in the required format and the incoming signals are directed correctly to the buses.

As shown in Figure 1, the four pins 14 and the sixteen pins 17 are connected through four conductors 15 and sixteen conductors 18 respectively to a memory system 19. A line 20 indicates the boundary between the integrated circuit and the external circuitry.

The modules 1, 2, ..., 8 may be signal processing devices, for example, which, after completing the operations of a process on some signal values derived from the memory system 19, seek to store the results in the memory system and derive some further signal values from it for processing.

Therefore, when a module is ready to transfer values, to or derive signals from, the memory system 19 it makes a request to the bus arbitration system logic circuit 11 for access to the buses. The circuit 11 allocates a priority to the request which may depend on which module the request is received from, on the stage of signal processing that has been reached and on the period of time for which the module has been waiting for access, for example, and sends a signal to the module indicating either that access has been granted or that it has been refused. If access is refused the module may be switched to an idle state to await the granting of access. When access is granted the module feeds its address and data information on to the buses 9 and 10 which convey the information to the other modules (for internal data transfer) and to the memory system 19.All modules may be arranged to receive signals from the buses 9 and 10 when not feeding signals to them, and to this end the modules may be allocated addresses so that they can identify and record data transmitted to them via the buses.

In the example being described the memory system 19 is a dynamic random access memory and is arranged to select the required location in the memory on receiving address information via the conductors 15 and 18. Shortly after receiving the address information the memory 19 reads the data stored in the selected location and emits corresponding data signals on the conductors 15 and 18. If the data stored at the selected address is not to be changed the data signals are used by means internal to-the memory 19 to refresh the stored data in the usual manner for dynamic memory.On the other hand, if the data stored at the selected address is to be changed, for example by substituting data from one of the modules 1, 2, ..., 8, then the data signals from the particular module appear on the conductors 15 and 18 immediately after those output by the memory 19, and the memory 19 writes the data represented by the other data signals into the selected location in place of those previously stored there.

There is a time interval between the address information's being applied to the memory 19 and its producing data signals, and during this time interval the 4bit module code from the bus arbitration logic circuit 11 is transmitted by the multiplexer 13 to the conductors 15. The memory 19 makes no use of the 4-bit module code, but a monitoring circuit (not shown) may be connected to the conductors 15 to select and store the module code so that it is accessible to a user for debugging or other purposes.

Figure 2 is a diagram showing the timing of the signals applied to the conductors 15. In each of the four parts of the memory cycle shown the 4-bits appear in parallel on the four conductors 15.

Figure 3 is a table listing the 4-bit module codes and indicating which modules they respectively represent. The eight codes used of the sixteen codes available are -allocated arbitrarily and the remaining codes ar unused. It would be possible for the unused codes to carry other status information relating to the operation of the integrated circuit provided that such use is compatible with the module codes representing which module is granted access to the buses 9 and 10.

There are other ways in which an indication of which module is granted access to the buses could be output from the integrated circuit. For example, the integrated circuit could have a number of additional contact pins respectively allocated to the modules and a particular voltage level on one pin with a different voltage level on the other pins could indicate that the module corresponding to the one pin was using the buses. In other arrangements, different multibit binary codes could be allocated respectively to the modules of the integrated circuit and output serially or in parallel from the circuit on one or more pins supplied for the purpose. Such module codes could be stored in the integrated circuit and output only on demand, for example, in response to an interrogation signal. The module codes are, of course, not limited to the four bits as described above.

The integrated circuit may have only a single bus or more than the two buses described.

In addition to their use in debugging or monitoring the functioning of the integrated circuit, the indication output by the circuit may be used to control the routing of signals external to the circuit by means of a multiplexer, for example. This would enable the modules of a single integrated circuit to be effectively connected to different external circuits through the same pins of the circuit.

Claims

CLAIMS:

1. An integrated circuit comprising a plurality of circuit modules, an internal communciation bus common to said circuit modules, said circuit modules including means for generating requests for access to said communication bus, access control means responsive to bus access requests from said circuit modules for selectively granting access one at a time to said circuit modules generating said requests and means for producing an output indication signal identifying which of said circuit modules currently has access to said communication bus.

2. An integrated circuit according to claim 1, including a plurality of connection means respectively connecting said access control means and said circuit modules, said connection means providing paths for transmission to said access control means of requests for access to said communication bus from said circuit modules, and paths for transmission from said access control means to said circuit modules of signals granting or not granting access to said communication bus and wherein said access control means includes said means for producing an output indication signal.

3. An integrated circuit according to claim 1 or claim 2, wherein said output indication signal is a digital signal.

4. An integrated circuit according to claim 3, wherein says means for producing an output indication signal produces a parallel, multi-bit binary number signal.

5. An integrated circuit according to claim 4, wherein said binary number signal is a four bit signal.

6. An integrated circuit according to claim 3, 4 or 5, wherein said output indication means can produce a number of different output indication signals greater than the number of said circuit modules, selected ones of said different output indication signals being respectively allocated to identification of said circuit module access to said communication bus and others of said different output indication signals being available for other purposes.

7. An integrated circuit according to any of claims 3 to 6, including means for multiplexing said digital signal output indication with other data to an output port of said integrated circuit.

8. An integrated circuit according to claim 7, wherein said internal communication bus includes a multi-bit data bus and a multi-bit address bus, said multiplexing means includes first and second multiplexer means for connecting conductors of said address bus and said data bus in turn to input/output ports of said integrated circuit, said multiplexers also multiplexing said output indication signal with bits from said address and data buses.

9. An integrated circuit according to claim 1, wherein said means for producing said output indication signal produces a digital output indication signal, and means is provided for outputting said digital output indication signal serially or in parallel from at least one dedicated terminal of said integrated circuit.

10. An integrated circuit according to any preceding claim, wherein said means for producing said output indication signal operates automatically.

11. An integrated circuit according to any one of claims 1 to 9, including means for providing an interrogation signal for operating said means for producing an output indication signal.

12. An integrated circuit substantially as described herein with reference to and as illustrated by the accompanying drawings.