GB2212978A - An integrated circuit having a patch array - Google Patents

An integrated circuit having a patch array Download PDF

Info

Publication number
GB2212978A
GB2212978A GB8727957A GB8727957A GB2212978A GB 2212978 A GB2212978 A GB 2212978A GB 8727957 A GB8727957 A GB 8727957A GB 8727957 A GB8727957 A GB 8727957A GB 2212978 A GB2212978 A GB 2212978A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
array
patch array
patch
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8727957A
Other versions
GB8727957D0 (en
Inventor
Ian Phillips
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB8727957A priority Critical patent/GB2212978A/en
Publication of GB8727957D0 publication Critical patent/GB8727957D0/en
Publication of GB2212978A publication Critical patent/GB2212978A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Abstract

The integrated circuit has at least one patch array (B) built into a spare space on the integrated circuit. The patch array is brought into use when faults are discovered during the manufacturing process to enable the manufacturing process to continue. The patch array consists of a gate array, and may be metalised into gate patterns to assist in testing. <IMAGE>

Description

AN INTEGRATED CIRCUIT HAVING A PATCH ARRAY The present invention relates to an integrated circuit having a patch array.
Full custom or cell based integrated circuits are more expensive to process for two main reasons.
There are only a limited set of masking stages involved in the characterisation of a gate array, typically three, whereas a cell/custom design involves a complete set of masks, typically thirteen.
The gate array base layers, known as mirrors, benefit in cost from the total volume of them produced, rather than the customers requirements only.
Custom integrated circuits, as gate arrays are inevitably wrong in some minor detail at the first, and often subsequent attempts are also wrong. For a custom circuit the cost of any change inevitably requires the generation of a complete set of new masks. The consequence for the gate array is the same, but, having only a limited mask set, the cost is lower and so is the cycle time.
Accordingly, an aim of the present invention is to provide integrated circuits having at least one patch array which is brought into use when a fault is discovered during the manufacturing process.
According to the present invention there is provided an integrated circuit having a plurality of base layers and a pluality of metalisaiton layers and at least one patch array built into a spare space on the integrated circuit, said patch array being brought into use when a fault is discovered during the development process, to enable the manufacturing process to continue on the base layers.
An embodiment of the invention will now be described with reference to the accompanying drawing in which: Figure 1 shows an integrated circuit layout having space-filling patch arrays.
The flexibility of a gate array is due to the layout of a field of usable transistors, plus a family of 'lay-on' metal patterns to characterise them into convenient logic functions. Thus any logic function can be implemented by changing only the metal layers. The cost however is silicon inefficiency and gate arrays are usually larger for a given function.
Most custom or cell based designs are very compact for most of their area, but there usually are 'gaps' where 'odd' shaped blocks fit together. As a percentage of the overall chip they are small, but then so too are the usual initial errors.
The invention is concerned with the provision in available spaces on any custom/cell designed integrated circuit A, small patches of gate array B. They would be connected to source and drain voltage supplies, or provision made to do so, and may initially be metalised into 'harmless' gate patterns, to aid testing.
Their use becomes apparent when a fault is discovered on the first and subsequent batches processed.
Because the patch arrays are little sections of gate array, a large set of 'cell' metalisation options are available, these can be used to provide the level of correction usually required at this stage of manufacture. Further, because the changes, which can be quite extensive, only involve changing the metal layers, the cost and timescale becomes comparable with that of gate arrays.
Further, as customers purchasing the initial silicon are confident of getting working product from the 'base layers' of their initial design, they can at little risk commit larger initial batches, holding back a quantity at a 'pseudo-mirror' stage, thus in his turn gaining the cost benefit of scale.
The above description is not intended to limit the scope of the present invention, for example some designs involving small individual changes, such as address fields, could be designed intending to use the patch arrays for these variants.

Claims (6)

1. An integrated circuit having a plurality of base layers and a plurality of metalisation layers and at least one patch array built into a spare space on the integrated circuit, said patch array being brought into use when a fault is discovered during the manufacturing process, to enable the development process to continue on the base layers.
2. An integrated circuit as claimed in claim 1, wherein the patch array consists of a gate array.
3. An integrated circuit as claimed in claim 2, wherein the array is metalised into 'harmless' gate patterns to assist in testing.
4. An integrated circuit as claimed in claim 3, wherein the gate array is used to provide level correction.
5. An integrated circuit substantially as hereinbefore described.
6. An integrated circuit substantially as hereinbefore described with reference to Figure 1.
GB8727957A 1987-11-30 1987-11-30 An integrated circuit having a patch array Withdrawn GB2212978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8727957A GB2212978A (en) 1987-11-30 1987-11-30 An integrated circuit having a patch array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8727957A GB2212978A (en) 1987-11-30 1987-11-30 An integrated circuit having a patch array

Publications (2)

Publication Number Publication Date
GB8727957D0 GB8727957D0 (en) 1988-01-06
GB2212978A true GB2212978A (en) 1989-08-02

Family

ID=10627744

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8727957A Withdrawn GB2212978A (en) 1987-11-30 1987-11-30 An integrated circuit having a patch array

Country Status (1)

Country Link
GB (1) GB2212978A (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1297924A (en) * 1968-11-29 1972-11-29
EP0044628A2 (en) * 1980-06-30 1982-01-27 Inmos Corporation Redundancy scheme for an MOS memory
GB2082005A (en) * 1980-02-12 1982-02-24 Mostek Corp Block redundancy for memory array
EP0089457A2 (en) * 1982-03-23 1983-09-28 Texas Instruments Incorporated Avalanche fuse element as programmable memory
GB2130770A (en) * 1982-11-24 1984-06-06 Western Electric Co Improvements in or relating to semiconductor memories
EP0112675A1 (en) * 1982-12-28 1984-07-04 Fujitsu Limited A link structure selectively activable to create a conducting link in an integrated circuit
GB2135485A (en) * 1983-01-21 1984-08-30 Hitachi Ltd Semiconductor memory device
EP0135780A2 (en) * 1983-09-02 1985-04-03 International Business Machines Corporation Reconfigurable memory
EP0202873A2 (en) * 1985-05-16 1986-11-26 Fujitsu Limited Semiconductor memory device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1297924A (en) * 1968-11-29 1972-11-29
GB2082005A (en) * 1980-02-12 1982-02-24 Mostek Corp Block redundancy for memory array
EP0044628A2 (en) * 1980-06-30 1982-01-27 Inmos Corporation Redundancy scheme for an MOS memory
EP0089457A2 (en) * 1982-03-23 1983-09-28 Texas Instruments Incorporated Avalanche fuse element as programmable memory
GB2130770A (en) * 1982-11-24 1984-06-06 Western Electric Co Improvements in or relating to semiconductor memories
EP0112675A1 (en) * 1982-12-28 1984-07-04 Fujitsu Limited A link structure selectively activable to create a conducting link in an integrated circuit
GB2135485A (en) * 1983-01-21 1984-08-30 Hitachi Ltd Semiconductor memory device
EP0135780A2 (en) * 1983-09-02 1985-04-03 International Business Machines Corporation Reconfigurable memory
EP0202873A2 (en) * 1985-05-16 1986-11-26 Fujitsu Limited Semiconductor memory device

Also Published As

Publication number Publication date
GB8727957D0 (en) 1988-01-06

Similar Documents

Publication Publication Date Title
EP0549949A2 (en) Built-in self test circuit
US7326595B2 (en) Semiconductor integrated circuit and method of redesigning same
GB1281933A (en) Improvements in and relating to the manufacture of integrated circuit devices
WO2000036525A3 (en) Mechanisms for making and inspecting reticles
TW200925919A (en) Integrated circuit design based on scan design technology
US20080148206A1 (en) Method of designing semiconductor integrated circuits, and semiconductor integrated circuits that allow precise adjustment of delay time
GB2212978A (en) An integrated circuit having a patch array
US20060093965A1 (en) Variable mask field exposure
WO1998040913A1 (en) Semiconductor integrated circuit device with its layout designed by the cell base method
US5387810A (en) Cell library for semiconductor integrated circuit design
EP0507441B1 (en) Counter circuit
EP0347332B1 (en) Method of forming semiconductor integrated circuit using master slice approach
JP3187739B2 (en) Semiconductor integrated circuit and test method therefor
KR0133269B1 (en) Glass mask for semiconductor device and making method thereof
JPS5593598A (en) Memory unit
EP0609047A2 (en) Process for fabricating an ASIC device having a gate-array function block
JPS6012741A (en) Semiconductor integrated circuit
Mucha et al. Self-test in a standard cell environment
US20060279329A1 (en) Mask-programmable logic macro and method for programming a logic macro
US6774671B2 (en) Multi-purpose transistor array
KR0141419B1 (en) Analog asic
DE3887335T2 (en) INTEGRATED CIRCUITS.
JPS60251719A (en) Mos transistor circuit
US20020047789A1 (en) Method of designing semiconductor integrated circuit
KR100333204B1 (en) Semiconductor integrated circuit device with its layout designed by the cell base method

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)