GB2208344A - Digital display system - Google Patents

Abstract

A digital display system in which image data is held in a video memory comprising a number of planes 20-29. During display, one bit is read out of each plane to produce a multi-bit display value for the pixel currently being scanned. The video memory can also be accessed by a processor, for updating the display. In a normal access mode, one plane is selected (using processor address bits PADD 18-21, decoded at 52) and one word within that plane is accessed for reading or writing. In a fast graphics mode (FGM), (using register 53), a specified combination of planes is selected, and data is written into a word within each of those planes in parallel. This allows pixel data to be updated more rapidly than in the normal mode. The selection of the mode is by means of processor address bits (PADD 22, 23). <IMAGE>

Description

DIGITAL DISPLAY SYSTEM Background to the invention This invention relates to digital display systems.

More specifically, the invention is concerned with a digital display system in which data to be displayed is stored in a video memory, and is read out sequentially from the memory to provide video signals for a raster-scanned display device, such as a cathode ray tube (CRT).

In such a system, the video memory may also be accessible by way of a data/address bus, to allow the memory to be read and updated by an associated processing unit.

The object of the present invention is to provide an improved organisation for such a video memory, which facilitates updating of the display data.

Summary of the invention According to the invention, there is provided a digital display system comprising a raster-scanned display device and a video memory for holding data to be displayed, characterised in that (a) the video memory comprises a plurality of memory planes, (b) during display, one bit of data is read out from each of the planes in parallel, to provide a multi-bit display value for the picture element of the display currently being scanned, (c) in a first access mode, one of said planes is selected, and one data word within that plane is selected for reading or writing, and (d) in a second access mode, a plurality of said planes are selected and one data word within each of these planes is selected for writing in parallel.

One display system in accordance with the invention will now be described by way of example with reference to the accompanying drawings.

Brief description of the drawings Figure 1 is an overall view of a digital display system including a processor, a video memory, and a CRT monitor.

Figure 2 shows the video memory in more detail, illustrating the way in which the memory is organised into a plurality of planes.

Figure 3 shows one of the video memory planes in greater detail.

Figure 4 shows a circuit for addressing the memory planes.

Figure 5 shows a circuit for generating column address strobe signals (CAS) for selecting the meory planes.

Description of an embodiment of the invention Referring to Figure 1, the digital display system comprises a high-resolution raster-scanned colour CRT monitor 10. This displays an image consisting of 1408 columns and 1024 rows of picture elements (pixels), at a 60Hz refresh rate. The pixel clock rate, which defines the time taken to scan each pixel, is 128 MHZ.

The monitor 10 may be conventional and hence will not be described in further detail.

The system also includes a video memory 11 and a system memory 12. Both the memories can be accessed by a data processor 13, by way of an address bus 14 and a bidirectional data bus 15. The address bus carries a 24-bit address PADD 0-23.

In operation, the video memory 11 stores a pattern of bits defining an image to be displayed on the CRT monitor 10. This image can be updated, when required, by the processor 13. The system memory 12 is used as the main memory for the processor. Both the video memory 11 and the system memory 12 appear to the processor 13 as part of a single memory address space.

If the whole of the video memory is not required for storing an image (e.g. if only a monochrome display is required) then unused portions of the video memory can be used by the processor as an extension of the system memory.

The processor 13 may be a conventional microprocessor, and will not be described in detail.

During display of an image, the video memory 11 outputs a succession of 8-bit signals, each of which defines a display value for one pixel of the image.

These 8-bit signals are fed to the address input of a 256 x 24 random access memory (RAM) 16, which translates each 8-bit signal into three 8-bit colour signals, which defines the intensity levels for the three colours red, green and blue. These colour signals are fed to respective digital-to-analogue converters 17, so as to produce the three video signals R, G, B for the CRT monitor 10.

Thus, it can be seen that 224 (more than 16 million) different colours can be generated by the system, each colour being defined by the 24 output bits from the RAM 16. At any given time, however, only a subset consisting of 28 (256) different colours can be displayed, these colours being defined by the contents of the RAM 16, and being selected by the 8-bit output from the video memory. In other words, the RAM 16 provides a palette of 256 different colours.

Referring now to Figure 2, this shows the video memory 10 in greater detail.

The video memory comprises ten planes 20-29.

Each plane holds 64K (65536) 32-bit words of data. As will be described below, any one of these 32-bit words from one of the planes can be accessed by the processor over the address and data busses for reading or writing.

Alternatively, in a special mode referred to as the fast graphics mode (FGM), the processor can access a word from each of a plurality of planes simultaneously. In order to produce the display, data is read out sequentially, a bit at a time from each of the planes (i.e. ten bits are output in parallel from the ten planes).

The first eight planes (20-27) are used to hold colour information, defining the colours of the pixels in the display: that is, each pixel is defined by eight bits, held in corresponding locations of the planes 20-27. The other two planes are referred to as the mask and bichrome planes.

The bichrome plane 29 is a bit map which defines a two-colour image that can be overlaid on the main image held in the colour planes 20-27. Each bit in the bichrome plane selects either a foreground colour or a background colour for the corresponding pixel.

The mask plane 28 holds a pattern of bits defining a window (not necessarily a simple rectangle) in the image, which specifies where the bichrome image is to be visible, and where the main colour image is to be visible.

The output bit from the mask plane controls a multiplexer 30, the output of which provides the eight-bit output from the video memory to the RAM 16 (Figure 1). Where the mask bit is equal to 0, the multiplexer 30 selects its first input, which is connected to the serial outputs of the eight colour planes 20-27. Where the mask bit equals 1, the multiplexer selects its second input which is connected to the output of an eight-bit bichrome register 31, which defines a background colour for the bichrome image. The least significant bit of the bichrome register is selectively inverted, by means of an exclusive-OR gate 32 when the output bit from the bichrome plane is 1, so as to produce the code for the foreground colour.

Thus, it can be seen that where the mask equals 0, the colour image held in planes 20-27 is displayed, and where the mask equals 1 the bichrome image is displayed.

Referring now to Figure 3, this shows one of the ten planes 20-29 in greater detail. The other planes are all similar.

The plane comprises eight VRAM (video random access memory) chips 35. In this example each VRAM is an NEC uPD41264 dual port memory, full details of which are available from the manufacturer's handbook. Briefly, however, the VRAM can act as a normal random access memory, having 64K 4-bit locations,any one of which can be accessed for reading or writing by way of a 4-bit data input/output port 36. Each VRAM also has an internal 256 X 4-bit data register which can be loaded with data from any selected row of the memory and then operated to shift out the contents of its locations sequentially, by way of a 4-bit shift output port 37. The shifting is enabled by an input SOE, and is controlled by a shift clock SC.

The VRAM has an 8-bit address input, which receives an address ADD 0-7, a row address strobe input, which receives a signal RAS, and a column address strobe input, which receives a signal CAS.

At the falling edge of RAS, the eight address bits ADD 0-7 are strobed into an internal row address register within the VRAM. Similarly, at the falling edge of CAS, the eight address bits ADD 0-7 are strobed into an internal column address register within the VRAM. The row and column addresses in the address buffers select one of the 4-bit locations in each VRAM.

The VRAM also has an internal mask register which can be loaded with a 4-bit mask pattern from the IO port, and then used as a mask for subsequent write operations, allowing data to be written only to specified bit positions.

The VRAM also has control inputs WB/WE and DT/OE each of which has a dual function. At the falling edge of RAS, WB/WE controls the loading of the internal mask register, and DT/OE controls loading of the internal data register. At the falling edge of CAS, WB/WE acts as a write enable, and DT/OE acts as an output enable, for controlling input and output of data over the IO port.

The input/output ports 36 of the eight VRAMs are connected to the processor data bus 15. Thus, it can be seen that a 32-bit data word can be accessed in the VRAMs, for reading or writing over the data bus 15.

The shifting of the VRAMs is controlled by a 4 MHz shift clock signal which is fed to the inputs SC of all the VRAMs. Thus, it can be seen that one 32-bit word is shifted out of the eight VRAMs every 0.25 microseconds.

The shift output ports 37 of the VRAMs are connected, in two groups of four, to parallel data inputs of two shift registers 38, 39. Each shift register is loaded with four bits by means of a 16 MHz load clock signal LD. Thus, the shift registers are loaded four times for each shift of the VRAMs. Each time the shift registers 38, 39 are loaded, a different pair of the VRAMs is selected for output, by means of respective shift output enable signals SOE0-3. Hence, it can be seen that each shift register 38, 39 receives, in turn, four bits from each of the four VRAMs to which it is connected.

Each of the shift registers 38, 39 receives a 64 MHz shift clock signal CK which causes the contents of the register to be shifted by one bit position at each clock beat. Hence, the four bits in each shift register are shifted out serially from the register before the next four bits are received from the VRAM.

The serial data outputs from the shift registers 38, 39 are connected to a multiplexer 40 which selects one bit from each shift register alternately, so as to produce a multiplexed stream of bits at 128 MHz, i.e. the pixel rate of the display. The output of the multiplexer 40 provides the serial output of the plane which is fed to the multiplexer 30 (Figure 2).

Referring now to Figure 4, this shows the way in which the address ADD 0-7 for the VRAMs is produced.

Bits PADD 2-9 of the processor address bus are stored in an address latch 41. A multiplexer 42 then selects either the stored bits 2-9, or bits 10-17. The selected bits are stored in an address register 43, the output of which provides the address signal ADD 0-7 for all the VRAMs in all the planes.

As mentioned above, each of the VRAMs receives row and column address signals RAS and CAS. The RAS signals are common to all the VRAMs in all the planes.

However, each plane receives its own separate CAS signal CAS 0-CAS 9 (i.e. one CAS signal is common to the eight VRAMS in a plane).

Referring now to Figure 5, this shows the way in which these CAS signals are generated.

The signals CAS 0-CAS 9 are derived from respective multiplexers 50 by way of respective AND gates 51. The AND gates are enabled by a signal CASEN.

The multiplexers 50 are controlled by a mode control signal FGM. This signal is normally 0, and is set to 1 for operation in the fast graphics mode.

When FGM=0, the multiplexers 50 select the output of a 4:10 decoder 52, which decodes the address bits PADD 18-21 on the address bus, to produce a signal on one of the decoder outputs. Thus, in this mode, a CAS signal is produced for only one of the planes, as specified by the address bits PADD 18-21. This allows a single 32-bit word within the selected plane to be accessed.

In the fast graphics mode (FGM=1), the generation of the CAS signals is controlled by a special register 53, referred to as the FGM register. This register contains three fields: (1) plane data: this consists of 10 bits, one for each plane of the video memory, defining a data value to be written to the planes in FGM mode.

(2) plane mask: this consists of 10 bits, one for each plane, specifying which of the ten planes is allowed to be written to in FGM mode.

(3) Plane enable: this consists of 8 bits, specifying which of the eight colour planes (20-27) is allowed to output video data for the display.

The plane data is fed, by way of ten exclusive-OR gates 54 and ten AND gates 55 to the second inputs of the multiplexers 50, and is thus selected when FGM=1. The exclusive-OR gates all receive a control signal INV which allows the plane data to be selectively inverted. The AND gates 55 are controlled by respective bits of the plane mask field from the FGM register.

Thus, it can be seen that, in the FGM mode, a selected combination of the CAS signals is generated, allowing data to be written to a number of the planes 20-29 simultaneously.

For example, in order to set one or more pixels to a specified colour, the following operations are performed. First, the desired colour value is set in the plane data field of the FGM register. It is assumed that the plane mask field is all-ones in this case. Data is applied to the data bus 15, having a one in each bit position corresponding to a pixel which it is required to set to the specified colour. This bit pattern is loaded into the internal mask registers of the VRAMS at the falling edge of RAS, so as to select the required bit positions for writing.

The fast graphics mode is then selected (FGM=1), with the signal INV initially equal to 0. This causes a CAS signal to be applied to all the planes corresponding to ones in the plane data field of the FGM register.

Thus, one word location in each of these planes is accessed, and data ones are written simultaneously into the selected bit position of each addressed location from the data bus.

Now the signal INV is set to 1, so as to invert the plane data, and at the same time the data bus 15 is forced to all-zero. This causes a CAS signal to be applied to all the planes corresponding to zeros in the plane data field of the FGM register. Thus, a word location in each of these planes is accessed, and zero data is written into the selected bit position of all these locations in parallel.

It can be seen that the fast graphics mode thus allows a particular pixel or group of pixels to be set to a specified colour value using just two write operations: a first to write the ones of the colour code, and a second to write the zeros. This is considerably faster than the normal mode (FGM=0) where each of the ten planes 20-29 would have to be accessed in turn to write the desired data into it.

The mode control signal FGM is produced by an AND gate 56 which receives the address bit PADD 23 and the inverse of the address bit PADD 22. Thus, it can be seen that if the input address is in a predetermined range such that PADD 22=0 and PADD 23=1, the fast graphics mode is selected (FGM=1). If the input address is outside this range, then the normal mode is selected.

The bits of the plane enable field of the FGM register provide eight plane enable signals PEN 0-PEN 7 which are used to enable the outputs of the shift registers 38, 39 in the eight colour planes 20-27. If one of these bits is set to zero, the output of the corresponding plane is suppressed. This facility is used to suppress the serial outputs from those planes which are not being used to store video data but rather are being used as extensions of the system memory, so as to prevent those planes from outputting data to the display.

Claims (9)

CLAIMS:

1. A digital display system comprising a raster-scanned display device and a video memory for holding data to be displayed, characterised in that (a) the video memory comprises a plurality of memory planes, (b) during display, one bit of data is read out from each of the planes in parallel, to provide a multi-bit display value for the picture element of the display currently being scanned, (c) in a first access mode, one of said planes is selected, and one data word within that plane is selected for reading or writing, and (d) in a second access mode, a plurality of said planes are selected and one data word within each of these planes is selected for writing in parallel.

2. A system according to Claim 1 wherein the system has an address bus for receiving an input address comprising a first portion specifying one of the planes and a second portion specifying one data word within that plane.

3. A system according to Claim 2 wherein the first and second access modes are controlled by a mode control signal which is derived from said input address, such that input addresses in a first predetermined range cause the first access mode to be selected, and addresses in a second predetermined range cause the second access mode to be selected.

4. A system according to Claim 3 including a decoder for decoding the first portion of the input address to produce a first selection signal indicating which plane is to be selected in the first access mode, a register for holding a pattern of bits providing a second selection signal indicating which planes are to be selected in the second access mode, and multiplexing means, controlled by the mode control signal, for selecting the first selection signal in the first access mode and selecting the second selection signal in the second access mode.

5. A system according to any preceding claim wherein the planes are selected by applying address strobe signals to the planes.

6. A system according to any preceding claim wherein said memory planes comprise a plurality of colour planes defining a multi-colour image, a bichrome plane, defining an alternative two-colour image, and a mask plane defining a window in which the two-colour image is to be visable in the display.

7. A digital display system substantially as hereinbefore described with reference to the accompanying drawings.

8. A data processing system including a digital display system as claimed in any preceding claim, in combination with a data processor.

9. A data processing system substantially as hereinbefore described with reference to the accomanying drawings.