GB2181928A - Teletext television receivers - Google Patents

Description

1 GB2181928A 1

SPECIFICATION

Teletext television receivers 1 > 45 c This invention relates to teletext television receivers, that is, television receivers suitable for receiving television transmissions of a type in which coded data pulses representing alphanumeric text for display or other teletext infor- mation are transmitted in a television signal in television lines where no picture signals representing normal picture information are present.

The publication -Broadcast Teletext Specification-, September 1976, published jointly by the British Broadcasting Corporation, Independent Broadcasting Authority and British Radio Equipment Manufacturers' Association, discloses a specification for a television transmission of the above type for use in 625-line television systems (e.g. as transmitted in the United Kingdom). Also, a television system for implementing this type of television transmission is described in United Kingdom patent specification 1 370 535.

In the above-identified -Broadcast Teletext Specification-, a quantity of teletext information to be displayed as an entity on a television screen is termed a page and will be so termed hereinafter. All of the pages which are available for display are transmitted in a recurrent cycle, with or without up-dating page information, as appropriate. A teletext television receiver includes a teletext decoder and any page selected by a viewer for display is ac- quired by the teletext decoder from the cyclic transmission the next time it occurs therein and is stored in a page memory of the teletext decoder until replaced by a subsequently acquired page. A page consists of up to 24 data rows each having 40 character positions. The first data row (Row 0) of each page is termed a page-header and contains inter-alia the page number. The transmission of each page begins with, and includes, its pageheader and ends with, and excludes, the next 110 page-header which is transmitted. Thus, it is assumed that all of the data rows which are transmitted between two successively transmitted different page-headers belong to the page having the first page-header. The assumption avoids the need to include in each data row data for identifying the page to which the row belongs. Also, there is rowadaptive transmission in that data rows con- taining no information are not transmitted. Because different groups (magazines) of pages use the same range of page numbers, so that more than one page can have the same page number within that range, and because, as transmitted, the pages from different magazines may have their data rows interleaved, each data row also includes data which identifies the magazine containing the page that the row belongs to.

It is also a requirement of said -Broadcast Teletext Specification- that the data for an entire data row is contained in a single television line that is used for transmitting teletext information. Such a television line is termed a data-line and will be so termed hereinafter. The -Broadcast Teletext Specification- further specifies that only data-lines in the vertical or field-blanking intervals (V131) should be used for transmitting teletext information. Initially, teletext transmissions in the United Kingdom used television lines 17 and 18 in odd fields and television lines 330 and 331 in even fields as data- lines, but current teletext transmissions in the United Kingdom now use six television lines in each field as data-lines. The V131 transmission is thus, in effect, multiplexed with the normal picture transmission and the teletext information transmitted in this way can be displayed at a teletext television receiver as a selectable alternative to the normal picture information.

The said -Broadcast Teletext Specificationprovides a page erasure interval by specifying, in effect, that rows of a page will be transmitted such as to allow an active television field period between the transmission of a page-header of a page and the transmission of subsequent data rows for the page. This interval, which is 20 ms. in 625- line television systems, allows time for a teletext decoder to respond to receipt of the page-header of a new page selected by a viewer to erase from its page memory any previously acquired page that is already stored therein, before the data rows of the new page are received. The page memory is thus made ready to store the data rows of the new pages as transmitted in the data-lines of field-blanking intervals subsequent to the field-blanking interval in which the page-header was transmitted. This provision simplifies teletext decoder design by allowing the operation of the teletext decoder to be relatively slow.

If the data of an 'old' page in the page memory is not erased before a 'new' page is stored therein, the resulting display would include any data rows of the 'old' page that have not been over-written by corresponding data rows of the 'new' page. This display of spurious data rows would occur in respect of every 'new' page that did not contain the full 24 data rows.

A proposed extension of teletext transmission is for -full-channeloperation in which all of the television lines of each field of a TV channel are employed for transmitting teletext information. Thus, a complete TV channel, which can be an over-air broadcast channel or a cable channel, is dedicated to teletext transmission.

If a teletext specification adopted for -fullchannel- operation included the 20ms. page erasure interval discussed above, then after the transmission of a page-header of a parti- cular page in one television (data) line, 312 2 GB2181928A 2 subsequent data-lines would have to occur be fore the first data row of that page could be transmitted. This means that the flexibility and usuable capacity of a TV channel dedicated to -full-channel- operation would be severely re stricted. For instance, for a serial mode of page transmission in which the pages are transmitted sequentially with all the data rows of each page being transmitted successively between the page-header for the page and the 75 page-header for the next page, only about 10% of the total capacity of the channel would be usuable.

Therefore, for efficient -full-channel- oper ation, a teletext transmission is required in which data rows of a page can be transmitted immediately after the transmission of the page-header of the page. In other words, in the most extreme case, the first data row of a page should be transmitted in the next data- 85 line following the data-line in which the page header for the page is transmitted. However, this reduces an effective minimum page era sure interval for a teletext decoder to approxi mately 40ps, (i.e. the period in a data-line that 90 contains the page-header data) and this poses the problem of making the teletext decoder operate fast enough after recognition of a se lected page in one data-line to clear its page memory in time to store the first data row of 95 the selected page as received in the immedi ately following data line.

It is an object of the present invention to provide in a teletext decoder a means of cir cumventing this problem.

According to the invention there is provided a teletext decoder for use in a television re ceiver which is suitable for receiving teletext television transmissions of the type set forth above, in which the teletext information com prises pages which are transmitted in a recur rent cycle, each page comprising a plurality of data rows containing character data codes, of which rows the first data row as transmitted includes the page number and each data row includes an individual row address; said tele text decoder comprising means for selecting a page by its page number, means for detecting a selected page number when received, a page memory for storing the character data codes in each received data row of a selected page in respective character locations of a re spective memory portion which is identifed by the row address of the data row, the page memory being a random access memory into which character data codes can be written at the respective character locations and each data code can over-write and thereby replace any data code already written into its charac ter location by a previous writing action, and character generator means responsive to data read from stored data rows to generate video signals appropriate for producing a visual dis play of the selected page; and said teletext decoder being characterised by further corn- prising display control means for permitting visual display only of the stored data rows of the selected page.

The provision of the display control means avoids the need to erase previously stored data in the page memory before the data for a new page is written into it. Of course, the character locations of any memory portions in the page memory that have not had data codes for the relevant data row of the new page written into them, may still contain old data codes previously written-in. However, these old data codes do not result in characters being displayed in the corresponding data rows of the new page because of the action of the display control means.

In carrying out the invention, the display control means can comprise, a --row-foundregister having an individual flag position for each possible data row (e.g. 23) that a page can have adaptively, together with moans for re-setting this register in response to the detection of the page number of a selected page, means for entering a flag into the relevant flag position for each received data row of the selected page, and means for inhibiting the visual display of any data row that does not have a flag in the flag position for that data row.

Thus, the teletext decoder is made ready to receive a new page immediately after the 11 row-found" register has been reset. Assuming a maximum of 23 data rows (plus the page-header) per page, and assuming that each flag position of the register is a single bit position, then only 23 bit positions have to be emptied before new data can be received and stored in the page memory. In comparison, (assuming 7-bit character data codes) an exist- ing decoder would have to clear 23 x 7 x 40 = 6440 bit positions to achieve the same result. The "row-found" register may have a permanently set flag position for the data row that contains the page number, i.e. the page- header (Row 0).

The "row-found" register may be composed of a plurality of latches which form the individual flag positions of the register. Alternatively, a portion of a memory device which forms the page memory may serve as the row-found" register.

In an existing form of teletext decoder, erasure of the page memory is effected by writing into each character location the data code for displaying a blank space. Subsequently, as the character data codes of a selected page are received, they over-write the---space-data code in the relevant character locations. A further feature of this existing form of teletext decoder is that each character data code that is received is checked for parity. If there is a parity error then the data code is rejected on that reception of it by a write inhibit condition. If the data code has previously been received with correct parity, then the data code will 3 GB2181928A 3 1 45 t already be stored in the relevant character location of the page memory. If it has not been received, then the data code for the blank space will be stored in that location and the resulting display of the page will have a blank space at the character position concerned.

In order to preserve this feature of displaying blank spaces at character positions for which no character data codes have been re- ceived correctly, a teletext decoder according to the invention may include means which are operable such that, following the detection of a selected page, a parity error in the first reception of a character data code will cause the data code for a blank space to be written into the page memory at the character location concerned, whereas on subsequent receptions of the character data code a parity error will cause a write inhibit condition to obtain.

In further considering the nature of the invention reference will now be made by way of example to the accompanying drawings, of which:

Figure 1 is a block diagram of a teletext television receiver including a teletext decoder in which the invention can be embodied; Figures 2 and 3 are respective block diagrams of display control means according to the invention for use in the teletext decoder in Figure 1; Figure 4 is a block diagram showing elements of the teletext decoder in Figure 1 with further elements for implementing the invention; and Figure 5 is a block diagram illustrating a modification of the invention.

Referring to the drawings, the teletext televi sion receiver shown in Figure 1 comprises vi deo and data processing circuits for receiving and displaying both normal picture information and teletext information. The front end FE of the receiver comprises the usual amplifying, tuning and i.f. detector circuits, and is con nected to receive an incoming television video signal VS. For normal picture display by the 110 television receiver, the demodulated video sig nal VS' is applied to a colour decoder which produces the R, G and B component signals for the picture display. Time base circuits for a display tube DT receive the usual line and 115 field synchronising pulses from a sync. separa tor circuit which extracts these synchronising pulses from the video signal V9. The element CD represents the colour decoder and these other circuit elements which are provided for 120 conventional picture display.

The demodulated video signal VS' is also applied to a teletext decoder section of the teletext television receiver which deals with the receipt and display of the alpha-numeric text and other teletext information that is re ceived in digitally coded form. This section comprises a video processor circuit VP which performs inter alia data slicing for retrieving teletext data pulses D from the video signal V9. The video processor VP also produces input data clock pulses C from the data pulses D. The data pulses D are fed together with the clock pulses C to a data acquisition circuit DAC which is operable to feed selected groups D/G of the teletext data pulses to a memory MEM as address and display information. The memory MEM has a capacity for storing at least one page of information, comprising a plurality of data rows. The page and row format laid down in the aforementioned -Broadcast Teletext Specification- is assumed.

A logic processor PRO is operable in accor- dance with select signals S applied to it from a remote control arrangement RC to control which groups of teletext data pulses D/G are acquired by the data acquisition circuit DAC. The arrangement RC has a receiver part RR and a remote transmitter part comprising a transmitter TX and a keypad KP. The processor PRO is further operable to read out from the memory MEM display information for the selected page, for application to a character generator CG which is responsive to this display information to provide R, G, B component signals for the display. A timing circuit TC provides timing signals on connections tl to t3 for the circuit elements DAC, MEM and CG.

These circuit elements and the timing circuit TC are accessed by the processor PRO via an interface circuit INT. The operation of the timing circuit is synchronised with the received video signal VS by a composite pulse signal VCS which contains the line (LS) and field (FS) synchronising pulses which are separated from the demodulated video signal VS' in the video processor VP.

In the teletext television receiver shown in Figure 1, only single line connections have been shown for the interconnections between the various circuit elements for the sake of simplicity. However, it will be apparent to a person skilled in the art that in practice most of these interconnections would be multi-line. For instance, whereas the teletext data pulses D retrieved from the video signal VS' would be applied serially to the data acquisition circuit DAC over a single connection, serial-toparallel conversion would take place within this circuit DAC, so that the groups D/G of teletext data pulses would be applied to the memory MEM in parallel over a multi-line connection. Also, the connection between the processor PRO and the interface circuit INT would be a multi- line bus, for instance, a socalled 12C bus. The processor PRO can be a commercially available microcomputer; e.g. from the MAB 8400 Series (Philips). The cir- cuit elements DAC, CG, TC and INT can be the integrated circuit EURO CCT type SAA 5240 (Mullard). The circuit element VP can be the integrated circuit VIP2 type SAA 5230 (Mullard). Although a composite television re- ceiver for receiving both normal picture infor- 4 GB2181928A 4 nation and teletext information is exemplified in Figure 1, it will be appreciated that the teletext decoder section for data acquisition together with the front end FE may be pro- vided as a separate teletext decoder which is adapted to feed either a CRT display monitor or a conventional television receiver.

In accordance with the present invention the teletext decoder section of the television re- ceiver of Figure 1 can include a display control means which operates to permit the display of only those data rows stored in the memory MEM that belong to the last selected page.

In Figure 2, one implementation of such a display control means comprises a plurality of latches L1 to L23 which pertain respectively to the data rows R 'I to R23 of a teletext page. These latches L1 to L23 serve as respective flag positions of a---row- found- register. The display control means also comprises a plurality of AND- gates GA1 to GA23 which have 'enabling' inputs (e) connected respectively to the Q-outputs of 01 to Q23 of the latches L1 to L23. The gates GA1 to GA23 have individual 'data' inputs (d) connected to respective output leads dl to d23 of a 1-of-24 decoder BCD1. The outputs of the gates GA1 to GA23 are combined by an OR-gate G01 which produces a display control signal D/N that has a high (active) level during the time that any one of the gates GA1 to GA23 is open to Rroduce a high active output level, the signal D/N having a low (inactive) level at all times when none of the gates GA 1 to GA23 is open.

Figure 2 also shows a second 1-of-24 decoder BCD2 and a counter COU, the latter being included in the timing circuit (TC-Figure 1). The decoder BCD2 has as set of binary input leads bil to which are applied groups of coded data pulses WRA which form the write row address information in the groups D/G of teletext data pulses produced by the data acquisition circuit DAC and are otherwise applied to the memory MEM. The output leads dl' to d23' of the decoder BCD2 are connected to the 'set' inputs (s) of the latches L1 to L23, respectively. Thus, as the data rows of a selected page are written into the memory MEM, a particular one of the latches L1 to L23 is set for each data row that is present in the page. The row addresses of the memory (MEM-Figure 1) are subsequently addressed to read out the data rows of the selected page for display. This addressing is effected by groups of coded data pulses PRA which form read row address information and which are produced sequentially by the counter COU in response to a row display clock pulse rdcp. The decoder BCD1 has its set of binary input leads bi2 addressed by the row address information PRA and is responsive to produce a control signal on each of its output leads dl to d23 in turn. For the data rows that are actually present in the selected page stored in the memory, only the corresponding latches L1 to L23 will be set and only those of the AND-gates GA1 to GA23 which are enabled by the set latches will open to pass the control signal to the ORgate G01 to provide the display control signal DIN-with a high active level. The signal D/N is used to allow display to occur when it has a high active level and to inhibit display when it has a low active level. Suitably, the signal DI-N can be used to turn on or turn off the R, G, B component signals produced by the character generator (CG-Figure 1). Alternatively, the signal D/-N when it has a high active level, can be used to force the character generator CG to display a blank space, as will be described. When a request for a new page is made (or the memory is otherwise to receive fresh page information) a reset signal is applied to the 'reset' inputs (rs) of all the latches L1 to L23 to reset them to their nonflag condition. In order to allow data in Row 0 (page-header) always to be displayed, an extra gate GAO is provided which is permanently enabled from a reference point (+). This gate is open each time the row address information for Row 0 causes the decoder BCD1 to produce a control signal on the output lead do. A second implementation of the display control means shown in Figure 3 also includes the latches L1 to L23 and the second decoder BCD2, so that when a page is written into the memory MEM, the latches corresponding to the data rows actually present in the page are set to the flag position. Instead of the first decoder and AND-gates (BCD1, GA1... GA23), there is now provided a shift register SR having an individual position for each of the latches. This shift register SR is stepped by the row display clock pulse rdcp and its output signal forms the display control signal D/W Prior to each field of the display, the condition (set or reset) of the latches is loaded into the corresponding positions of shift register SR by the field sync. pulse FS. As each row display clock pulse rdcp occurs in the following field, the data row concerned is displayed or not, according as the output signal D/Rfrom the shift register SR has a high active level or a low active level. The shift register SR has an additional position which is provided in respect of Row 0 and is always set directly by the field sync. pulse FS. The arrangement represented by the block diagram of Figure 4 extends the operation of display control means according to the invention by including the means whereby a parity.error in the first reception of a character data code will cause a space to be written into the character location concerned, whereas on subsequent receptions of the character data code a parity error will cause a write inhibit condition to obtain. The block diagram of Figure 4 shows elements of the data acquisition circuit (DAC Figure 1) as well as elements of the 9 GB2181928A 5 k display control means. More specially, the received teletext data pulses D are clocked into an 8-bit shift register SR/8 by the clock pulses C. In the aforesaid -Broadcast Teletext Specification-, each teletext data row includes for byte synchronisation an 8-bit framing code. This framing code is looked for by a framing code detector FCD and when it is found, this indicates the start of proper data on a teletext data-line and a 'start' signal ST is applied by the detector FCD to a data bit counter BC. The bit counter BC is clocked by the clock pulses C and thus counts through the teletext data bits as they are clocked into the input shift register SR/8. Various decodes from this bit counter BC provide pulses to other parts of the data acquisition circuit at certain times during the data-line. One of these decodes provides a signal (-. 8) every eight clock pulses, and is used to clock an 8bit latch LA. The serial teletext data stream is thus broken up into 8-bit words.

Seven of the eight bits of words from the latch LA form display information D] to be stored in the memory MEM. The eighth bit is a parity bit, which is not stored because parity is checked by a Hamming and parity checker HPC. Whenever a parity error occurs the checker HPC produces a -parity error- signal PE. The first two 8-bit words after the framing code on each data line are the magazine and row address group. These contain the row address and magazine address which are protected by Hamming codes. The data passes through the checker HPC, and Hamming corrected data (two 4-bit words) is clocked into row and magazine address latches RL and MIby pulses RA and MA from the bit counter BC.

The 'row address' output from the latch RL (5 bits) is the write row address information WRA which is used, as aforesaid, to determine where the display information DI is to be stored in the memory MEM. The 'row address' output from the latch RL is also applied 110 to a detector DRO which can detect the address of Row 0. When Row 0 (i.e. a pageheader) is detected, the detector DRO produces a signal which 'sets' (s) a flip-flop FF1.

The resulting signal from the flip-flop FF1 'enables' (e) a page comparator PC, 'resets' (rs) a second flip-flop FF2, and 'activates' (a) a write control element WC via an OR-gate OWC. When activated, the element WC pro- duces a 'write' signal WS to permit data in the detected page-header (Row 0) to be written into the memory MEM.

The 'magazine address' output from the latch ML (3 bits) is compared in a magazine address comparator MAC with a selected magazine address input which is, in effect, the 'hundreds' digit of a selected page number which has been entered by a user into a selected page latch SPL. If there is correspon- dence between the two magazine numbers, the comparator MAC produces a signal which 'enables' (e), a first input of an AND-gate AWC, allowing possible continued activation of the write control element WC beyond the reception of Row 0.

The information in the page-header (Row 0) following the magazine and row address group is page information containing two 4-bit words (after Hamming correction) which give the 'tens' and 'units' digits of the page number contained in the page- header (Row 0). The page comparator PC compares these two digits with the 'tens' and 'units' digits of the page number stored in the latch SPL, and if there is correspondence the page comparator PC produces a Signal which 'sets' the flip-flop FF2. Provided that the 'enable' signal from the comparator MAC is present, the resulting output signal from the flip-flop FF2 'activates' (a) the write control element WC (by opening the gate AWC) for all the following data-lines that contain the data rows of the selected page, until receipt of the next page-header (Row 0) causes the flip-flop FF2 to be reset by the flipflop FF1 and thereby terminate the writing action.

The writing into the memory MEM of the data in each following data row is conditional upon the presence of the 'enable' signal from the magazine address comparator MAC. This - ensures that when the rows of pages of different magazines are interleaved, only those data rows with the correct magazine number are accepted.

The flip-flop FF 'I is reset at the end of every data line by a 'reset' pulse RS from the bit counter BC.

The arrangement of Figure 4 also includes a third flip-flop FF3 which is 'set' (s) by a signal from the page selector latch SPL when a selected page number is initially entered therein. When set, the flip-flop FF3 it produces a signal which 'enables' (e) a first input of an ANDgate ANG. As soon as the flip-flop FF2 has been set on recognition of the selected page, it supplies a signal to open' (o) the gate ANG. An edge detector ED is operated by the leading edge of this output signal to 'reset' (rs) the flip-flop FF3, so that the gate ANG is open only briefly after flip-flop FF2 is set. The resulting signal at the output of gate ANG is applied through an OR-gate ORG as a pulse signal PS to 'set' (s) a fourth flip-flop FF4. Equivalently, the flip-flop FF4 can be 'set' (s) by a pulse signal PS produced from the gate ORG in response to a control bit (C4) which is contained in the page-header (Row 0) at a bit position after the page number bits. The purpose of this control bit is to allow a transmitting authority to initiate erasure of a page already stored in the page memory of the teletext decoders so as to allow for instance, for the new reception of the same page which contains updated information.

When the flip-flop FF4 is set by the pulse 6 GB2181928A 6 signal PS it switches a demultiplexer DIVI. This demultiplexer DM is normally in acondition in which it supplies a signal which 'inhibits' (i) the write control element WC, in response to a parity error signal PE as produced by the checker HPC when there is a parity error in a received data code for a character. This 'inhi bit' signal prevents writing into the relevant character position of the memory MEM. How ever, when the demultiplexer 13M is switched, it applies instead a 'force space' (fs) signal to a buffer BUF via which 7-bit words forming the display information DI are fed from the checker HPC for storage into the memory MEM. The effect of this signal (fs) is to cause the data code for a blank space to be written into the memory MEM at the character posi tion concerned, instead of the error data code.

This means that any data code already in the character position (because data in the mem ory MEM is not erased before the new page is stored) is over-written as a blank space. A time delay circuit TD is responsive to the pulse signal PS to produce a signal which 're sets' (rs) the flip-flop FF4 after a delay (e.g. 2 90 seconds) which is long enough for the first full reception of the selected page, but before any subsequent reception of the selected page oc curs. The demultiplexer DM then reverts to its original condition, so that writing is now inhi- 95 bited for subsequent receptions of character codes of the selected page that do not satisfy parity.

The pulse signal PS is also used to reset (rs) the 'row-found' latches L1 to L23. The Q- 100 outputs G1 to Q23 of the latches control the production of the display control signal 5/N in the manner already described with reference to Figure 2 or Figure 3. In the present ar40 rangement these latches L1 to L23 are set by 105 the output signals of AND-gates GAl' to GA23' which are 'enabled' (e) by respective output signals from a decoder BCD2' which, like the decoder BCD2 in Figure 2, is con- nected to receive the row address information 110 WRA of the selected page at its binary input bi. The row address pulse RA produced by the bit counter BC 'interrogates' (i) the gates GA l' to GA23' once per row period and the gate that is enabled opens to set the relevant 'row found' latch.

Figure 5 shows a modification of Figure 4: elements which are common to both Figures 4 and 5 have been given the same references.

In the modification of Figure 5, there is provided a further set of ANDgates G131 to GB23 which are associated respectively with the latches L1 to L23. Also, the row address pulse RA is now applied to the second inputs of the original gates GA l' to GA23' via two delay circuits TD1 and TD2 in series. The row address pulse RA is now also used to reset (rs) the flip-flop FF4. The operation of this modification is as follows. When a newly se- lected page has been found the pulse PS re- sets (rs) the latches L1 to L23, as before. The G-outputs of the latches L1 to L23 'enable' (e) a first input of a respective one of the gates G131 to G1323. In response to the first row address pulse RA, the flip-flop FF4 is reset (rs). After the delay imposed by the delay circuit TD1, the row address pulse RA is applied to 'enable' (e') a second input of all the gates GB1 to G1323. If a row address is re- ceived in the row period concerned, then the signal at the relevant output of the decoder BCD2' will 'open' (o) the particular one of the gates G131 to G1323, resulting in a signal which 'sets' (s) the flip-flop FF4 via an OR- gate ORG1. Thus, the demultiplexer DIV1 is switched to force blank space codes into any character location for which a parity error is detected in a character data code. When the next pulse RS is received, the flip-flop FF4 is reset (rs) and the demultiplexer DM reverts to its original condition to inhibit (i) writing when parity-errors are detected. The signal at the output of the decoder BCD2' also 'enables' (e) the relevant one of the gates GA 1' to GA2X. After the delay imposed by the delay circuit TD2 the row address pulse RA interrogates (i) to GA' gates and the gates opens to 'set' (s) the associated 'row found' latch. The Q-outputs Q1 to Q23 of the latches L1 to L23 again control the production of the display control signal D/N. When a latch is 'set' (s), its G-output is terminated to close the associated GB gate. Thus, in this modification, the forcing of blank space codes into character locations for parity errors is effected in respect of each row individually, rather than on an overall page basis as in the arrangement of Figure 4. Each of the delay circuits TD 'I and TD2 imposes only a few microseconds delay on the row address pulse RA. This modification allows good performance in the presence of errors to be achieved without any assumptions concerning the page transmission or magazine cycle times..

Claims (10)

1. A teletext decoder for use in a television receiver which is suitable for receiving television transmissions of a type in which coded data pulses representing alpha-numeric text for display or other teletext informatio.i are transmitted in a television signal in television lines where no picture signals representing normal picture information are present, the tel- etext information comprising pages which are transmitted in a recurrent cycle, each page comprising a plurality of data rows containing character data codes, of which rows the first data row as transmitted includes the page number and each data row includes an individual row address: said teletext decoder comprising means for selecting a page by its page number, means for detecting a selected page number when received, a page memory for storing the character data codes in each re- 9 7 GB2181928A 7 1 45 ceived data row of a selected page in respective character locations of a respective memory portion which is identified by the row address of the data row, the page memory being a random access memory into which character data codes can be written at the respective character locations and each data code can over-write and thereby replace any data code already written into its character location by a previous writing action, and character generator means responsive to data read from stored data rows to generate video signals appropriate for producing a visual display of the selected page; and said teletext decoder being characterised by further comprising display control means for permitting visual display only of the stored data rows of the selected page.

2. A teletext decoder as claimed in Claim 1, characterised in that said display control means comprises a "row-found" register having an individual flag position for each possible data row that a page can have adaptively, together with means for re-setting this register in response to the detection of the page number of a selected page, means for entering a flag into the relevant flag position for each received data row of the selected page, and means for inhibiting the display of any data row that does not have a flag in the flag position for that data row.

3. A teletext decoder as claimed in Claim 2, characterised in that the "row-found" register has a permanently set flag position for the data row that contains the page number.

4. A teletext decoder as claimed in Claim 2 or Claim 3, characterised in that the---rowfound- register is composed of a plurality of latches which form the individual flag positions of the register.

5. A teletext decoder as claimed in Claim 2 or Claim 3, characterised in that a portion of a memory device which forms the page memory serves as the "row-found" register.

6. A teletext decoder as claimed in any preceding Claim, for receiving teletext information in which data codes include a parity bit and the decoder includes means for checking the parity of each received data code, character- ised in that the decoder further includes error compensating means which are operable such that, following the detection of a selected page, a parity error in the first reception of a character data code will cause the data code for a blank space to be written into the page memory at the character location concerned, whereas on subsequent receptions of the character data code a parity error will cause a write inhibit condition to obtain.

7. A teletext decoder as claimed in Claim 6, characterised in that said error compensating means is arranged to be rendered operable at the beginning a page and to remain operable until after the reception of all the possible data rows of the page.

8. A teletext decoder as claimed in Claim 6, characterised in that said error compensating means is arranged to be rendered operable at the beginning of each possible data row of a page and to remain operable only until the end of the data row.

9. A teletext decoder substantially as hereinbefore described with reference to the accompanying drawings.

10. A television receiver embodying a teletext decoder as claimed in any preceding Claim.

Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd, Dd 8991685, 1987. Published at The Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.