GB2163627A - Error generator - Google Patents

Error generator Download PDF

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Publication number
GB2163627A
GB2163627A GB8521222A GB8521222A GB2163627A GB 2163627 A GB2163627 A GB 2163627A GB 8521222 A GB8521222 A GB 8521222A GB 8521222 A GB8521222 A GB 8521222A GB 2163627 A GB2163627 A GB 2163627A
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United Kingdom
Prior art keywords
bits
error
word
bit
output
Prior art date
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Granted
Application number
GB8521222A
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GB8521222D0 (en
GB2163627B (en
Inventor
Peter Michael Attkins
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British Telecommunications PLC
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British Telecommunications PLC
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Publication of GB8521222D0 publication Critical patent/GB8521222D0/en
Publication of GB2163627A publication Critical patent/GB2163627A/en
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Publication of GB2163627B publication Critical patent/GB2163627B/en
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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/24Testing correct operation
    • H04L1/242Testing correct operation by comparing a transmitted test signal with a locally generated replica
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/24Testing correct operation
    • H04L1/241Testing correct operation using pseudo-errors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic

Abstract

The output of a pseudo-random sequence generator (SR,X1) is fed to a comparator (CP1, M1) which produces an output when a selected number of bits of the generator output matches a comparison word (from CR1); the number of bits selected (by MR1) determines the error rate. Correlation problems are reduced by changing the comparison word (eg. by loading latch CR1 from counter LC incremented at clock rate) each time a match is found. <IMAGE>

Description

SPECIFICATION Error generation There are various types of random and pseudo random error generator principles. For example, a white noise source connected to a variable threshold comparator and sampling circuit will produce an output signal with probability altered by the threshold level. This type of generator has many failings such as; small noise power changes caused by temperature etc. will have a considerable effect on the error probability; the noise power bandwidth and comparator bandwidth must be many times greater than the sampling frequency-if this is not attained then there will be correlation between consecutive samples and the output signal will reflect this deficiency.
The most consistent and predictable error generators are based on digital techniques, ideally using random number generation. A realistic approach is to generate a long pseudo random sequence and use a digital word detector.
Assume that the generator consists of an n-bit shift register with feedback, and a w-bit word detector produces an output whenever a specified word appears in the output sequence.
The generator will produce 2"-1 unique words of n-bits (with exclusive OR feedback all zeros is illegal and with exclusive NOR feedback all ones is illegal). This is true for certain tap configurations only-some combinations will produce far fewer words. The word detector can 'look' for any w-bit word in the sequence except the illegal word therefore it is better to make w < n to avoid such a situation.
The probability of a w-bit word being detected is slightly greater than 2 W because there are only 2- 1words and not 2n. The difference depends on the actual value of n. An obvious limitation to this generator is that the probability values obtainable are in powers of 2 and not infinitely variable. In practice, however, there is normally more than enough resolution.
This method of error generation does produce the correct probability, but the nature of error distribution along the length of pseudorandom sequence is sequence related. For a given w-bit word the output sequence from the detector may be charged by altering the generator, for example by changing n or just changing the other shift resistor tap/taps and the word order will change. Similarly an exclusive NOR feedback would give a different distribution from exclusive OR. This is irrelvant if the distribution is reasonable anyway, but certain configurations may result in the output signals being bunched together and ten a long gap until the pattern repeats, especially when w approaches n.
Closer examination of a typical PRBSG will reveal another shortcoming of this type of error generator and that is of inter-word correlation similar to bandwidth limitation in a noise source based design. A PRBSG has word correlation at an interval of 2-n-i (a maximal length sequence)-this is ONLY for a one bit word though. If we use more than one bit there may be correlation over a much shorter interval. If, for example, the feedback is an EXCLUSIVE OR of shift register taps 28 and 31, the sequence is very long, but correlation will occur at intervals of Tap 28+1, Tap 31 + 1, Tap 31-Tap 28 because each new bit entering the shift register is related to bits 28 and 31 further down. It causes an unwanted distribution of output signals which gets worse as w increases from 2.
An error generator of this type is described in CCITT Study Group XVII Document No: 18, Annex 1 (14 July 1982). This uses a 31-bit register with exclusive or feedback from taps 28 and 31; a w-bit word detector produces an error output when taps 12 to (11+w) are all "1".
This error generator attempts to circumvent the problem of correlation by sub-sampling the PRBSG at a ratio of 1:32. This is achieved by clocking the generator 32 times between each test by the word detector thereby removing all correlations < 32. In practical terms the shift register clock is 2.048MHz while the sampling/data rate is 64KHz. The feedback taps used (Taps 28 and 31) produce a maximal length pseudo random binary sequence of length 231 - 1 bits or approximately 2.1X109 bits before a repeat of the sequence.
The sub-sampling rate cannot be a submultiple of the pattern length due to the - 1 term in 2"- 1 so the actual sub-sampled pattern would repeat approximately: 32X2.1X109 bits at 2.048Mbit/s (each pattern is 'short' bu 1 bit) 32 (sub-sampling rate) which is the same length as the original pattern of 2.1 X109 bits or a repetition once every 32812.5 seconds (9 hours approximately).
Unfortunately this sub-sampling only shifts the correlation intervals instead of eiiminating them.
Computer simulation of this error generator has been carried out and results are shown in Figs.
1 to 3 for an order w of 3, 7 and 10 respectively, the probability p of an interval of the samples between errors being plotted against tbe. Further data are set out below: Equivalent duration of % of test at errors 64kbit/s Total beyond Fig Order (w) Error Rate (seconds) Errors tbe=250 1 3 120X10-3 13 100,000 0 2 7 7.8X10 3 20 10,000 14 3 10 0.97X10 3 161 10,000 75 It will be observed that the output shows major correlation problems at intervals 63 and 64 and less important problems at higher intervals.If P(tbe) is the probability of consecutive errors occurring at an interval of the then: P(63)- 0 for all values of ORDER-ie. once an error has occurred it is certain that no error will occur 63 samples later P(64) > P(x) where x63 and x is 'near' to 64 for all values of ORDER For ORDER > 3:P(64) is 4 to 6 percent of the total error rate or there is roughly a 5 percent chance of an error being produced 64 bits after the previous error. This is clearly a failing of the error generation method.
The relationship between error probability/rates and equivalent mean-time-between-errors for 64 kbit/s data rates, and the ORDER of the system is as follows: ORDER=w Error probability (approximately)=2 Error rate 1 in 2 Equivalent mean-time between errors=2w/64000 (seconds) If the generator was set to ORDER =20 the mean time between errors would be 16s and this would be very like having a push-switch to generate a single error occasionally. One important difference though is that the generator will, about 5 percent of the time, produce a second error 64 bits (lems) later-the ear would detect this as a single disturbance of greater magnitude than one error.Therefore the transmission system under test may well sound worse than it should as some of the time the double errors will be considered, by the listener, to be single errors as indeed they should be. Any transmission system with data structure at a sub-multiple of 64 (byte derived systems such as PCM) could be affected by the problem at P(64) and any system which has framing information will not respond to a given error in the same manner as it would with properly (randomly) distributed errors. Indeed it may be possible to build transmission systems which deliberately respond very favourably to the error injector and thereby give a better measured performance than they would otherwise.
According to the present invention there is provided a variable probability error generator comprising a pseudo-random sequence generator (SR,X1) and detector means (CP1, CP2) arranged to examine a selected number of bits of the generated sequence and to produce an output upon recognition that those bits correspond to a comparison word, characterised by modification means (LC, CR1, CR2) operable, following each such recognition, to change the comparison word.
Some embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figures 1 to 3 are graphs illustrating the performance of a known error generator; Figures 4 and 5 are block diagrams of two alternative error generators according to the invention; Figures 6 to 8 are graphs illustrating the performance of the generator of Fig. 5; and Figure 9 is a flowchart illustrating a third embodiment of the invention.
Referring to Fig. 4, a pseudo random binary sequence generator is formed by a shift register SR having feedback via an exclusive-or gate X1 from taps 5 and 23, giving a pattern length of more than 8 million bits. The register is loaded initially (by means not shown) with a non-zero number to ensure proper startup. The first W taps are used in conjunction with a w-bit word detector where w is less than or equal to W. The errors output are injected into the incoming data stream with an exclusive OR gate X2.
It is the implementation of the w-bit word detector that controls the performance of the error generator with regard to distribution of time between errors, the problems with conventional generators having been shown already. In Fig. 4, the W bits are compared bit by bit in comparator CP1 with a comparison word stored in a latch CR1. The outputs of the comparator are fed to a masker M1 in which the first w bits are AND-ed to form the output; the remainder if any being forced to 1 by the output of a latch MR1 by presetting appropriate bits of the latter.
This generator does not even attempt to employ sub-sampling techniques, instead, the w-bit word detector uses a variable word for its comparison. Conventional generators use a fixed word-the actual word will affect the error distribution, but any fixed word produces an unwanted distribution similar to the graphs shown in Figs. 1 to 3 (this used 'all ones' as the word). Using a variable word overcomes the correlation problem providing that the word is not directly related to the sequence. The word is charged each time the w-bit word detector produces an output, the new word being stored in the latch CR1 and is the value of a modulo 256 counter LC clocked by the data rate clock f.
Fig. 5 shows a modified version, in which the word detector examines up to 16 bits (ie.
W=16). The lower 8 bits are dealt with in the same way as in Fig. 4, whilst the upper 8 are compared in comparator CP2 with a separate comparison word from an 8-bit modulo 256 down counter CR2, decremented by the equal output of the comparator. The comparator output is masked by masker M2 and mask register MR2 and the output combined with that of MR1 in an AND gate Al.
The error rate selection is controlled by the mask registers MR2, MR1 eg: ORDER MR2 MR1 COMMENT 1 00000000 00000001 Look at tap 1 only 13 00011111 11111111 Look at tap 1 to tap 13 Note however that the bits set do not have to be consecutive; any pattern can be used provided the total number of bits set to 1 is w.
These values are used by the 8-bit maskers to select only the required taps for the selected ORDER. A 'zero' mask bit means-assume the corresponding tap was equal to the compare register bit value (ignore it). A 'one' means pass the comparator value to the equal detector in the masker. Note that this is the reverse convention to that employed in Fig. 4. Thus if w is less than or equal to 8, then operation is identical to that of Fig. 4; if w is greater than 8 then the upper half of the detector is used. The upper EQUAL O/P will detect w-8 bits from the PRBSG (the detector always 'looks' at tap 1 to tap w) and when equality is found then the upper 8-bit word is decremented by one. Obviously to produce an error output both halves of the word detector must be presented with their correct words simultaneously.
Computer generated results for the arrangement of Figs. 5 are shown in Fig. 6 to 8 (Figs. 6 and 7 are also valid for the version of Fig. 4, of course). Further data are as follows: Equivalent duration of % of test at errors 64kbit/s Total beyond Fig Order (w) Error Rate (seconds) Errors tbe=250 6 3 120X10 3 13 10,000 0 7 7 7.9X10 3 198 10,000 14 8 10 0.97X10 3 1610 10,000 78 It will be observed that there are no zero probability points, and that there are no longer any excessively high probability points. Fig. 8 shows a wider variation than the others but this is due to the low error rate in relation to the duration of the test and would also be seen for a true random sequence. It is found that the graph "smoothes" as the test is continued.
It should also be noted that the vertical scales of the graphs of Figs. 6 to 8 are different from those of Figs. 1 to 3. Interestingly, the differences between the two sets of results cannot be discerned using a spectrum analyser.
As well as the substantial improvement in probability distribution, the generators described also have the advantage, compared with generators using sub-sampling, of not requiring logic operating at rates in excess of the data clock rate. Whilst this would be of importance in the hardware versions described only in the case of extremely high data rates, it is significant for the microprocessor based version described below. Using a Motorola 68000 microprocessor with an 8 MHz processor clock, programmed in machine code, it has been found tlhat it is possible to achieve real-time error generation for 64kbit/s data. Were sub-sampling employed, this would not be possible.
A microprocessor-based version has also been implemented on an 8-bit Intel 8051 microcontroller chip. The prime requirement was for speed of execution as the application was a 1 6kbit/s error injector. The microcontroller will produce errors at 32kbit/s, but it is insufficiently fast for 64kbit/s. All practical tests (to conform the simulation) were performed at 16kit/$. A flowchart for this implementation is shown in Fig. 9.
This uses the same algorithm as embodied in the hardware version of Fig. 5. The same references are used to refer to the CPU registers (or memory locations) as were used to refer to the register of Fig. 5. The 23-bit shift registers BR is represented by three 8-bit registers as follows: SR1:-tap 1 -tap 8 SR2:-tap 9 -tap 15 SR3:-tap 16-tap 24 Only those steps of the flowchart which are not self-explanatory are discussed below 2 Initialise: Set SR1=5; SR2=SR3=0 CR1=CR2=O LC =0 Mask registers filled with N ones starting from the I.s.b of MR1 3 The loop counter is incremented.
When listening to speech over a 64kbit/s transmission system a single error may be noticed; however, there is little point in using an error generator with an order greater than 20 because it would approximate single errors.

Claims (5)

1. A variable probability error generator comprising a pseudo-random sequence generator (SR,X1) and detector means (CP1, CP2) arranged to examine a selected number of bits of the generated sequence and to produce an output upon recognition that those bits correspond to a comparison word, characterised by modification means (LC, CR1, CR2) operable, following each such recognition, to change the comparison word.
2. An error generator according to claim 1 characterised in that the detector means is arranged to examine the selected number of consecutivie bits of the generated sequence.
3. An error generator according to Claim 2 characterised in that the detector means is arranged, for each bit of the generated sequence, to examine that bit and the appropriate number of succeeding bits.
4. An error generator according to claim 2 or claim 3 characterised in that the modification means is arranged, upon such recognition, to make the comparison word, considered as a binary number, is made equal to the number of comparisons, counted modulo-sw, where w is the selected number of bits, which have occurred since an arbitary datum point.
5. An error generator substantially as herein described with reference to the accompanying drawings.
GB8521222A 1984-08-24 1985-08-23 Error generator Expired GB2163627B (en)

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GB8421500A GB8421500D0 (en) 1984-08-24 1984-08-24 Error generation

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GB2163627A true GB2163627A (en) 1986-02-26
GB2163627B GB2163627B (en) 1988-04-07

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046036A (en) * 1984-10-15 1991-09-03 International Business Machines Corporation Pseudorandom number generator
GB2291234A (en) * 1994-07-15 1996-01-17 Ando Electric Pseudo-random pattern generating circuit
WO1998006175A1 (en) * 1996-08-06 1998-02-12 Amersham International Plc Method of and apparatus for generating random numbers
DE19717110A1 (en) * 1997-04-23 1998-10-29 Siemens Ag Circuit arrangement for generating a pseudo-random sequence
EP1130865A1 (en) * 1998-11-11 2001-09-05 Kabushiki Kaisha Kenwood Dummy error addition circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2131183A (en) * 1982-11-30 1984-06-13 Sony Corp Digital random error generators

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2131183A (en) * 1982-11-30 1984-06-13 Sony Corp Digital random error generators

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046036A (en) * 1984-10-15 1991-09-03 International Business Machines Corporation Pseudorandom number generator
GB2291234A (en) * 1994-07-15 1996-01-17 Ando Electric Pseudo-random pattern generating circuit
US5638309A (en) * 1994-07-15 1997-06-10 Ando Electric Co., Ltd. Pseudo-random pattern generating circuit
GB2291234B (en) * 1994-07-15 1998-01-28 Ando Electric Pseudo-random pattern generating circuit
WO1998006175A1 (en) * 1996-08-06 1998-02-12 Amersham International Plc Method of and apparatus for generating random numbers
EP0828349A1 (en) * 1996-08-06 1998-03-11 AMERSHAM INTERNATIONAL plc Method of and apparatus for generating random numbers
US6415309B1 (en) 1996-08-06 2002-07-02 Mark G. Shilton Method of and apparatus for generating random numbers
DE19717110A1 (en) * 1997-04-23 1998-10-29 Siemens Ag Circuit arrangement for generating a pseudo-random sequence
DE19717110C2 (en) * 1997-04-23 2000-11-23 Siemens Ag Circuit arrangement for generating a pseudo-random sequence
EP1130865A1 (en) * 1998-11-11 2001-09-05 Kabushiki Kaisha Kenwood Dummy error addition circuit
EP1130865A4 (en) * 1998-11-11 2005-09-28 Kenwood Corp Dummy error addition circuit

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Publication number Publication date
GB8421500D0 (en) 1984-09-26
GB8521222D0 (en) 1985-10-02
GB2163627B (en) 1988-04-07

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