GB2159963A

GB2159963A - Measuring rate of change of frequency

Info

Publication number: GB2159963A
Application number: GB08510696A
Authority: GB
Inventors: John William Warin
Original assignee: Northern Engineering Industries PLC
Current assignee: Rolls Royce Power Engineering PLC
Priority date: 1984-05-19
Filing date: 1985-04-26
Publication date: 1985-12-11
Also published as: GB8510696D0; GB2159010A; GB2159010B; GB2159963B; GB8510695D0; GB8412856D0

Abstract

A repeatedly updated signal indicative of rate of change of frequency in an electricity supply system is obtained by repeatedly counting at 10 a number such as ten of cycles of a phase of the supply from 24 to determine an indexing period at 12 during which high frequency clock pulses from 14 are counted at 16. Clock pulse counts for successive indexing, periods are stored in respective locations of store 18, the index count from 12 serving to remove the oldest and add the newest count from 16. The difference between the oldest stored count and the median stored count and between the median stored count and the newest stored count are substrated at 20 to give the rate of change of frequency signal at 22. To derive the indexing periods 12 related to the supply phase input to circuit 24 but insensitive to spikes thereon, the circuit 24 gates oscillator pulses from 28 to counters 30, 32 during positive and negative half cycles. These each reset after a predetermined count and cause a bistable 34 to set and reset. This generates in effect a squared and delayed version of the input to be counted down at 12. <IMAGE>

Description

1 GB 2 159 963 A 1

SPECIFICATION

Rate of change of frequency detection in electricity supplies The invention relates to the detection of rate of change of frequency in electricity supplies.

According to one aspect of the invention, a method of obtaining a repeatedly updated signal indicative of rate of change of frequency in an electricity supply system comprises repeatedly counting a number of cycles of a phase of the supply equal to a predetermined number of cycles to determine periods during which high frequency time pulses are counted, storing at least three successive counts of time pulses and discarding the oldest count as the newest count is stored and obtaining a signal indicative of the rate of change of frequency by subtracting the differences between the oldest stored count and the median stored count and the median stored count and the newest stored count.

According to another aspect of the invention, apparatus for obtaining a repeatedly updated signal indicative of rate of change of frequency in an electricity supply system comprises a first generator for generating cycles directly proportional to the cycles of a phase of the supply, a first counter for counting the cycles generated by the first gen- erator, a second generator for generating high frequency time pulses, a second counter for counting the time pulses, a count store for storing at least three successive counts of time pulses, the store being indexable by the first counter when a prede- termined number of cycles has been counted to discard the oldest stored count and to store the count in the second counter and means for subtracting the differences between the oldest stored count and the median stored count and the median stored count and the newest stored count to obtain a signal indicative of rate of change of frequency of the supply.

Apparatus will now be described to illustrate the invention by way of example only with reference to the accompanying drawing which is a schematic block diagram of apparatus in accordance with the invention.

The apparatus has a generator 10 for generating cycles directly proportional to the voltage cycles of a phase of the electricity supplied by an alternator of an alternator system, for example, which is connected in parallel with a grid; a counter 12 for counting the cycles generated by the generator 10; a generator in the form of a high frequency oscilla- tor 14 for generating time pulses; a counter 16 for counting the time pulses produced by the oscillator 14; a count store 18; and a processor means 20.

The generator 10 has a comparator 24 for deter mining when the voltage half cycles are positive and negative. The comparator 24 operates a solidstate switch 26 controlling the output of a 2MHz oscillator 28. The output of the oscillator 28 passes to a counter 30 during the positive half cycles and to a counter 32 during the negative half cycles. The counters 30 and 32 are each arranged to count up to 2 14 during the respective half cycles.

When the counter 30 reaches a count of 214, it sets a bistable switch 34 to the "on" state which, in turn, locks a counter 30 into a reset (count =0) condition and removes a reset signal from counter 32. As soon as the voltage cycle becomes negative counter 32 begins to count and when it reaches a count of 214 it resets the bistable switch to the 11 off" state which, in turn, locks the counter into a reset condition and removes the reset signal from counter 30.

The effect is to produce "on" and "off" states in synchronism with the voltage half cycles but delayed by 21;1 microseconds. However, transitory ex- cursions of the waveform, caused by mains borne spikes for example, do not get counted as a cycle but merely introduce a timing error equal to the time for which the excursion causes the voltage to be of wrong polarity. The delayed synchronisation of the generated cycles with the voltage cycles is re-established in the next half cycle or full cycle assurning a further excursion does not occur.

The generated cycles are counted by the counter 12 which is a programmable downcounter. The counter 12 can be programmed to index the count store 18 at a suitable number of cycles, say every 10 cycles.

The oscillator 14 produces high frequency time pulses, for example 18000 Hz and the counter 16 counts the pulses continuously. When the counter capacity is reached, the counter returns to zero and continues counting upwardly again.

When the store 18, which holds eleven successive counts, is indexed by the counter 12, the counter 16 is stopped, the oldest count in the store is discarded, the remaining ten counts are shifted through the store 18 and the figure in the counter 16 is introduced into the store 18. The counter 16 then starts counting again.

The processor means 20 is arranged to ignore the highest and lowest significant figures of the counts and to subtract the differences between the oldest and the median and the median and the newest counts to obtain a signal indicative of rate of change of frequency. If the result of the difference between the counts would be negative, the processor means takes a unit from the next higher significant figure and adds it to the lower number before performing the subtraction so that a posi- tive result is obtained.

The process is repeated each time the store 18 is indexed by the counter 12 so that the signal is repeatedly updated.

If necessary, the processor means 20 is used to perform subsequent operations with the signal so obtained.

The number of counts held in the store 18 can be as low as three. If an even number of counts are used, the median count is taken to be the two adjacent middle counts, respectively. For example, if eights counts were stored, the processor would subtract the difference between counts 1 and 4 and counts 5 and 8.

Typically, the signal indicative of rate of change of frequency of the electricity supply produced by 2 GB 2 159 963 A 2 the processor means 20 can be used to isolate an alternator from the grid if the grid is disconnected from the alternator as is described and claimed in our co-pending Application No. 85 10695 (Appil5 cants' reference AP-AL 1343A).

Claims

1. A method of obtaining a repeatedly updated signal indicative of rate of change of frequency in an electricity supply system comprising repeatedly counting a number of cycles of a phase of the supply equal to a predetermined number of cycles to determine periods during which high frequency time pulses are counted, storing at least three successive counts of time pulses and discarding the oldest count as the newest count is stored and obtaining a signal indicative of the rate of change of frequency by subtracting the differences between the oldest stored count and the median stored count and the median stored count and the newest stored count.

2. Apparatus for obtaining a repeatedly updated signal indicative of rate of change of frequency in an electricity supply system comprising a first generator for generating cycles directly proportional to the cycles of a phase of the supply, a first counter for counting the cycles generated by the first generator, a second generator for generating high fre- quency time pulses, a second counter for counting the time pulses, a count store for storing at least three successive counts of time pulses, the store being indexed by the first counter when a predetermined number of cycles has been counted to discard the oldest stored count and to store the count in the second counter and means for subtracting the differences between the oldest stored count and the median stored count and the median stored count and the newest stored count to obtain a signal indicative of rate of change of frequency of the supply

3. Apparatus according to claim 2, in which the first generator comprises a comparator for determining when the supply half cycles are positive and negative, a first switch controlled by the cornparator, a high frequency oscillator, first and second counters and a second bistable switch, the output from the oscillator being passed by the first switch to the first and second counters, respec- tively, when the comparator detects positive and negative half cycles, respectively, the output from the first counter, when the first counter reaches a predetermined count in its respective positive half cycle, setting the bistable switch to the "on" state which, in turn, locks the first counter in a reset condition and removes a reset signal from the second counter and the output from the second counter, when the second counter reaches a predetermined count in its respective negative half cycle, setting the bistable switch to the "off" state which, in turn, locks the second counter in a reset condition and removes a reset signal from the first counter.

4. A method according to claim 1 substantially as hereinbefore described with reference to the ac- companying drawing.

5. Apparatus according to claim 2 substantially as hereinbefore described with reference to the accompanying drawing.

Printed in the UK for HMSO, D8818935, 10i85. 7102. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.

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